[ECOS] Question about clock tick in ecos? Thanks

Nick Garnett nickg@ecoscentric.com
Fri Jan 31 18:12:00 GMT 2003

"Qiang Huang" <jameshq@liverpool.ac.uk> writes:

> Q1. so should the *tick interrupt* happens just after the exit of the
> IRQ1( around 1ms after the tick should happen but not happen) ?


> Q2. or no *tick interrupt* until the after 10ms as indicated in the
> graph?


> Q3. If the timer is freely running the during the time of IRQ1 timer will
> get to the limit and set the flag bit but not interrupt to the
> microprocessor because irq is disabled while processing the IRQ1, if nothing
> has done to clear the flag bit of the timer, it will triger the interrupt
> after execution exits from IRQ1, Is this correct?


> Q4. so the tick interrupt will happen at around 2ms, this will make the
> system heart beat not at 10ms, Is this correct?

Yes. For this particular instance the timer interrupt will be later
than normal. This is an expected consequence of the choice of
interrupt priorities. If you want timer interrupts to be perfectly
regular then it must be higher priority than any others, and you must
enable interrupt nesting.

> Q5. if not should we clear the timer flag bit before the higher priority IRQ
> exit when the counter already reach the limit during the IRQ?

That would simply result in the timer interrupt being missed. I don't
see what that would gain us.

Nick Garnett - eCos Kernel Architect

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