[ECOS] Possible typo in hal/arm/arm9/var/current/include/hal_cache.h

[Jonathan Larmour]

Patrick Doyle wrote:
> Can somebody (jskov perhaps, since your name is in the ChangeLog)

I'm not sure Jesper still reads ecos-discuss. I think he doesn't any more 
unfortunately.

> tell me
> the source of the data for the ARM925T cache configuration?  I am asking
> because the #defines in this file don't match the documentation I have from
> TI.  I will ask TI as well, but in the mean time, here is what the file
> says:
> 
> # define HAL_ICACHE_SIZE                 0x4000
> # define HAL_ICACHE_LINE_SIZE            32
> # define HAL_ICACHE_WAYS                 2
> # define HAL_ICACHE_SETS
> (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
> 
> And here is what the TI documentation (somewhat ambiguously) says:
> 
> "The 16K-byte instruction cache (I-cache) has 1024 lines of 16 bytes
> arranged as a two-way set-associative cache."

I notice hal_arm_arm9.cdl says:
             The ARM925T has 8k data cache, 16k instruction cache, 16 word
             write buffer and an MMU."

> These two pieces of information clearly differ in the definition of the line
> size.  Also, my first read of the TI documentation made me think there were
> 1024 lines in each set, but the math doesn't work out for that.  Instead, I
> think there are 1024 lines total, 512 in each set.  Regardless, these don't
> match the 256 sets defined by HAL_ICACHE_SETS.

The board this was written for was never released publically, but was from 
TI. I believe this is the CPU: http://www-s.ti.com/sc/ds/omap5910.pdf and 
more relevantly 
<http://focus.ti.com/docs/prod/productfolder.jhtml?genericPartNumber=OMAP5910&pfsection=user_man>
which includes the very paragraph you mention!

So I'm inclined to believe it's wrong, and a patch is welcome :-).

> Anyway, I thought I would ask here as well as at TI.  All comments are
> welcome.

If you've got the hardware you could play around! At least to verify that 
it's wrong.

Jifl
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