[ECOS] Possible typo in hal/arm/arm9/var/current/include/hal_cache.h

Patrick Doyle wpd@delcomsys.com
Tue Jan 7 18:53:00 GMT 2003


Can somebody (jskov perhaps, since your name is in the ChangeLog) tell me
the source of the data for the ARM925T cache configuration?  I am asking
because the #defines in this file don't match the documentation I have from
TI.  I will ask TI as well, but in the mean time, here is what the file
says:

# define HAL_ICACHE_SIZE                 0x4000
# define HAL_ICACHE_LINE_SIZE            32
# define HAL_ICACHE_WAYS                 2
# define HAL_ICACHE_SETS
(HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))

And here is what the TI documentation (somewhat ambiguously) says:

"The 16K-byte instruction cache (I-cache) has 1024 lines of 16 bytes
arranged as a two-way set-associative cache."

These two pieces of information clearly differ in the definition of the line
size.  Also, my first read of the TI documentation made me think there were
1024 lines in each set, but the math doesn't work out for that.  Instead, I
think there are 1024 lines total, 512 in each set.  Regardless, these don't
match the 256 sets defined by HAL_ICACHE_SETS.

Anyway, I thought I would ask here as well as at TI.  All comments are
welcome.

--wpd


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