[ECOS] What portions of eCos code can be locked in instruction cache

[Michael Anburaj]

Sandeep,

Sometime back on an ARM920T with slow SRAM memory we had a problem with a 
certain ISR. It demanded a very quick response, latency lesser than 2us. And 
when we measured it using a logic analyzer it was randomly swinging between 
8-30us. Moving this to FIQ (ARMÂ’s special fast IRQ option) did not help 
much. So, I locked down the entire ISR path right from the HW vectors, 1st 
level handler & the ISR into the I-Cache & the latency dropped down to <1us 
(consistent).

This was one such situation; I guess different devices may have different 
cache lockdown requirements.

Hope this gives an idea,
-Mike.


>From: "sandeep" <sandeep@codito.com>
>To: <ecos-discuss@sources.redhat.com>
>Subject: [ECOS] What portions of eCos code can be locked in instruction 
>cache
>Date: Thu, 18 Dec 2003 19:46:38 +0530
>
>hi list,
>
>in case you happen to get eCos working on a chip that has support for
>instruction cache locking, what portions of eCos kernel would you suggest 
>should
>be locked there for optimal performance?
>
>* HAL code that gets called often viz. context switch code, 
>interrupt/exception
>handling code
>* roughly what section of network code?
>* what part of kernel code? apart from scheduler related code, unlock_inner
>function, isrs/dsrs
>
>to instruction-cache-lock certain non-HAL code some changes may have to be 
>made
>to non-HAL code in eCos, eg. may be marking some functions with special
>attributes. to what extents it is fine to modify the non-HAL eCos code? 
>surely
>coz of this syncing with global eCos CVS is going to be bit of hassles than
>otherwise.
>
>hoping to get your views.
>
>peace
>sandeep
>
>
>
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