[ECOS] PCI Ethernet card

[Raghu BK]

Hi Mike/Eric,

I've a custom board based on XScale 255, PCI Bridge IT8152 and RTL8139. I'm 
in the process of porting RedBoot to this platform. I would really 
appreciate if you could share the RTL8139 controller driver with me.

Mike: Since you already ported Eric's driver to Redboot, could you please 
share the driver code you ported with me? This would cut short my 
development time and your driver would be validated on one more platform. 
I'll keep you folks updated on the status.

Thanks in Advance,
Raghu


>From: Eric Doenges <Eric.Doenges@DynaPel.com>
>To: Michael Anburaj <embeddedeng@hotmail.com>
>CC: Eric.Doenges@DynaPel.de, 
>gary@mlbassoc.com,ecos-discuss@sources.redhat.com
>Subject: Re: [ECOS] PCI Ethernet card
>Date: Wed, 20 Aug 2003 09:49:02 +0200
>
>Michael Anburaj wrote:
>
>>I found the problem & fixed it.
>
>Great !
>
>>
>>Problem:
>>-----------
>>
>>I displayed the value of ?header? each time after the following line of 
>>code at rltk8139_deliver():
>>
>>header = HAL_LE32TOC(*((cyg_uint32 *)&rltk8139_info->rx_ring[rx_pos]));
>>
>>And it was most of the time = 0x0.
>>I initially guessed that probably the Rx_Ring_buffer was not setup right. 
>>But, the actual problem was with the caches < cache coherency -same issue 
>>that Gary Thomas addressed in one of the emails sent to ecos-patches >. 
>>So, I pulled revision 3 of your driver & also defined 
>>CYGPKG_DEVS_ETH_RLTK_8139_SOFTWARE_CACHE_COHERENCY in my platform-specific 
>>.inl file. It worked well & got the IP parameters in 1 shot from the DHCP 
>>server. Right now it?s configured as eth0 interface, I will try making it 
>>eth1. Thanks a lot to you and all who participated in this discussion.
>>
>>FYI: I exchanged my PCI 2.2 compliant <with WOL> NIC with a PCI 2.1 one, 
>>but having the same chip - RTL8139D.
>
>It's nice to hear that my code actually works 8^). What I find so
>interesting is that carefull analysis of the MMU configuration of my
>hardware platform leads me to believe that cache coherency must be
>handled in software (there is no special uncached address space or bus
>snooping logic), yet the driver works well without it. I guess this just
>proves how beneficial it is to make code open source so it can be
>tested on many different platforms by many different people ...
>
>Ome more thing that you might have already done yourself - since my
>third revision of the driver I've found a simple way to ensure that the 
>buffers used are actually placed on cache line boundaries. In your
>platform-specific .inl-File, add the following definition:
>
>#define CACHE_ALIGNED __attribute__ ((aligned (HAL_DCACHE_LINE_SIZE)))
>
>Then, use this attribute on the transmit and receive buffer
>definitions:
>
>static cyg_uint8 rltk8139_eth0_rx_ring[RX_BUF_TOT_LEN] CACHE_ALIGNED;
>
>Note that this might fail for long cache lines. Gcc documentation
>unfortunately does not specify what the maximum allowed value for
>the 'aligned' attribute is, and it also seems to be linker specific.
>(This information will go into the README for the fourth revision,
>planned for release when either a bug is fixed, a feature added, or
>the acknowledgement of the copyright assignment to RedHat arrives,
>in which case I plan to hand the driver over to the eCos maintainers).
>--
>--------------------------------------------------------------------
>|     Eric Doenges              |     DynaPel Laboratories GmbH    |
>|     Tel: +49 89 962428 23     |     Fraunhoferstrasse 9/2        |
>|     Fax: +49 89 962428 90     |     D - 85737 Ismaning, Germany  |
>--------------------------------------------------------------------
>
>
>--
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>and search the list archive: http://sources.redhat.com/ml/ecos-discuss
>

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