[ECOS] eCos on NET+50
Peter Vandenabeele
peter.vandenabeele@mind.be
Wed Oct 30 09:39:00 GMT 2002
On Sat, Oct 19, 2002 at 01:35:42PM +0200, Peter Vandenabeele wrote:
> On Sat, Oct 19, 2002 at 04:59:35AM +0100, Jonathan Larmour wrote:
> > Olaf Peters wrote:
> > > Hi,
> > >
> > > I sucessfully and happily run eCos on an AMD-520 processor. Now I need
> > > some OS+TCP/IP for a custom NET+ARM board (the NET+50 processor from
> > > NetSilicon). In the latest CVS snapshot it seems not supported, are
> > > there any patches available somewhere?
> >
> > There are enough ARM7 ports around it shouldn't be that mammoth a task.
> > Another option is to approach NetSilicon and, as a customer, persuade them
> > to pay for an eCos port.
>
> We did an internal eCos port on a Net+ARM 50 Development System we received for
> this purpose from NetSilicon [...]
The patch for the Net+ARM 50 is attached. It was tested on the NetSilicon Net+50
evaluation board.
I made a mistake in that I assumed we also had support for the Ethernet
included, but that is not the case, sorry. If required, that additional
Ethernet support can be provided by any of the commercial providers of
eCos support (Navosha, eCosCentric, Mind).
I have made the patch available on our ftp server (ftp.mind.be).
Sincerely,
Peter Vandenabeele
--
Mind: Embedded Linux, eCos and JVM Development in Europe
Mind (http://mind.be) tel: +32-16-30.96.66
-------------- next part --------------
diff -urN -x CVS -x doc -x ChangeLog -x powerpc ecos/packages/cygmon/current/misc/arm/cpu.h ecos.my/packages/cygmon/current/misc/arm/cpu.h
--- ecos/packages/cygmon/current/misc/arm/cpu.h 2002-05-24 01:00:18.000000000 +0200
+++ ecos.my/packages/cygmon/current/misc/arm/cpu.h 2002-10-25 14:52:14.000000000 +0200
@@ -301,7 +301,7 @@
#define _r14 lr
#define _pc pc
#define _cpsr cpsr
-#define _spsvc msr
+#define _spsvc svc_sp
#else
typedef struct
{
diff -urN -x CVS -x doc -x ChangeLog -x powerpc ecos/packages/devs/serial/arm/netarm/current/cdl/ser_arm_netarm.cdl ecos.my/packages/devs/serial/arm/netarm/current/cdl/ser_arm_netarm.cdl
--- ecos/packages/devs/serial/arm/netarm/current/cdl/ser_arm_netarm.cdl 1970-01-01 01:00:00.000000000 +0100
+++ ecos.my/packages/devs/serial/arm/netarm/current/cdl/ser_arm_netarm.cdl 2002-10-26 22:40:19.000000000 +0200
@@ -0,0 +1,176 @@
+# ====================================================================
+#
+# ser_arm_netarm.cdl
+#
+# eCos serial NET+ARM configuration data
+#
+# ====================================================================
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s): Peter De Schrijver (p2@mind.be)
+# Original data: Peter De Schrijver (p2@mind.be)
+# Contributors:
+# Date: 2002-10-25
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+cdl_package CYGPKG_IO_SERIAL_ARM_NETARM {
+ display "NET+ARM serial device drivers"
+
+ parent CYGPKG_IO_SERIAL_DEVICES
+ active_if CYGPKG_IO_SERIAL
+ active_if CYGPKG_HAL_ARM_NETARM
+
+ requires CYGPKG_ERROR
+ include_dir cyg/io
+ include_files ; # none _exported_ whatsoever
+ description "
+ This option enables the serial device drivers for the
+ NetSilicon NET+ARM."
+ doc redirect/ecos-device-drivers.html
+
+ compile -library=libextras.a netarm_serial.c
+
+ implements CYGINT_IO_SERIAL_BLOCK_TRANSFER
+
+ define_proc {
+ puts $::cdl_system_header "/***** serial driver proc output start *****/"
+ puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HEADER <pkgconf/io_serial_arm_netarm.h>"
+ puts $::cdl_system_header "/***** serial driver proc output end *****/"
+ }
+
+cdl_component CYGPKG_IO_SERIAL_ARM_NETARM_SERIAL1 {
+ display "NetSilicon NET+ARM serial port 1 driver"
+ flavor bool
+ default_value 1
+ description "
+ This option includes the serial device driver for the NetSilion NET+ARM
+ port 1."
+
+ cdl_option CYGDAT_IO_SERIAL_ARM_NETARM_SERIAL1_NAME {
+ display "Device name for the NetSilicon NET+ARM serial port 1 driver"
+ flavor data
+ default_value {"\"/dev/ser0\""}
+ description "
+ This option specifies the name of serial device for the NET+ARM port 1."
+ }
+
+ cdl_option CYGNUM_IO_SERIAL_ARM_NETARM_SERIAL1_BAUD {
+ display "Baud rate for the NetSilicon NET+ARM serial port 1 driver"
+ flavor data
+ legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600
+ 4800 7200 9600 14400 19200 38400 57600 115200 230400
+ }
+ default_value 38400
+ description "
+ This option specifies the default baud rate (speed) for the NetARM
+ port 1."
+ }
+
+ cdl_option CYGNUM_IO_SERIAL_ARM_NETARM_SERIAL1_BUFSIZE {
+ display "Buffer size for the NetSilicon NET+ARM serial port 1 driver"
+ flavor data
+ default_value 128
+ legal_values 0 to 8192
+ description "
+ This option specifies the size of the internal buffers used
+ for the NET+ARM port 1."
+ }
+}
+
+cdl_component CYGPKG_IO_SERIAL_ARM_NETARM_SERIAL2 {
+ display "NetSilicon NET+ARM serial port 2 driver"
+ flavor bool
+ default_value 1
+ description "
+ This option includes the serial device driver for the NET+ARM port 2."
+
+ cdl_option CYGDAT_IO_SERIAL_ARM_NETARM_SERIAL2_NAME {
+ display "Device name for the NET+ARM serial port 2 driver"
+ flavor data
+ default_value {"\"/dev/ser1\""}
+ description "
+ This option specifies the name of serial device for the NET+ARM
+ port 2."
+ }
+
+ cdl_option CYGNUM_IO_SERIAL_ARM_NETARM_SERIAL2_BAUD {
+ display "Baud rate for the NET+ARM serial port 2 driver"
+ flavor data
+ legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600
+ 4800 7200 9600 14400 19200 38400 57600 115200 230400
+ }
+ default_value 38400
+ description "
+ This option specifies the default baud rate (speed) for the
+ NET+ARM port 2."
+ }
+
+ cdl_option CYGNUM_IO_SERIAL_ARM_NETARM_SERIAL2_BUFSIZE {
+ display "Buffer size for the NET+ARM serial port 2 driver"
+ flavor data
+ legal_values 0 to 8192
+ default_value 128
+ description "
+ This option specifies the size of the internal buffers used for
+ the NET+ARM port 2."
+ }
+}
+
+ cdl_component CYGPKG_IO_SERIAL_ARM_NETARM_OPTIONS {
+ display "Serial device driver build options"
+ flavor none
+ description "
+ Package specific build options including control over
+ compiler flags used only in building this package,
+ and details of which tests are built."
+
+
+ cdl_option CYGPKG_IO_SERIAL_ARM_NETARM_CFLAGS_ADD {
+ display "Additional compiler flags"
+ flavor data
+ no_define
+ default_value { "" }
+ description "
+ This option modifies the set of compiler flags for
+ building these serial device drivers. These flags are used in addition
+ to the set of global flags."
+ }
+
+ cdl_option CYGPKG_IO_SERIAL_ARM_NETARM_CFLAGS_REMOVE {
+ display "Suppressed compiler flags"
+ flavor data
+ no_define
+ default_value { "" }
+ description "
+ This option modifies the set of compiler flags for
+ building these serial device drivers. These flags are removed from
+ the set of global flags if present."
+ }
+ }
+
+ cdl_component CYGPKG_IO_SERIAL_ARM_NETARM_TESTING {
+ display "Testing parameters"
+ flavor bool
+ calculated 1
+ active_if CYGPKG_IO_SERIAL_ARM_NETARM_SERIAL1
+
+ implements CYGINT_IO_SERIAL_TEST_SKIP_115200
+
+ cdl_option CYGPRI_SER_TEST_SER_DEV {
+ display "Serial device used for testing"
+ flavor data
+ default_value { CYGDAT_IO_SERIAL_ARM_NETARM_SERIAL1_NAME }
+ }
+
+ define_proc {
+ puts $::cdl_header "#define CYGPRI_SER_TEST_CRASH_ID \"armnetarm\""
+ puts $::cdl_header "#define CYGPRI_SER_TEST_TTY_DEV \"/dev/tty1\""
+ }
+ }
+}
+
+
diff -urN -x CVS -x doc -x ChangeLog -x powerpc ecos/packages/devs/serial/arm/netarm/current/src/netarm_serial.c ecos.my/packages/devs/serial/arm/netarm/current/src/netarm_serial.c
--- ecos/packages/devs/serial/arm/netarm/current/src/netarm_serial.c 1970-01-01 01:00:00.000000000 +0100
+++ ecos.my/packages/devs/serial/arm/netarm/current/src/netarm_serial.c 2002-10-25 14:14:55.000000000 +0200
@@ -0,0 +1,473 @@
+//==========================================================================
+//
+// io/serial/arm/netarm_serial.c
+//
+// NetSilion NET+ARM Serial I/O Interface Module (interrupt driven)
+//
+//==========================================================================
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): Peter De Schrijver (p2@mind.be)
+// Contributors: Peter De Schrijver (p2@mind.be)
+// Date: 2002-10-25
+// Purpose: NET+ARM Serial I/O module (interrupt driven version)
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/system.h>
+#include <pkgconf/io_serial.h>
+#include <pkgconf/io.h>
+#include <cyg/io/io.h>
+#include <cyg/hal/hal_intr.h>
+#include <cyg/io/devtab.h>
+#include <cyg/io/serial.h>
+#include <cyg/infra/diag.h>
+
+#ifdef CYGPKG_IO_SERIAL_ARM_NETARM
+
+#include "netarm_serial.h"
+
+typedef struct netarm_serial_info {
+ volatile cyg_uint32 *base; // Pointer to serial base
+ CYG_WORD tx_int_num,
+ rx_int_num;
+ cyg_interrupt serial_tx_interrupt,
+ serial_rx_interrupt;
+ cyg_handle_t serial_tx_interrupt_handle,
+ serial_rx_interrupt_handle;
+ bool tx_enabled;
+ cyg_uint8 rx_buffer[4];
+ int rx_buffer_read, rx_buffer_write;
+} netarm_serial_info;
+
+static bool netarm_serial_init(struct cyg_devtab_entry *tab);
+static bool netarm_serial_putc(serial_channel *chan, unsigned char c);
+static Cyg_ErrNo netarm_serial_lookup(struct cyg_devtab_entry **tab,
+ struct cyg_devtab_entry *sub_tab,
+ const char *name);
+static unsigned char netarm_serial_getc(serial_channel *chan);
+static Cyg_ErrNo netarm_serial_set_config(serial_channel *chan, cyg_uint32 key,
+ const void *xbuf, cyg_uint32 *len);
+static void netarm_serial_start_xmit(serial_channel *chan);
+static void netarm_serial_stop_xmit(serial_channel *chan);
+
+static cyg_uint32 netarm_serial_tx_ISR(cyg_vector_t vector, cyg_addrword_t data);
+static void netarm_serial_tx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data);
+static cyg_uint32 netarm_serial_rx_ISR(cyg_vector_t vector, cyg_addrword_t data);
+static void netarm_serial_rx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data);
+
+static SERIAL_FUNS(netarm_serial_funs,
+ netarm_serial_putc,
+ netarm_serial_getc,
+ netarm_serial_set_config,
+ netarm_serial_start_xmit,
+ netarm_serial_stop_xmit
+ );
+
+#ifdef CYGPKG_IO_SERIAL_ARM_NETARM_SERIAL1
+static netarm_serial_info netarm_serial_info1 = { SERIALA,
+ CYGNUM_HAL_INTERRUPT_SERATX,
+ CYGNUM_HAL_INTERRUPT_SERARX,
+};
+
+#if CYGNUM_IO_SERIAL_ARM_NETARM_SERIAL1_BUFSIZE > 0
+static unsigned char netarm_serial_out_buf1[CYGNUM_IO_SERIAL_ARM_NETARM_SERIAL1_BUFSIZE];
+static unsigned char netarm_serial_in_buf1[CYGNUM_IO_SERIAL_ARM_NETARM_SERIAL1_BUFSIZE];
+
+static SERIAL_CHANNEL_USING_INTERRUPTS(netarm_serial_channel1,
+ netarm_serial_funs,
+ netarm_serial_info1,
+ CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_NETARM_SERIAL1_BAUD),
+ CYG_SERIAL_STOP_DEFAULT,
+ CYG_SERIAL_PARITY_DEFAULT,
+ CYG_SERIAL_WORD_LENGTH_DEFAULT,
+ CYG_SERIAL_FLAGS_DEFAULT,
+ &netarm_serial_out_buf1[0], sizeof(netarm_serial_out_buf1),
+ &netarm_serial_in_buf1[0], sizeof(netarm_serial_in_buf1)
+ );
+#else
+static SERIAL_CHANNEL(netarm_serial_channel1,
+ netarm_serial_funs,
+ netarm_serial_info1,
+ CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_NETARM_SERIAL1_BAUD),
+ CYG_SERIAL_STOP_DEFAULT,
+ CYG_SERIAL_PARITY_DEFAULT,
+ CYG_SERIAL_WORD_LENGTH_DEFAULT,
+ CYG_SERIAL_FLAGS_DEFAULT
+ );
+#endif
+
+DEVTAB_ENTRY(netarm_serial_io1,
+ CYGDAT_IO_SERIAL_ARM_NETARM_SERIAL1_NAME,
+ 0,
+ &cyg_io_serial_devio,
+ netarm_serial_init,
+ netarm_serial_lookup,
+ &netarm_serial_channel1
+ );
+#endif
+
+
+#ifdef CYGPKG_IO_SERIAL_ARM_NETARM_SERIAL2
+static netarm_serial_info netarm_serial_info2 = { SERIALB,
+ CYGNUM_HAL_INTERRUPT_SERBTX,
+ CYGNUM_HAL_INTERRUPT_SERBRX,
+};
+
+#if CYGNUM_IO_SERIAL_ARM_NETARM_SERIAL2_BUFSIZE > 0
+static unsigned char netarm_serial_out_buf2[CYGNUM_IO_SERIAL_ARM_NETARM_SERIAL2_BUFSIZE];
+static unsigned char netarm_serial_in_buf2[CYGNUM_IO_SERIAL_ARM_NETARM_SERIAL2_BUFSIZE];
+
+static SERIAL_CHANNEL_USING_INTERRUPTS(netarm_serial_channel2,
+ netarm_serial_funs,
+ netarm_serial_info2,
+ CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_NETARM_SERIAL2_BAUD),
+ CYG_SERIAL_STOP_DEFAULT,
+ CYG_SERIAL_PARITY_DEFAULT,
+ CYG_SERIAL_WORD_LENGTH_DEFAULT,
+ CYG_SERIAL_FLAGS_DEFAULT,
+ &netarm_serial_out_buf2[0], sizeof(netarm_serial_out_buf2),
+ &netarm_serial_in_buf2[0], sizeof(netarm_serial_in_buf2)
+ );
+#else
+static SERIAL_CHANNEL(netarm_serial_channel2,
+ netarm_serial_funs,
+ netarm_serial_info2,
+ CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_NETARM_SERIAL2_BAUD),
+ CYG_SERIAL_STOP_DEFAULT,
+ CYG_SERIAL_PARITY_DEFAULT,
+ CYG_SERIAL_WORD_LENGTH_DEFAULT,
+ CYG_SERIAL_FLAGS_DEFAULT
+ );
+#endif
+
+DEVTAB_ENTRY(netarm_serial_io2,
+ CYGDAT_IO_SERIAL_ARM_NETARM_SERIAL2_NAME,
+ 0,
+ &cyg_io_serial_devio,
+ netarm_serial_init,
+ netarm_serial_lookup,
+ &netarm_serial_channel2
+ );
+#endif
+
+static int rx_overflow_count;
+
+static bool netarm_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config,bool init) {
+
+ netarm_serial_info *netarm=(netarm_serial_info *)chan->dev_priv;
+ unsigned int baud_divisor = select_baud[new_config->baud];
+
+ if (baud_divisor == 0) return false;
+
+ *(netarm->base+SERIAL_RCT)|=SERIAL_TRUN;
+ *(netarm->base+SERIAL_CCR_B)=SERIAL_MODE_ASYNC|SERIAL_RCGT;
+ *(netarm->base+SERIAL_CCR_A)&=~SERIAL_CE & ~(3 << 24) & ~SERIAL_STICKP &
+ ~SERIAL_EPS & ~SERIAL_PE & ~SERIAL_STOPB;
+ *(netarm->base+SERIAL_CCR_A)|=select_word_length[new_config->word_length - CYGNUM_SERIAL_WORD_LENGTH_5] |
+ select_stop_bits[new_config->stop] |
+ select_parity[new_config->parity] |
+ SERIAL_CE;
+ *(netarm->base+SERIAL_BRR)=SERIAL_EBIT | UART_BITRATE(baud_divisor);
+ *(netarm->base+SERIAL_SR_A)|=SERIAL_RBC;
+ while(netarm->base[SERIAL_SR_A] & SERIAL_RREADY)
+ *(netarm->base+SERIAL_FDR);
+
+ if (new_config != &chan->config) {
+ chan->config = *new_config;
+ }
+
+ return true;
+
+}
+
+static bool netarm_serial_init(struct cyg_devtab_entry *tab) {
+
+ serial_channel *chan = (serial_channel *)tab->priv;
+ netarm_serial_info *netarm_chan=(netarm_serial_info *)chan->dev_priv;
+#ifdef CYGDBG_IO_INIT
+ diag_printf("NETARM SERIAL init - dev: %x.%d\n",netarm_chan->base, netarm_chan->tx_int_num);
+#endif
+ (chan->callbacks->serial_init)(chan);
+ if (chan->out_cbuf.len != 0) {
+ cyg_drv_interrupt_create(netarm_chan->tx_int_num,
+ 99,
+ (cyg_addrword_t)chan,
+ netarm_serial_tx_ISR,
+ netarm_serial_tx_DSR,
+ &netarm_chan->serial_tx_interrupt_handle,
+ &netarm_chan->serial_tx_interrupt);
+ cyg_drv_interrupt_attach(netarm_chan->serial_tx_interrupt_handle);
+ cyg_drv_interrupt_mask(netarm_chan->tx_int_num);
+ netarm_chan->base[SERIAL_CCR_A]|=SERIAL_TFHE_IE;
+ }
+ if (chan->in_cbuf.len != 0) {
+ cyg_drv_interrupt_create(netarm_chan->rx_int_num,
+ 99,
+ (cyg_addrword_t)chan,
+ netarm_serial_rx_ISR,
+ netarm_serial_rx_DSR,
+ &netarm_chan->serial_rx_interrupt_handle,
+ &netarm_chan->serial_rx_interrupt);
+ cyg_drv_interrupt_attach(netarm_chan->serial_rx_interrupt_handle);
+ cyg_drv_interrupt_unmask(netarm_chan->rx_int_num);
+ netarm_chan->base[SERIAL_CCR_A]|=SERIAL_RBC_IE|SERIAL_RRR_IE;
+ }
+ netarm_serial_config_port(chan, &chan->config, true);
+ return true;
+
+}
+
+static Cyg_ErrNo netarm_serial_lookup(struct cyg_devtab_entry **tab,
+ struct cyg_devtab_entry *sub_tab,
+ const char *name) {
+
+ serial_channel *chan = (serial_channel *)(*tab)->priv;
+ (chan->callbacks->serial_init)(chan);
+
+ return ENOERR;
+
+}
+
+static bool netarm_serial_putc(serial_channel *chan, unsigned char c) {
+
+ netarm_serial_info *netarm_chan=(netarm_serial_info *)chan->dev_priv;
+ volatile cyg_uint32 *base = netarm_chan->base;
+
+ if(base[SERIAL_SR_A] & SERIAL_TRDY) {
+ *(volatile cyg_uint8 *)(base+SERIAL_FDR)=c;
+ return true;
+ }
+ else
+ return false;
+
+}
+
+static unsigned char netarm_serial_getc(serial_channel *chan) {
+
+ unsigned char c;
+ cyg_uint32 word, validbytes;
+ netarm_serial_info *netarm_chan=(netarm_serial_info *)chan->dev_priv;
+ int count;
+
+ if(netarm_chan->rx_buffer_read!=netarm_chan->rx_buffer_write) {
+ c=netarm_chan->rx_buffer[netarm_chan->rx_buffer_read++];
+ if(netarm_chan->rx_buffer_read==4)
+ netarm_chan->rx_buffer_read=0;
+ return c;
+ }
+
+ while(!(netarm_chan->base[SERIAL_SR_A] & SERIAL_RBC));
+ netarm_chan->base[SERIAL_SR_A]|=SERIAL_RBC;
+
+ validbytes=(netarm_chan->base[SERIAL_SR_A] >> 20) & 0x3;
+ word=netarm_chan->base[SERIAL_FDR];
+
+ c=word>>24;
+ word&=0xffffff;
+
+ count=0;
+ switch(validbytes) {
+ case 0:
+ netarm_chan->rx_buffer[(netarm_chan->rx_buffer_write+2)&3]=word &0xff;
+ count++;
+ case 3:
+ netarm_chan->rx_buffer[(netarm_chan->rx_buffer_write+1)&3]=(word &0xff00) >> 8;
+ count++;
+ case 2:
+ netarm_chan->rx_buffer[netarm_chan->rx_buffer_write]=(word & 0xff0000) >> 16;
+ count++;
+ }
+
+ netarm_chan->rx_buffer_write+=count;
+ netarm_chan->rx_buffer_write&=3;
+
+
+ return c;
+
+}
+
+static Cyg_ErrNo netarm_serial_set_config(serial_channel *chan, cyg_uint32 key,
+ const void *xbuf, cyg_uint32 *len) {
+
+ switch (key) {
+ case CYG_IO_SET_CONFIG_SERIAL_INFO:
+ {
+ cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf;
+ if ( *len < sizeof(cyg_serial_info_t) ) {
+ return -EINVAL;
+ }
+ *len = sizeof(cyg_serial_info_t);
+ if ( true != netarm_serial_config_port(chan, config, false))
+ return -EINVAL;
+ }
+ break;
+
+ default:
+ return -EINVAL;
+ }
+ return ENOERR;
+}
+
+static void netarm_serial_start_xmit(serial_channel *chan) {
+
+ netarm_serial_info *netarm_chan=(netarm_serial_info *)chan->dev_priv;
+
+ netarm_chan->tx_enabled=true;
+ cyg_drv_interrupt_unmask(netarm_chan->tx_int_num);
+
+}
+
+static void netarm_serial_stop_xmit(serial_channel *chan) {
+
+ netarm_serial_info *netarm_chan=(netarm_serial_info *)chan->dev_priv;
+
+ cyg_drv_interrupt_mask(netarm_chan->tx_int_num);
+ netarm_chan->tx_enabled=false;
+
+}
+
+static cyg_uint32 netarm_serial_tx_ISR(cyg_vector_t vector, cyg_addrword_t data) {
+
+ serial_channel *chan = (serial_channel *)data;
+ netarm_serial_info *netarm_chan=(netarm_serial_info *)chan->dev_priv;
+
+ cyg_drv_interrupt_mask(netarm_chan->tx_int_num);
+ cyg_drv_interrupt_acknowledge(netarm_chan->tx_int_num);
+
+ return CYG_ISR_CALL_DSR;
+}
+
+static void netarm_serial_tx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) {
+
+ int space,chars_avail,i;
+ serial_channel *chan = (serial_channel *)data;
+ netarm_serial_info *netarm_chan=(netarm_serial_info *)chan->dev_priv;
+ volatile cyg_uint32 *base = netarm_chan->base;
+ xmt_req_reply_t block_status=CYG_XMT_DISABLED;
+ unsigned char *chars;
+
+ if(base[SERIAL_SR_A] & SERIAL_THALF)
+ space=16;
+ else
+ space=4;
+
+ block_status=(chan->callbacks->data_xmt_req)(chan, space, &chars_avail, &chars);
+ if(block_status == CYG_XMT_DISABLED) {
+ while(space-- && (netarm_chan->tx_enabled==true))
+ (chan->callbacks->xmt_char)(chan);
+ }
+ else if(block_status == CYG_XMT_OK) {
+ do {
+ for(i=chars_avail;i>3;i-=4,chars+=4)
+ *((cyg_uint32 *)&base[SERIAL_FDR])=*(cyg_uint32 *)chars;
+
+ if(i>1) {
+ *((cyg_uint16 *)&base[SERIAL_FDR])=*(cyg_uint16 *)chars;
+ i-=2;
+ chars+=2;
+ }
+
+ if(i)
+ *((cyg_uint8 *)&base[SERIAL_FDR])=*(cyg_uint8 *)chars;
+
+ (chan->callbacks->data_xmt_done)(chan, chars_avail);
+
+ space=0;
+ if(base[SERIAL_SR_A] & SERIAL_THALF)
+ space=16;
+ else if(base[SERIAL_SR_A] & SERIAL_TRDY)
+ space=4;
+
+ } while(space && (chan->callbacks->data_xmt_req)(chan, space, &chars_avail, &chars) == CYG_XMT_OK);
+ }
+
+ if(netarm_chan->tx_enabled) {
+ cyg_drv_interrupt_unmask(netarm_chan->tx_int_num);
+ }
+}
+
+static cyg_uint32 netarm_serial_rx_ISR(cyg_vector_t vector, cyg_addrword_t data) {
+
+ serial_channel *chan = (serial_channel *)data;
+ netarm_serial_info *netarm_chan=(netarm_serial_info *)chan->dev_priv;
+
+ cyg_drv_interrupt_mask(netarm_chan->rx_int_num);
+ cyg_drv_interrupt_acknowledge(netarm_chan->rx_int_num);
+
+ netarm_chan->base[SERIAL_SR_A]|=SERIAL_RBC;
+
+ if(netarm_chan->base[SERIAL_SR_A] & SERIAL_ROVER) {
+ netarm_chan->base[SERIAL_SR_A]|=SERIAL_ROVER;
+ rx_overflow_count++;
+ }
+
+ return CYG_ISR_CALL_DSR;
+
+}
+
+static void netarm_serial_rx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) {
+
+ rcv_req_reply_t block_status;
+ cyg_uint32 word;
+ int avail,i,space_avail;
+ serial_channel *chan=(serial_channel *)data;
+ netarm_serial_info *netarm_chan=(netarm_serial_info *)chan->dev_priv;
+ unsigned char *space;
+
+ avail=0;
+ if(netarm_chan->base[SERIAL_SR_A]&SERIAL_RHALF)
+ avail=16;
+ else if(netarm_chan->base[SERIAL_SR_A]&SERIAL_RREADY) {
+ avail=(netarm_chan->base[SERIAL_SR_A] >> 20) & 0x3;
+ if(!avail)
+ avail=4;
+ }
+
+ block_status=(chan->callbacks->data_rcv_req)(chan,avail,&space_avail,&space);
+ if(block_status==CYG_RCV_OK) {
+ do {
+ for(i=space_avail;i>3;i-=4)
+ *((cyg_uint32 *)space++)=netarm_chan->base[SERIAL_FDR];
+
+ word=netarm_chan->base[SERIAL_FDR];
+ for(;i>0;i--) {
+ *(space++)= word>>24;
+ word<<=8;
+ }
+
+ (chan->callbacks->data_rcv_done)(chan,space_avail);
+
+ avail=0;
+ if(netarm_chan->base[SERIAL_SR_A]&SERIAL_RHALF)
+ avail=16;
+ else if(netarm_chan->base[SERIAL_SR_A]&SERIAL_RREADY) {
+ avail=(netarm_chan->base[SERIAL_SR_A] >> 20) & 0x3;
+ if(!avail)
+ avail=4;
+ }
+
+ } while(avail > 0 && ((chan->callbacks->data_rcv_req)(chan,avail,&space_avail,&space)==CYG_RCV_OK));
+ }
+ else {
+ while(netarm_chan->base[SERIAL_SR_A]&SERIAL_RREADY) {
+ i=(netarm_chan->base[SERIAL_SR_A] >> 20) & 0x3;
+ if(!i)
+ i=4;
+ word=netarm_chan->base[SERIAL_FDR];
+ for(;i>0;i--) {
+ (chan->callbacks->rcv_char)(chan, word>>24);
+ word<<=8;
+ }
+ }
+ }
+
+ cyg_drv_interrupt_unmask(netarm_chan->rx_int_num);
+}
+
+#endif
+
diff -urN -x CVS -x doc -x ChangeLog -x powerpc ecos/packages/devs/serial/arm/netarm/current/src/netarm_serial.h ecos.my/packages/devs/serial/arm/netarm/current/src/netarm_serial.h
--- ecos/packages/devs/serial/arm/netarm/current/src/netarm_serial.h 1970-01-01 01:00:00.000000000 +0100
+++ ecos.my/packages/devs/serial/arm/netarm/current/src/netarm_serial.h 2002-10-25 14:14:45.000000000 +0200
@@ -0,0 +1,78 @@
+#ifndef CYGONCE_ARM_NETARM_SERIAL_H
+#define CYGONCE_ARM_NETARM_SERIAL_H
+
+// ====================================================================
+//
+// netarm_serial.h
+//
+// Device I/O - Description of NET+ARM serial hardware
+//
+// ====================================================================
+// ====================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): Peter De Schrijver (p2@mind.be)
+// Contributors: Peter De Schrijver (p2@mind.be)
+// Date: 2002-10-25
+// Purpose: Internal interfaces for serial I/O drivers
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+// ====================================================================
+
+// Description of serial ports on NET+ARM
+
+#include <cyg/hal/hal_netarm.h> // Hardware definitions
+
+static unsigned int select_word_length[] = {
+ (SERIAL_WLEN5<<24), // 5 bits / word (char)
+ (SERIAL_WLEN6<<24),
+ (SERIAL_WLEN7<<24),
+ (SERIAL_WLEN8<<24)
+};
+
+static unsigned int select_stop_bits[] = {
+ 0,
+ 0, // 1 stop bit
+ SERIAL_STOPB, // 1.5 stop bit
+ SERIAL_STOPB // 2 stop bits
+};
+
+static unsigned int select_parity[] = {
+ 0, // No parity
+ SERIAL_PE|SERIAL_EPS, // Even parity
+ SERIAL_PE, // Odd parity
+ SERIAL_PE|SERIAL_STICKP|SERIAL_EPS, // Mark parity
+ SERIAL_PE|SERIAL_STICKP, // Space parity
+};
+
+// Baud rate values, based on PLL clock
+
+static cyg_int32 select_baud[] = {
+ 0, // Unused
+ 0, // 50
+ 75, // 75
+ 0, // 110
+ 0, // 134.5
+ 150, // 150
+ 0, // 200
+ 300, // 300
+ 600, // 600
+ 1200, // 1200
+ 1800, // 1800
+ 2400, // 2400
+ 3600, // 3600
+ 4800, // 4800
+ 7200, // 7200
+ 9600, // 9600
+ 14400, // 14400
+ 19200, // 19200
+ 38400, // 38400
+ 57600, // 57600
+ 115200, // 115200
+ 0, // 230400
+};
+
+#endif // CYGONCE_ARM_NETARM_SERIAL_H
+
diff -urN -x CVS -x doc -x ChangeLog -x powerpc ecos/packages/ecos.db ecos.my/packages/ecos.db
--- ecos/packages/ecos.db 2002-10-18 18:56:52.000000000 +0200
+++ ecos.my/packages/ecos.db 2002-10-25 14:17:58.000000000 +0200
@@ -687,6 +687,15 @@
description "Atmel AT91 evaluation board (EB40) serial drivers."
}
+package CYGPKG_IO_SERIAL_ARM_NETARM {
+ alias { "ARM NET+ARM serial device drivers"
+ devs_serial_arm_netarm netarm_serial_driver }
+ hardware
+ directory devs/serial/arm/netarm
+ script ser_arm_netarm.cdl
+ description "ARM NET+ARM serial device drivers"
+}
+
package CYGPKG_IO_SERIAL_POWERPC_COGENT {
alias { "Cogent PowerPC serial device drivers"
devs_serial_powerpc_cogent cogent_serial_driver }
@@ -2036,7 +2045,15 @@
The IQ80321 HAL package provides the support needed to run
eCos on an Intel XScale IQ80321 evaluation board."
}
-
+package CYGPKG_HAL_ARM_NETARM {
+ alias { "NetSilicon NET+ARM board" hal_arm_netarm arm_netarm_hal }
+ directory hal/arm/netarm
+ script hal_arm_netarm.cdl
+ hardware
+ description "
+ The NetARM HAL package provides the support needed to run
+ eCos on an NetSilicon NetARM evaluation board."
+}
# --------------------------------------------------------------------------
# SH packages
package CYGPKG_HAL_SH {
@@ -3328,6 +3345,16 @@
The snds target provides the packages needed to run eCos on a
Samsung SNDS eval board."
}
+
+target netarm {
+ alias { "NetSilicon NetARM board" netarm }
+ packages { CYGPKG_HAL_ARM
+ CYGPKG_HAL_ARM_NETARM
+ }
+ description "
+ The netarm target provides the packages needed to run eCos on a NetSilicon
+ NET+ARM evaluation board."
+}
# --------------------------------------------------------------------------
# SH targets
diff -urN -x CVS -x doc -x ChangeLog -x powerpc ecos/packages/hal/arm/netarm/current/cdl/hal_arm_netarm.cdl ecos.my/packages/hal/arm/netarm/current/cdl/hal_arm_netarm.cdl
--- ecos/packages/hal/arm/netarm/current/cdl/hal_arm_netarm.cdl 1970-01-01 01:00:00.000000000 +0100
+++ ecos.my/packages/hal/arm/netarm/current/cdl/hal_arm_netarm.cdl 2002-10-25 15:53:18.000000000 +0200
@@ -0,0 +1,327 @@
+#
+cdl_package CYGPKG_HAL_ARM_NETARM {
+
+ display "NET+ARM development board"
+ parent CYGPKG_HAL_ARM
+ include_dir cyg/hal
+ define_header hal_arm_netarm.h
+ description "
+ The NET+ARM HAL package provides the support needed to run
+ eCos on a NetSilicon NET+ARM development board."
+ compile hal_diag.c netarm_misc.c
+ implements CYGINT_HAL_DEBUG_GDB_STUBS
+ implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
+ implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
+ implements CYGINT_HAL_ARM_ARCH_ARM7
+ define_proc {
+ puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_arm.h>"
+ puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_arm_netarm.h>"
+ }
+
+ cdl_component CYG_HAL_STARTUP {
+ display "Startup type"
+ flavor data
+ legal_values { "ROM" "RAM" "ROMRAM" }
+ default_value { "RAM"}
+
+ no_define
+
+ define -file system.h CYG_HAL_STARTUP
+
+ description "
+ When targetting the NET+ARM evaluation boards it is possible to
+ build the system for either RAM bootstrap or ROM bootstrap(s).
+ Select 'ram' when building programs to load into RAM using onboard
+ debug software such as Angel or eCos GDB stubs. Select 'rom' when
+ building a stand-alone application which will be put into ROM."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
+ display "Diagnostic serial port baud rate"
+ flavor data
+ legal_values 9600 19200 38400 115200
+ default_value 38400
+ description "
+ This option selects the baud rate used for the diagnostic port.
+ Note: this should match the value chosen for the GDB port if the
+ diagnostic and GDB port are the same."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
+ display "GDB serial port baud rate"
+ flavor data
+ legal_values 9600 19200 38400 115200
+ default_value 38400
+ description "
+ This option controls the baud rate used for the GDB connection."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+ display "Number of communication channels on the board"
+ flavor data
+ calculated 2
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT {
+ display "Default console channel."
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS - 1
+ calculated 0
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+ display "Debug serial port"
+ active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS - 1
+ default_value 0
+ description "
+ The NET+ARM board has two serial ports. This option
+ chooses which port will be used to connect to a host
+ running GDB."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+ display "Diagnostic serial port"
+ active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS - 1
+ default_value 0
+ description "
+ The NET+ARM board has two serial ports. This option
+ chooses which port will be used for diagnostic output."
+ }
+
+# Real-time clock/counter specifics
+
+ cdl_component CYGNUM_HAL_NETARM_CLOCK_SPEED {
+ display "F_XTAL value"
+ flavor data
+ default_value 3686400
+ description "F_XTAL = F_CRYSTAL/6 (See NET+ARM datasheet)."
+ }
+
+ cdl_component CYGNUM_HAL_RTC_CONSTANTS {
+ display "Real-time clock constants"
+ flavor none
+ cdl_option CYGNUM_HAL_RTC_NUMERATOR {
+ display "Real-time clock numerator"
+ flavor data
+ calculated 1000000000
+ }
+ cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
+ display "Real-time clock denominator"
+ flavor data
+ calculated 100
+ }
+ cdl_option CYGNUM_HAL_RTC_PERIOD {
+ display "Real-time clock period"
+ flavor data
+ calculated (CYGNUM_HAL_NETARM_CLOCK_SPEED / (8 * 6 * CYGNUM_HAL_RTC_DENOMINATOR))
+ }
+ }
+
+ cdl_component CYGBLD_GLOBAL_OPTIONS {
+ display "Global build options"
+ flavor none
+ description "
+ Global build options including control over
+ compiler flags, linker flags and choice of toolchain."
+ parent CYGPKG_NONE
+
+ cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+ display "Global command prefix"
+ flavor data
+ no_define
+ default_value { "arm-elf"}
+ description "
+ This option specifies the command prefix used when
+ invoking the build tools."
+ }
+
+ cdl_option CYGBLD_GLOBAL_CFLAGS {
+ display "Global compiler flags"
+ flavor data
+ no_define
+ default_value { "-mbig-endian -mcpu=arm7tdmi -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority"}
+ description "
+ This option controls the global compiler flags which are used to
+ compile all packages by default. Individual packages may define
+ options which override these global flags."
+ }
+
+ cdl_option CYGBLD_GLOBAL_LDFLAGS {
+ display "Global linker flags"
+ flavor data
+ no_define
+ default_value { "-mbig-endian -mcpu=arm7tdmi -Wl,--gc-sections -Wl,-static -g -nostdlib"}
+ description "
+ This option controls the global linker flags. Individual
+ packages may define options which override these global flags."
+ }
+
+ cdl_option CYGBLD_BUILD_GDB_STUBS {
+ display "Build GDB stub ROM image"
+ default_value 0
+ requires { CYG_HAL_STARTUP == "ROM"}
+ requires CYGSEM_HAL_ROM_MONITOR
+ requires CYGBLD_BUILD_COMMON_GDB_STUBS
+ requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ requires CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ requires CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
+ requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
+ requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
+ no_define
+ description "
+ This option enables the building of the GDB stubs for the
+ board. The common HAL controls takes care of most of the
+ build process, but the final conversion from ELF image to
+ binary data is handled by the platform CDL, allowing
+ relocation of the data if necessary."
+
+ make -priority 320 {
+ <PREFIX>/bin/gdb_module.bin:<PREFIX>/bin/gdb_module.img
+ $(OBJCOPY) -O binary $< $@
+ }
+ }
+ }
+
+ cdl_component CYGHWR_MEMORY_LAYOUT {
+ display "Memory layout"
+ flavor data
+ no_define
+ calculated { CYG_HAL_STARTUP == "RAM" ? "arm_netarm_ram.mlt" :
+ CYG_HAL_STARTUP == "ROM" ? "arm_netarm_rom.mlt" :
+ CYG_HAL_STARTUP == "ROMRAM" ? "arm_netarm_romram.mlt" :
+ "BOGUS.mlt" }
+
+ cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
+ display "Memory layout linker script fragment"
+ flavor data
+ no_define
+ define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
+ calculated {
+ CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_arm_netarm_ram.ldi>"
+ : CYG_HAL_STARTUP == "ROM" ? "<pkgconf/mlt_arm_netarm_rom.ldi>"
+ : CYG_HAL_STARTUP == "ROMRAM" ? "<pkgconf/mlt_arm_netarm_romram.ldi>"
+ : "BOGUS.ldi"
+ }
+ }
+
+ cdl_option CYGHWR_MEMORY_LAYOUT_H {
+ display "Memory layout header file"
+ flavor data
+ no_define
+ define -file system.h CYGHWR_MEMORY_LAYOUT_H
+ calculated {
+ CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_arm_netarm_ram.h>"
+ : CYG_HAL_STARTUP == "ROM" ? "<pkgconf/mlt_arm_netarm_rom.h>"
+ : CYG_HAL_STARTUP == "ROMRAM" ? "<pkgconf/mlt_arm_netarm_romram.h>"
+ : "BOGUS.h"
+ }
+ }
+ }
+
+ cdl_option CYGSEM_HAL_ROM_MONITOR {
+ display "Behave as a ROM monitor"
+ flavor bool
+ default_value 0
+ parent CYGPKG_HAL_ROM_MONITOR
+ requires { CYG_HAL_STARTUP == "ROM"}
+ description "
+ Enable this option if this program is to be used as a ROM monitor,
+ i.e. applications will be loaded into RAM on the board, and this
+ ROM monitor may process exceptions or interrupts generated from the
+ application. This enables features such as utilizing a separate
+ interrupt stack when exceptions are generated."
+ }
+
+ cdl_component CYGPKG_CYGMON_HAL_OPTIONS {
+ display "CygMon HAL options"
+ flavor none
+ no_define
+ parent CYGPKG_CYGMON
+ active_if CYGPKG_CYGMON
+ requires CYGPKG_IO_SERIAL_ARM_NETARM
+ requires { (CYGDAT_CYGMON_CONSOLE_DEV != "\"/dev/ser0\"") || \
+ (CYGPKG_IO_SERIAL_ARM_NETARM_SERIAL1)}
+ requires { (CYGDAT_CYGMON_CONSOLE_DEV != "\"/dev/ser1\"") || \
+ (CYGPKG_IO_SERIAL_ARM_NETARM_SERIAL2)}
+
+ description "
+ This option lists the target's requirements for a valid CygMon
+ configuration."
+ cdl_option CYGDAT_CYGMON_CONSOLE_DEV {
+ display "Serial port for default console"
+ flavor data
+ default_value { "\"/dev/ser1\""}
+ description "
+ This option selects the physical device to use as the default
+ console device for CygMon."
+ }
+
+ cdl_option CYGBLD_BUILD_CYGMON_BIN {
+ display "Build CygMon ROM binary image"
+ active_if CYGBLD_BUILD_CYGMON
+ default_value 1
+ no_define
+ description "
+ This option enables the conversion of the CygMon ELF
+ image to a binary image suitable for ROM programming."
+ make -priority 325 {
+ <PREFIX>/bin/cygmon.bin: <PREFIX>/bin/cygmon.elf
+ $(OBJCOPY) --strip-debug $< $(@:.bin=.img)
+ $(OBJCOPY) -O srec $< $(@:.bin=.srec)
+ $(OBJCOPY) -O binary $< $@
+ }
+ }
+ }
+
+ cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+ display "Work with a ROM monitor"
+ flavor booldata
+ legal_values { "Generic" "GDB_stubs"}
+ default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0}
+ parent CYGPKG_HAL_ROM_MONITOR
+ requires { CYG_HAL_STARTUP == "RAM"}
+ description "
+ Support can be enabled for different varieties of ROM monitor.
+ This support changes various eCos semantics such as the encoding
+ of diagnostic output, or the overriding of hardware interrupt
+ vectors.
+ Firstly there is \"Generic\" support which prevents the HAL
+ from overriding the hardware vectors that it does not use, to
+ instead allow an installed ROM monitor to handle them. This is
+ the most basic support which is likely to be common to most
+ implementations of ROM monitor.
+ \"GDB_stubs\" provides support when GDB stubs are included in
+ the ROM monitor or boot ROM."
+ }
+
+ cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {
+ display "Redboot HAL options"
+ flavor none
+ no_define
+ parent CYGPKG_REDBOOT
+ active_if CYGPKG_REDBOOT
+ description "
+ This option lists the target's requirements for a valid Redboot
+ configuration."
+ cdl_option CYGBLD_BUILD_REDBOOT_BIN {
+ display "Build Redboot ROM binary image"
+ active_if CYGBLD_BUILD_REDBOOT
+ default_value 1
+ no_define
+ description "
+ This option enables the conversion of the Redboot ELF
+ image to a binary image suitable for ROM programming."
+ make -priority 325 {
+ <PREFIX>/bin/redboot.bin: <PREFIX>/bin/redboot.elf
+ $(OBJCOPY) --strip -debug $< $(@: .bin =.img)
+ $(OBJCOPY) -O srec $< $(@:.bin =.srec)
+ $(OBJCOPY) -O binary $<
+ $@
+ }
+ }
+ }
+}
diff -urN -x CVS -x doc -x ChangeLog -x powerpc ecos/packages/hal/arm/netarm/current/include/hal_cache.h ecos.my/packages/hal/arm/netarm/current/include/hal_cache.h
--- ecos/packages/hal/arm/netarm/current/include/hal_cache.h 1970-01-01 01:00:00.000000000 +0100
+++ ecos.my/packages/hal/arm/netarm/current/include/hal_cache.h 2002-10-26 22:42:21.000000000 +0200
@@ -0,0 +1,88 @@
+/*
+ * hal_cache.h: Cache support for NET+ARM CPU's
+ *
+ * Copyright 2002 Mind NV
+ *
+ * http://www.mind.be/
+ *
+ * Author : Peter De Schrijver (p2@mind.be)
+ *
+ */
+
+#ifndef CYGONCE_HAL_CACHE_H
+#define CYGONCE_HAL_CACHE_H
+
+#include <cyg/infra/cyg_type.h>
+#include <cyg/hal/hal_netarm.h>
+
+#define HAL_ICACHE_SIZE 0x2000 // Size of cache in bytes
+#define HAL_ICACHE_WAYS 4 // Associativity of the cache
+#define HAL_ICACHE_LINE_SIZE 4 // Size of a cache line
+
+#define HAL_ICACHE_BASE 0x08000000
+#define HAL_ICACHE_MASK 0xfe000000
+
+#define HAL_ICACHE_ENABLE() \
+{ \
+ unsigned int *p; \
+ int i; \
+ \
+ *(SYSCON)|=SYSCON_CINIT|SYSCON_CACHE; \
+ p=(unsigned int *)0xfff00000; \
+ for(i=0;i<(0x2000/4);i++,p++) \
+ *p=0; \
+ \
+ *(SYSCON)&=~(SYSCON_CINIT); \
+ *(CCR0)=(HAL_ICACHE_BASE) | \
+ (HAL_ICACHE_MASK >> 8) | \
+ (CCR_ENABLE) | \
+ (CCR_SET1 | CCR_SET2 | CCR_SET3 | CCR_SET4); \
+ *(CCR1)=0; \
+ *(SYSCON)|=SYSCON_CACHE; \
+ *(SYSCON)&=~SYSCON_WB; \
+}
+
+#define HAL_ICACHE_DISABLE() \
+{ \
+ *(CCR0)=0; \
+ *(SYSCON)&=~SYSCON_CACHE; \
+}
+
+#define HAL_ICACHE_IS_ENABLED(_state_) _state_ = ((*(CCR0) & CCR_ENABLE) >> 15)
+
+#define HAL_ICACHE_INVALIDATE_ALL() \
+{ \
+ unsigned *p; \
+ *(SYSCON)|=SYSCON_CINIT; \
+ for(p=(unsigned int*)0xfff00000; \
+ (unsigned int)p<0xfff02000; \
+ p++) \
+ *p=0; \
+ \
+ *(SYSCON)&=~SYSCON_CINIT; \
+}
+
+#define HAL_ICACHE_SYNC()
+
+#define HAL_ICACHE_PURGE_ALL() HAL_ICACHE_INVALIDATE_ALL()
+
+#define HAL_DCACHE_LINE_SIZE 0
+#define HAL_DCACHE_WAYS 0
+#define HAL_DCACHE_SETS 0
+
+#define HAL_DCACHE_ENABLE()
+
+#define HAL_DCACHE_DISABLE()
+
+#define HAL_DCACHE_INVALIDATE_ALL()
+
+#define HAL_DCACHE_SYNC()
+
+#define HAL_DCACHE_IS_ENABLED(_state_) 0
+
+#define HAL_DCACHE_FLUSH( _base_ , _size_ )
+
+#define HAL_DCACHE_STORE( _base_ , _size_ )
+
+#endif
+
diff -urN -x CVS -x doc -x ChangeLog -x powerpc ecos/packages/hal/arm/netarm/current/include/hal_diag.h ecos.my/packages/hal/arm/netarm/current/include/hal_diag.h
--- ecos/packages/hal/arm/netarm/current/include/hal_diag.h 1970-01-01 01:00:00.000000000 +0100
+++ ecos.my/packages/hal/arm/netarm/current/include/hal_diag.h 2002-10-19 19:35:15.000000000 +0200
@@ -0,0 +1,54 @@
+/*
+ * hal_diag.h: Hardware dependant diagnostic interfaces
+ *
+ * Copyright 2002 Mind NV
+ *
+ * http://www.mind.be/
+ *
+ * Author : Peter De Schrijver (p2@mind.be)
+ *
+ */
+
+#ifndef CYGONCE_HAL_DIAG_H
+#define CYGONCE_HAL_DIAG_H
+
+#include <pkgconf/hal.h>
+
+#include <cyg/infra/cyg_type.h>
+
+#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
+
+#include <cyg/hal/hal_if.h>
+
+#define HAL_DIAG_INIT() hal_if_diag_init()
+#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_)
+#define HAL_DIAG_READ_CHAR(_c_) hal_if_diag_read_char(&_c_)
+
+extern void hal_delay_us(cyg_int32 usecs);
+
+#define HAL_DELAY_US(n) hal_delay_us(n);
+
+#else
+
+/*---------------------------------------------------------------------------*/
+/* functions implemented in hal_diag.c */
+
+externC void hal_diag_init(void);
+externC void hal_diag_write_char(char c);
+externC void hal_diag_read_char(char *c);
+
+/*---------------------------------------------------------------------------*/
+
+#define HAL_DIAG_INIT() hal_diag_init()
+
+#define HAL_DIAG_WRITE_CHAR(_c_) hal_diag_write_char(_c_)
+
+#define HAL_DIAG_READ_CHAR(_c_) hal_diag_read_char(&_c_)
+
+#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+/*---------------------------------------------------------------------------*/
+/* end of hal_diag.h */
+#endif /* CYGONCE_HAL_DIAG_H */
+
+
diff -urN -x CVS -x doc -x ChangeLog -x powerpc ecos/packages/hal/arm/netarm/current/include/hal_netarm.h ecos.my/packages/hal/arm/netarm/current/include/hal_netarm.h
--- ecos/packages/hal/arm/netarm/current/include/hal_netarm.h 1970-01-01 01:00:00.000000000 +0100
+++ ecos.my/packages/hal/arm/netarm/current/include/hal_netarm.h 2002-10-24 23:37:09.000000000 +0200
@@ -0,0 +1,151 @@
+#ifndef CYGONCE_HAL_NETARM_H
+#define CYGONCE_HAL_NETARM_H
+
+/*=============================================================================
+//
+// hal_netarm.h
+//
+// Hardware specific defines
+//
+//=============================================================================
+
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): Peter De Schrijver (p2@mind.be)
+// Contributors: Peter De Schrijver (p2@mind.be)
+// Date: 2002-10-19
+// Purpose: Netsilicon NET+ARM Hardware description
+// Description:
+// Usage: #include <cyg/hal/hal_netarm.h>
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================*/
+
+#define SYSCON ((volatile cyg_uint32 *)0xffb00000)
+#define SYSCON_CINIT (1<<7)
+#define SYSCON_CACHE (1<<9)
+#define SYSCON_WB (1<<8)
+
+#define SWSR ((volatile cyg_uint32 *)0xffb0000c)
+
+#define CCR0 ((volatile cyg_uint32 *)0xffb00040)
+#define CCR1 ((volatile cyg_uint32 *)0xffb00044)
+#define CCR_ENABLE (1<<15)
+#define CCR_SET1 (1<<3)
+#define CCR_SET2 (1<<2)
+#define CCR_SET3 (1<<1)
+#define CCR_SET4 (1)
+
+#define TIMERCON1 ((volatile cyg_uint32 *)0xffb00010)
+#define TIMERCON2 ((volatile cyg_uint32 *)0xffb00018)
+#define TIMERSTAT1 ((volatile cyg_uint32 *)0xffb00014)
+#define TIMERSTAT2 ((volatile cyg_uint32 *)0xffb0001c)
+#define TIMERCON_TE (1<<31)
+#define TIMERCON_TIE (1<<30)
+#define TIMERCON_TIRQ (1<<29)
+#define TIMERCON_TPRE (1<<28)
+#define TIMERCON_TPRE (1<<28)
+#define TIMERSTAT_TIP (1<<30)
+
+#define INTENABLE ((volatile cyg_uint32 *)0xffb00030)
+#define INTENABLE_SET ((volatile cyg_uint32 *)0xffb00034)
+#define INTENABLE_CLR ((volatile cyg_uint32 *)0xffb00038)
+#define INTSTATUS ((volatile cyg_uint32 *)0xffb00034)
+#define INTSTATUS_RAW ((volatile cyg_uint32 *)0xffb00038)
+
+#define PORTA ((volatile cyg_uint32 *)0xffb00020)
+#define PORTB ((volatile cyg_uint32 *)0xffb00024)
+#define PORTC ((volatile cyg_uint32 *)0xffb00028)
+
+#define SERIALA ((volatile cyg_uint32 *)0xffd00000)
+#define SERIALB ((volatile cyg_uint32 *)0xffd00040)
+
+#define SERIAL_CCR_A 0x0
+#define SERIAL_CCR_B 0x1
+#define SERIAL_SR_A 0x2
+#define SERIAL_BRR 0x3
+#define SERIAL_FDR 0x4
+#define SERIAL_RBT 0x5
+#define SERIAL_RCT 0x6
+#define SERIAL_RMR 0x7
+#define SERIAL_RMMR 0x8
+#define SERIAL_CCR_C 0x9
+#define SERIAL_SR_B 0xa
+#define SERIAL_SR_C 0xb
+
+#define SERIAL_MODE_ASYNC 0x0
+#define SERIAL_MODE_HDLC 0x1
+#define SERIAL_MODE_SPI_MASTER 0x2
+#define SERIAL_MODE_SPI_SLAVE 0x3
+
+#define SERIAL_EBIT (1<<31)
+#define SERIAL_TMODEX1 (1<<30)
+#define SERIAL_CLK_FXTAL 0
+#define SERIAL_CLK_SYSCLK 1
+#define SERIAL_CLK_OUT1 2
+#define SERIAL_CLK_OUT2 3
+
+#define SERIAL_CE (1<<31)
+#define SERIAL_STICKP (1<<29)
+#define SERIAL_EPS (1<<28)
+#define SERIAL_PE (1<<27)
+#define SERIAL_STOPB (1<<26)
+#define SERIAL_WLEN5 0x0
+#define SERIAL_WLEN6 0x1
+#define SERIAL_WLEN7 0x2
+#define SERIAL_WLEN8 0x3
+#define SERIAL_RTS (1<<16)
+#define SERIAL_RB_IE (1<<15)
+#define SERIAL_RFE_IE (1<<14)
+#define SERIAL_RPE_IE (1<<13)
+#define SERIAL_RO_IE (1<<12)
+#define SERIAL_RRR_IE (1<<11)
+#define SERIAL_RFH_IE (1<<10)
+#define SERIAL_RBC_IE (1<<9)
+#define SERIAL_DDCD_IE (1<<7)
+#define SERIAL_DRI_IE (1<<6)
+#define SERIAL_DDSR_IE (1<<5)
+#define SERIAL_DCTS_IE (1<<4)
+#define SERIAL_TRE_IE (1<<3)
+#define SERIAL_TFHE_IE (1<<2)
+#define SERIAL_TBC_IE (1<<1)
+
+#define SERIAL_TEMPTY 1
+#define SERIAL_THALF (1<<2)
+#define SERIAL_TRDY (1<<3)
+#define SERIAL_RBC (1<<9)
+#define SERIAL_RHALF (1<<10)
+#define SERIAL_RREADY (1<<11)
+#define SERIAL_ROVER (1<<12)
+#define SERIAL_RDM1 (1<<31)
+#define SERIAL_RDM2 (1<<30)
+#define SERIAL_RDM3 (1<<29)
+#define SERIAL_RDM4 (1<<28)
+#define SERIAL_RCGT (1<<26)
+
+#define SERIAL_TRUN (1<<31)
+
+#define UART_DIVISOR (CYGNUM_HAL_NETARM_CLOCK_SPEED/32)
+#define UART_BITRATE(bitrate) (((UART_DIVISOR/(bitrate))-1) | (SERIAL_CLK_FXTAL << 24))
+
+
+#define MMCR ((volatile cyg_uint32 *)0xffc00000)
+#define BAR0 ((volatile cyg_uint32 *)0xffc00010)
+#define OR0 ((volatile cyg_uint32 *)0xffc00014)
+#define BAR1 ((volatile cyg_uint32 *)0xffc00020)
+#define OR1 ((volatile cyg_uint32 *)0xffc00024)
+#define BAR2 ((volatile cyg_uint32 *)0xffc00030)
+#define OR2 ((volatile cyg_uint32 *)0xffc00034)
+#define BAR3 ((volatile cyg_uint32 *)0xffc00040)
+#define OR3 ((volatile cyg_uint32 *)0xffc00044)
+#define BAR4 ((volatile cyg_uint32 *)0xffc00050)
+#define OR4 ((volatile cyg_uint32 *)0xffc00054)
+
+/*---------------------------------------------------------------------------*/
+/* end of hal_netarm.h
+*/
+#endif /* CYGONCE_HAL_NETARM_H */
+
+
diff -urN -x CVS -x doc -x ChangeLog -x powerpc ecos/packages/hal/arm/netarm/current/include/hal_platform_ints.h ecos.my/packages/hal/arm/netarm/current/include/hal_platform_ints.h
--- ecos/packages/hal/arm/netarm/current/include/hal_platform_ints.h 1970-01-01 01:00:00.000000000 +0100
+++ ecos.my/packages/hal/arm/netarm/current/include/hal_platform_ints.h 2002-10-19 19:38:40.000000000 +0200
@@ -0,0 +1,79 @@
+#ifndef CYGONCE_HAL_PLATFORM_INTS_H
+#define CYGONCE_HAL_PLATFORM_INTS_H
+
+//==========================================================================
+//
+// hal_platform_ints.h
+//
+// HAL Interrupt and clock support
+//
+//==========================================================================
+
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): Peter De Schrijver (p2@mind.be)
+// Contributors: Peter De Schrijver (p2@mind.be)
+// Date: 2002-10-19
+// Purpose: Define Interrupt support
+// Description: The interrupt details for the NET+ARM are defined here.
+// Usage:
+// #include <cyg/hal/hal_platform_ints.h>
+// ...
+//
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <cyg/hal/hal_netarm.h>
+
+#define CYGNUM_HAL_INTERRUPT_unused 0
+#define CYGNUM_HAL_INTERRUPT_C0 1
+#define CYGNUM_HAL_INTERRUPT_C1 2
+#define CYGNUM_HAL_INTERRUPT_C2 3
+#define CYGNUM_HAL_INTERRUPT_C3 4
+#define CYGNUM_HAL_INTERRUPT_TIMER2 5
+#define CYGNUM_HAL_INTERRUPT_TIMER1 6
+#define CYGNUM_HAL_INTERRUPT_WTCHDOG 7
+#define CYGNUM_HAL_INTERRUPT_SERBTX 13
+#define CYGNUM_HAL_INTERRUPT_SERBRX 14
+#define CYGNUM_HAL_INTERRUPT_SERATX 15
+#define CYGNUM_HAL_INTERRUPT_SERARX 16
+#define CYGNUM_HAL_INTERRUPT_ENETTX 17
+#define CYGNUM_HAL_INTERRUPT_ENETRX 18
+#define CYGNUM_HAL_INTERRUPT_ENI4 19
+#define CYGNUM_HAL_INTERRUPT_ENI3 20
+#define CYGNUM_HAL_INTERRUPT_ENI2 21
+#define CYGNUM_HAL_INTERRUPT_ENI1 22
+#define CYGNUM_HAL_INTERRUPT_DMA10 23
+#define CYGNUM_HAL_INTERRUPT_DMA9 24
+#define CYGNUM_HAL_INTERRUPT_DMA8 25
+#define CYGNUM_HAL_INTERRUPT_DMA7 26
+#define CYGNUM_HAL_INTERRUPT_DMA6 27
+#define CYGNUM_HAL_INTERRUPT_DMA5 28
+#define CYGNUM_HAL_INTERRUPT_DMA4 29
+#define CYGNUM_HAL_INTERRUPT_DMA3 30
+#define CYGNUM_HAL_INTERRUPT_DMA2 31
+#define CYGNUM_HAL_INTERRUPT_DMA1 32
+
+#define CYGNUM_HAL_ISR_MIN 0
+#define CYGNUM_HAL_ISR_MAX 32
+#define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX+1)
+
+#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TIMER1
+
+//----------------------------------------------------------------------------
+// Reset.
+
+#define HAL_PLATFORM_RESET() \
+do { \
+ *(SWSR)=0x123; \
+ *(SWSR)=0x321; \
+} while(0)
+
+#define HAL_PLATFORM_RESET_ENTRY 0x0
+
+#endif // CYGONCE_HAL_PLATFORM_INTS_H
+
+
diff -urN -x CVS -x doc -x ChangeLog -x powerpc ecos/packages/hal/arm/netarm/current/include/hal_platform_setup.h ecos.my/packages/hal/arm/netarm/current/include/hal_platform_setup.h
--- ecos/packages/hal/arm/netarm/current/include/hal_platform_setup.h 1970-01-01 01:00:00.000000000 +0100
+++ ecos.my/packages/hal/arm/netarm/current/include/hal_platform_setup.h 2002-10-26 20:54:43.000000000 +0200
@@ -0,0 +1,139 @@
+#ifndef CYGONCE_HAL_PLATFORM_SETUP_H
+#define CYGONCE_HAL_PLATFORM_SETUP_H
+
+/*=============================================================================
+//
+// hal_platform_setup.h
+//
+// Bootstrap support for HAL (assembly code)
+//
+//=============================================================================
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): Peter De Schrijver (p2@mind.be)
+// Contributors: Peter De Schrijver (p2@mind.be)
+// Date: 2002-10-19
+// Purpose: NetSilicon NET+ARM evaluation board specific support routines
+// Description:
+// Usage: #include <cyg/hal/hal_platform_setup.h>
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================*/
+
+#include <pkgconf/system.h> // System-wide configuration info
+#include <pkgconf/hal.h> // Architecture independent configuration
+#include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
+#include <cyg/hal/hal_netarm.h> // Platform specific hardware definitions
+#include <cyg/hal/hal_mmu.h> // MMU definitions
+
+#define CYGHWR_LED_MACRO ldr r1,=0xffb00028; \
+ ldr r0,[r1]; \
+ orr r0,r0,#6 ;\
+ bic r0,r0, #((\x & 3)<<1); \
+ str r0,[r1]
+
+#if defined(CYG_HAL_STARTUP_ROMRAM)
+#define HAL_FLASH_PHYS_ADDR 0x02000000
+#define UNMAPPED(x) ((x)-0x08000000)
+#elif defined(CYG_HAL_STARTUP_ROM)
+#define HAL_FLASH_PHYS_ADDR 0x02000000
+#define UNMAPPED(x) ((x)-0x02000000)
+#endif
+ .macro PLATFORM_SETUP1
+
+
+#if defined(CYG_HAL_STARTUP_ROMRAM) || defined(CYG_HAL_STARTUP_ROM)
+ mov r1,#0xff000000
+ orr r1,r1,#0xb00000 /* Setup GEN Module base addr */
+
+ ldr r0,=0x4004a800 /* System control register */
+ str r0,[r1]
+
+ mov r0,#0 /* PLL config */
+ str r0,[r1,#8]
+
+ ldr r0,=0xfff00000 /* PORT A mode & dir */
+ str r0,[r1,#0x20]
+
+ ldr r0,=0xfff00000 /* PORT B mode & dir */
+ str r0,[r1,#0x24]
+
+ ldr r0,=0xb07e0006 /* PORT C mode & dir */
+ str r0,[r1,#0x28]
+
+ add r1,r1,#0x100000 /* Setup MEM Module base addr */
+
+ ldr r0,=0x148C0000 /* Memory Module Config register */
+ str r0,[r1]
+
+ ldr r2,=0xffb00028 /* green LED on */
+ ldr r0,[r2]
+ and r0,r0,#~2
+ str r0,[r2]
+
+ ldr r2,=UNMAPPED(10f)
+ add r2,r2,#HAL_FLASH_PHYS_ADDR
+
+ ldr r0,=0xf3f00304 /* CS0 Option register */
+ str r0,[r1,#0x14]
+
+ ldr r0,=0x02000001 /* CS0 Base Address register */
+ str r0,[r1,#0x10]
+
+ mov pc,r2 /* Jump to new flash base */
+10:
+
+ ldr r2,=0xffb00028 /* yellow LED on */
+ ldr r0,[r2]
+ and r0,r0,#~4
+ str r0,[r2]
+
+ /* Configure SDRAM */
+
+ ldr r0,=0xf38000b0 /* CS1 Option register, BLEN=11 */
+ str r0,[r1,#0x24]
+
+ ldr r0,=0x0000022d /* CS1 Base Address register */
+ str r0,[r1,#0x20]
+
+ mov r4,#0x00000000 /* Dummy read */
+ ldr r0,[r4],#4
+ ldr r0,[r4],#4
+ ldr r0,[r4],#4
+ ldr r0,[r4],#4
+ ldr r0,[r4],#4
+ ldr r0,[r4],#4
+
+
+#if defined(CYG_HAL_STARTUP_ROMRAM)
+ mov r1,#0
+ mov r2,#HAL_FLASH_PHYS_ADDR
+ ldr r3,=(__heap1 - 0x04000000 + HAL_FLASH_PHYS_ADDR)
+
+ mov r4,#0
+ mov r6,#0
+20:
+ ldr r0,[r2],#4
+ eor r6,r6,r0
+ str r0,[r1]
+ ldr r5,[r1],#4
+ eor r4,r4,r5
+ cmp r2,r3
+ bne 20b
+
+ ldr r0,=30f /* And we go back to RAM */
+
+ mov pc,r0
+ nop
+ nop
+ nop
+30:
+#endif
+
+#endif
+ .endm
+
+#endif
+
diff -urN -x CVS -x doc -x ChangeLog -x powerpc ecos/packages/hal/arm/netarm/current/include/pkgconf/mlt_arm_netarm_ram.h ecos.my/packages/hal/arm/netarm/current/include/pkgconf/mlt_arm_netarm_ram.h
--- ecos/packages/hal/arm/netarm/current/include/pkgconf/mlt_arm_netarm_ram.h 1970-01-01 01:00:00.000000000 +0100
+++ ecos.my/packages/hal/arm/netarm/current/include/pkgconf/mlt_arm_netarm_ram.h 2002-10-19 21:38:24.000000000 +0200
@@ -0,0 +1,15 @@
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+extern unsigned int _dataram;
+#define CYGMEM_REGION_ram (&_dataram)
+#define CYGMEM_REGION_ram_SIZE (16*1024*1024)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE ((cyg_uint32)CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
+
diff -urN -x CVS -x doc -x ChangeLog -x powerpc ecos/packages/hal/arm/netarm/current/include/pkgconf/mlt_arm_netarm_ram.ldi ecos.my/packages/hal/arm/netarm/current/include/pkgconf/mlt_arm_netarm_ram.ldi
--- ecos/packages/hal/arm/netarm/current/include/pkgconf/mlt_arm_netarm_ram.ldi 1970-01-01 01:00:00.000000000 +0100
+++ ecos.my/packages/hal/arm/netarm/current/include/pkgconf/mlt_arm_netarm_ram.ldi 2002-10-20 22:04:57.000000000 +0200
@@ -0,0 +1,36 @@
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+ noncacheram : ORIGIN = 0, LENGTH = 16*1024*1024
+ dataram : ORIGIN = 0x4000000, LENGTH = 16*1024*1024
+ codecacheram : ORIGIN = 0x8000000, LENGTH = 16*1024*1024
+}
+
+SECTIONS
+{
+ SECTIONS_BEGIN
+ _dataram = 0x4000000;
+ SECTION_rom_vectors (nocacheram, 0x0, LMA_EQ_VMA)
+ SECTION_fixed_vectors (nocacheram, ALIGN (0x4), LMA_EQ_VMA)
+ code_start = . + 0x8000000;
+ SECTION_text (codecacheram, code_start, AT (code_start - 0x8000000))
+ fini = .;
+ SECTION_fini (codecacheram, ALIGN (0x4), AT (fini - 0x8000000))
+ rodata = .;
+ SECTION_rodata (codecacheram, ALIGN (0x4), AT (rodata - 0x8000000))
+ rodata1 = .;
+ SECTION_rodata1 (codecacheram, ALIGN (0x4), AT (rodata1 - 0x8000000))
+ fixup = .;
+ SECTION_fixup (codecacheram, ALIGN (0x4), AT (fixup - 0x8000000))
+ gcc_except_table =.;
+ SECTION_gcc_except_table (codecacheram, ALIGN (0x4), AT (gcc_except_table - 0x8000000))
+ data_start = ALIGN(0x4) - 0x4000000;
+ SECTION_data (dataram, data_start, AT (data_start - 0x4000000))
+ bss = .;
+ SECTION_bss (dataram, ALIGN (0x4), AT (bss - 0x4000000))
+ CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+ SECTIONS_END
+}
+
+
diff -urN -x CVS -x doc -x ChangeLog -x powerpc ecos/packages/hal/arm/netarm/current/include/pkgconf/mlt_arm_netarm_rom.h ecos.my/packages/hal/arm/netarm/current/include/pkgconf/mlt_arm_netarm_rom.h
--- ecos/packages/hal/arm/netarm/current/include/pkgconf/mlt_arm_netarm_rom.h 1970-01-01 01:00:00.000000000 +0100
+++ ecos.my/packages/hal/arm/netarm/current/include/pkgconf/mlt_arm_netarm_rom.h 2002-10-19 21:38:41.000000000 +0200
@@ -0,0 +1,15 @@
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+extern unsigned int _dataram;
+#define CYGMEM_REGION_ram (&_dataram)
+#define CYGMEM_REGION_ram_SIZE (16*1024*1024)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE ((cyg_uint32)CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
+
diff -urN -x CVS -x doc -x ChangeLog -x powerpc ecos/packages/hal/arm/netarm/current/include/pkgconf/mlt_arm_netarm_rom.ldi ecos.my/packages/hal/arm/netarm/current/include/pkgconf/mlt_arm_netarm_rom.ldi
--- ecos/packages/hal/arm/netarm/current/include/pkgconf/mlt_arm_netarm_rom.ldi 1970-01-01 01:00:00.000000000 +0100
+++ ecos.my/packages/hal/arm/netarm/current/include/pkgconf/mlt_arm_netarm_rom.ldi 2002-10-26 20:51:22.000000000 +0200
@@ -0,0 +1,38 @@
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+ noncacheram : ORIGIN = 0, LENGTH = 16*1024*1024
+ rom : ORIGIN = 0x2000000, LENGTH = 2*1024*1024
+ dataram : ORIGIN = 0x4000000, LENGTH = 16*1024*1024
+ codecacheram : ORIGIN = 0x8000000, LENGTH = 16*1024*1024
+}
+
+SECTIONS
+{
+ SECTIONS_BEGIN
+ _dataram = 0x4000000;
+ SECTION_rom_vectors (rom, 0x02000000, AT (0))
+ SECTION_fixed_vectors (nocacheram, 0x20, LMA_EQ_VMA)
+ code_start = . + 0x02000000;
+ SECTION_text (rom, code_start, AT (code_start - 0x2000000))
+ fini = .;
+ SECTION_fini (rom, ALIGN (0x4), AT (fini - 0x2000000))
+ rodata = .;
+ SECTION_rodata (rom, ALIGN (0x4), AT (rodata - 0x2000000))
+ rodata1 = .;
+ SECTION_rodata1 (rom, ALIGN (0x4), AT (rodata1 - 0x2000000))
+ fixup = .;
+ SECTION_fixup (rom, ALIGN (0x4), AT (fixup - 0x2000000))
+ gcc_except_table = .;
+ SECTION_gcc_except_table (rom, ALIGN (0x4), AT (gcc_except_table - 0x2000000))
+ data_start = 0x4001000;
+ SECTION_data (dataram, data_start, FOLLOWING (.gcc_except_table))
+ __rom_data_start += 0x02000000;
+ bss = . ;
+ SECTION_bss (dataram, ALIGN (0x4), LMA_EQ_VMA)
+ CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+ SECTIONS_END
+}
+
+
diff -urN -x CVS -x doc -x ChangeLog -x powerpc ecos/packages/hal/arm/netarm/current/include/pkgconf/mlt_arm_netarm_romram.h ecos.my/packages/hal/arm/netarm/current/include/pkgconf/mlt_arm_netarm_romram.h
--- ecos/packages/hal/arm/netarm/current/include/pkgconf/mlt_arm_netarm_romram.h 1970-01-01 01:00:00.000000000 +0100
+++ ecos.my/packages/hal/arm/netarm/current/include/pkgconf/mlt_arm_netarm_romram.h 2002-10-25 15:36:17.000000000 +0200
@@ -0,0 +1,15 @@
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+extern unsigned int _dataram;
+#define CYGMEM_REGION_ram (&_dataram)
+#define CYGMEM_REGION_ram_SIZE (16*1024*1024)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE ((cyg_uint32)CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
+
diff -urN -x CVS -x doc -x ChangeLog -x powerpc ecos/packages/hal/arm/netarm/current/include/pkgconf/mlt_arm_netarm_romram.ldi ecos.my/packages/hal/arm/netarm/current/include/pkgconf/mlt_arm_netarm_romram.ldi
--- ecos/packages/hal/arm/netarm/current/include/pkgconf/mlt_arm_netarm_romram.ldi 1970-01-01 01:00:00.000000000 +0100
+++ ecos.my/packages/hal/arm/netarm/current/include/pkgconf/mlt_arm_netarm_romram.ldi 2002-10-25 15:36:23.000000000 +0200
@@ -0,0 +1,36 @@
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+ noncacheram : ORIGIN = 0, LENGTH = 16*1024*1024
+ dataram : ORIGIN = 0x4000000, LENGTH = 16*1024*1024
+ codecacheram : ORIGIN = 0x8000000, LENGTH = 16*1024*1024
+}
+
+SECTIONS
+{
+ SECTIONS_BEGIN
+ _dataram = 0x4000000;
+ SECTION_rom_vectors (nocacheram, 0x0, LMA_EQ_VMA)
+ SECTION_fixed_vectors (nocacheram, ALIGN (0x4), LMA_EQ_VMA)
+ code_start = . + 0x8000000;
+ SECTION_text (codecacheram, code_start, AT (code_start - 0x8000000))
+ fini = .;
+ SECTION_fini (codecacheram, ALIGN (0x4), AT (fini - 0x8000000))
+ rodata = .;
+ SECTION_rodata (codecacheram, ALIGN (0x4), AT (rodata - 0x8000000))
+ rodata1 = .;
+ SECTION_rodata1 (codecacheram, ALIGN (0x4), AT (rodata1 - 0x8000000))
+ fixup = .;
+ SECTION_fixup (codecacheram, ALIGN (0x4), AT (fixup - 0x8000000))
+ gcc_except_table = .;
+ SECTION_gcc_except_table (codecacheram, ALIGN (0x4), AT (gcc_except_table - 0x8000000))
+ data_start = . - 0x4000000;
+ SECTION_data (dataram, data_start, AT (data_start - 0x4000000))
+ bss = .;
+ SECTION_bss (dataram, ALIGN (0x4), AT (bss - 0x4000000))
+ CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+ SECTIONS_END
+}
+
+
diff -urN -x CVS -x doc -x ChangeLog -x powerpc ecos/packages/hal/arm/netarm/current/include/plf_io.h ecos.my/packages/hal/arm/netarm/current/include/plf_io.h
--- ecos/packages/hal/arm/netarm/current/include/plf_io.h 1970-01-01 01:00:00.000000000 +0100
+++ ecos.my/packages/hal/arm/netarm/current/include/plf_io.h 2002-10-19 21:41:12.000000000 +0200
@@ -0,0 +1 @@
+#include <cyg/hal/hal_netarm.h>
diff -urN -x CVS -x doc -x ChangeLog -x powerpc ecos/packages/hal/arm/netarm/current/include/plf_stub.h ecos.my/packages/hal/arm/netarm/current/include/plf_stub.h
--- ecos/packages/hal/arm/netarm/current/include/plf_stub.h 1970-01-01 01:00:00.000000000 +0100
+++ ecos.my/packages/hal/arm/netarm/current/include/plf_stub.h 2002-10-25 12:00:52.000000000 +0200
@@ -0,0 +1,55 @@
+#ifndef CYGONCE_HAL_PLF_STUB_H
+#define CYGONCE_HAL_PLF_STUB_H
+
+//=============================================================================
+//
+// plf_stub.h
+//
+// Platform header for GDB stub support.
+//
+//=============================================================================
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): jskov
+// Contributors:jskov, gthomas
+// Date: 1999-04-21
+// Purpose: Platform HAL stub support for Cirrus EDB7XXX boards.
+// Usage: #include <cyg/hal/plf_stub.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_arm_netarm.h>
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+#include <cyg/infra/cyg_type.h> // CYG_UNUSED_PARAM
+
+#include <cyg/hal/arm_stub.h> // architecture stub support
+
+//----------------------------------------------------------------------------
+// Define some platform specific communication details. This is mostly
+// handled by hal_if now, but we need to make sure the comms tables are
+// properly initialized.
+
+externC void cyg_hal_plf_comms_init(void);
+
+#define HAL_STUB_PLATFORM_INIT_SERIAL() cyg_hal_plf_comms_init()
+
+#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud))
+#define HAL_STUB_PLATFORM_INTERRUPTIBLE 0
+#define HAL_STUB_PLATFORM_INIT_BREAK_IRQ() CYG_EMPTY_STATEMENT
+
+//----------------------------------------------------------------------------
+// Stub initializer.
+#define HAL_STUB_PLATFORM_INIT() CYG_EMPTY_STATEMENT
+
+#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_PLF_STUB_H
+// End of plf_stub.h
+
+
diff -urN -x CVS -x doc -x ChangeLog -x powerpc ecos/packages/hal/arm/netarm/current/src/hal_diag.c ecos.my/packages/hal/arm/netarm/current/src/hal_diag.c
--- ecos/packages/hal/arm/netarm/current/src/hal_diag.c 1970-01-01 01:00:00.000000000 +0100
+++ ecos.my/packages/hal/arm/netarm/current/src/hal_diag.c 2002-10-19 21:03:55.000000000 +0200
@@ -0,0 +1,575 @@
+/*=============================================================================
+//
+// hal_diag.c
+//
+// HAL diagnostic output code
+//
+//=============================================================================
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): p2@mind.be
+// Contributors:p2@mind.be
+// Date: 2002-10-19
+// Purpose: HAL diagnostic output
+// Description: Implementations of HAL diagnostic output support.
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================*/
+
+#include <pkgconf/hal.h>
+#include <pkgconf/system.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#include <cyg/infra/cyg_type.h> // base types
+#include <cyg/infra/cyg_trac.h> // tracing macros
+#include <cyg/infra/cyg_ass.h> // assertion macros
+
+#include <cyg/hal/hal_arch.h> // basic machine info
+#include <cyg/hal/hal_intr.h> // interrupt macros
+#include <cyg/hal/hal_io.h> // IO macros
+#include <cyg/hal/hal_if.h> // calling interface API
+#include <cyg/hal/hal_misc.h> // helper functions
+#include <cyg/hal/hal_diag.h>
+#include <cyg/hal/drv_api.h>
+#include <cyg/hal/hal_netarm.h> // Hardware definitions
+
+struct netarm_serial {
+ cyg_uint32 ccr_a;
+ cyg_uint32 ccr_b;
+ cyg_uint32 sr_a;
+ cyg_uint32 brr;
+ cyg_uint32 fdr;
+ cyg_uint32 rbt;
+ cyg_uint32 rct;
+ cyg_uint32 rmr;
+ cyg_uint32 rmmr;
+ cyg_uint32 ccr_c;
+ cyg_uint32 sr_b;
+ cyg_uint32 sr_c;
+};
+
+typedef struct {
+ volatile struct netarm_serial* base;
+ cyg_int32 msec_timeout;
+ int isr_vector;
+ cyg_uint8 buffer[8];
+ int buffer_count;
+ int read_index;
+} channel_data_t;
+
+static void cyg_hal_plf_serial_init_channel(channel_data_t* __ch_data) {
+
+ channel_data_t* chan = (channel_data_t*)__ch_data;
+
+ chan->base->ccr_b=SERIAL_MODE_ASYNC|SERIAL_RCGT;
+ chan->base->rct=SERIAL_TRUN;
+ chan->base->brr=SERIAL_EBIT
+ | UART_BITRATE(CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD);
+ chan->base->ccr_a=SERIAL_CE | (SERIAL_WLEN8 <<24);
+
+ chan->buffer_count=0;
+ chan->read_index=0;
+}
+
+void cyg_hal_plf_serial_putc(void *__ch_data, char c) {
+
+ channel_data_t* chan = (channel_data_t*)__ch_data;
+
+ CYGARC_HAL_SAVE_GP();
+
+ while(!(chan->base->sr_a & SERIAL_TEMPTY));
+
+ *((cyg_uint8 *)(&chan->base->fdr))=c;
+
+ CYGARC_HAL_RESTORE_GP();
+
+}
+
+cyg_uint8 cyg_hal_plf_serial_getc(void* __ch_data) {
+
+ channel_data_t* chan = (channel_data_t*)__ch_data;
+ int count;
+ cyg_uint32 word, validbytes;
+ cyg_uint8 c;
+
+ CYGARC_HAL_SAVE_GP();
+
+ if(chan->buffer_count) {
+ chan->buffer_count--;
+ c=chan->buffer[chan->read_index];
+ chan->read_index++;
+ chan->read_index&=7;
+ CYGARC_HAL_RESTORE_GP();
+ return c;
+ }
+
+ while(!(chan->base->sr_a & SERIAL_RREADY)) {
+ while(!(chan->base->sr_a & (SERIAL_RREADY|SERIAL_RBC)));
+ if(chan->base->sr_a & SERIAL_RBC)
+ chan->base->sr_a|=SERIAL_RBC;
+ }
+
+ validbytes=(chan->base->sr_a >> 20) & 0x3;
+ word=chan->base->fdr;
+
+ c=word >> 24;
+ word&=0xffffff;
+
+ count=0;
+ switch(validbytes) {
+ case 0:
+ chan->buffer[(chan->buffer_count+2)&7]=word &0xff;
+ count++;
+ case 3:
+ chan->buffer[(chan->buffer_count+1)&7]=(word &0xff00) >> 8;
+ count++;
+ case 2:
+ chan->buffer[chan->buffer_count]=(word & 0xff0000) >> 16;
+ count++;
+ }
+
+ chan->buffer_count+=count;
+ chan->buffer_count&=7;
+
+ CYGARC_HAL_RESTORE_GP();
+ return c;
+
+}
+
+static channel_data_t netarm_ser_channels[2] = {
+ {(volatile struct netarm_serial *)SERIALA, 1000, CYGNUM_HAL_INTERRUPT_SERARX},
+ {(volatile struct netarm_serial *)SERIALB, 1000, CYGNUM_HAL_INTERRUPT_SERARX}};
+
+static void cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf, cyg_uint32 __len) {
+
+ CYGARC_HAL_SAVE_GP();
+
+ while(__len-- > 0)
+ cyg_hal_plf_serial_putc(__ch_data, *__buf++);
+
+ CYGARC_HAL_RESTORE_GP();
+
+}
+
+static void cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len) {
+
+ CYGARC_HAL_SAVE_GP();
+
+ while(__len-- > 0)
+ *__buf++ = cyg_hal_plf_serial_getc(__ch_data);
+
+ CYGARC_HAL_RESTORE_GP();
+
+}
+
+cyg_bool cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch) {
+
+ int delay_count;
+ channel_data_t* chan = (channel_data_t*)__ch_data;
+ cyg_bool res;
+
+ CYGARC_HAL_SAVE_GP();
+
+ delay_count = chan->msec_timeout * 10;
+
+ for(;;) {
+
+ if(chan->base->sr_a & (SERIAL_RREADY|SERIAL_RBC)) {
+ *ch=cyg_hal_plf_serial_getc(__ch_data);
+ res=true;
+ break;
+ }
+
+ if(!delay_count) {
+ res=false;
+ break;
+ }
+
+ delay_count--;
+ CYGACC_CALL_IF_DELAY_US(100);
+ }
+
+ CYGARC_HAL_RESTORE_GP();
+ return res;
+
+}
+
+static int cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...) {
+
+ static int irq_state = 0;
+ channel_data_t* chan = (channel_data_t*)__ch_data;
+ int ret=0;
+ CYGARC_HAL_SAVE_GP();
+
+ switch (__func) {
+ case __COMMCTL_IRQ_ENABLE:
+ irq_state = 1;
+ chan->base->rmr=(3<<24);
+ chan->base->rmmr=0;
+ chan->base->ccr_b|=SERIAL_RDM1;
+ chan->base->ccr_a|=SERIAL_RBC_IE;
+ HAL_INTERRUPT_UNMASK(chan->isr_vector);
+ break;
+
+ case __COMMCTL_IRQ_DISABLE:
+ ret = irq_state;
+ irq_state = 0;
+ HAL_INTERRUPT_MASK(chan->isr_vector);
+ chan->base->ccr_a&=~SERIAL_RBC_IE;
+ chan->base->ccr_b&=~SERIAL_RDM1;
+ break;
+
+ case __COMMCTL_DBG_ISR_VECTOR:
+ ret = chan->isr_vector;
+ break;
+
+ case __COMMCTL_SET_TIMEOUT:
+ {
+ va_list ap;
+
+ va_start(ap, __func);
+
+ ret = chan->msec_timeout;
+ chan->msec_timeout = va_arg(ap, cyg_uint32);
+
+ va_end(ap);
+ }
+
+ default:
+ break;
+ }
+
+ CYGARC_HAL_RESTORE_GP();
+
+ return ret;
+
+}
+
+static int cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc, CYG_ADDRWORD __vector, CYG_ADDRWORD __data) {
+
+ int res = 0,count;
+ channel_data_t* chan = (channel_data_t*)__ch_data;
+ cyg_uint32 word, validbytes;
+ char c;
+
+ CYGARC_HAL_SAVE_GP();
+
+ cyg_drv_interrupt_acknowledge(chan->isr_vector);
+
+ *__ctrlc = 0;
+ if (chan->base->sr_a & SERIAL_RBC) {
+
+ chan->base->sr_a|=SERIAL_RBC;
+
+ if(chan->base->sr_a & SERIAL_RREADY) {
+ validbytes=(chan->base->sr_a >> 20) & 0x3;
+ word=chan->base->fdr;
+ count=0;
+
+ c=word >> 24;
+
+ if( cyg_hal_is_break( &c , 1 ) )
+ *__ctrlc = 1;
+ else {
+ chan->buffer[chan->buffer_count]=c;
+ chan->buffer_count++;
+ chan->buffer_count&=7;
+ }
+
+ switch(validbytes) {
+ case 0:
+ chan->buffer[(chan->buffer_count+2)&7]=word &0xff;
+ count++;
+ case 3:
+ chan->buffer[(chan->buffer_count+1)&7]=(word &0xff00) >> 8; count++;
+ case 2:
+ chan->buffer[chan->buffer_count]=(word & 0xff0000) >> 16;
+ count++;
+ }
+ chan->buffer_count+=count;
+ chan->buffer_count&=7;
+ }
+
+ }
+ res=CYG_ISR_HANDLED;
+
+ CYGARC_HAL_RESTORE_GP();
+ return res;
+
+}
+
+static void cyg_hal_plf_serial_init(void) {
+
+ hal_virtual_comm_table_t* comm;
+ int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
+
+ HAL_INTERRUPT_MASK(netarm_ser_channels[0].isr_vector);
+ HAL_INTERRUPT_MASK(netarm_ser_channels[1].isr_vector);
+
+ cyg_hal_plf_serial_init_channel(&netarm_ser_channels[0]);
+ cyg_hal_plf_serial_init_channel(&netarm_ser_channels[1]);
+
+ // Setup procs in the vector table
+
+ // Set channel 0
+ CYGACC_CALL_IF_SET_CONSOLE_COMM(0);
+ comm = CYGACC_CALL_IF_CONSOLE_PROCS();
+ CYGACC_COMM_IF_CH_DATA_SET(*comm, &netarm_ser_channels[0]);
+ CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
+ CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
+ CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
+ CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
+ CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
+ CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
+ CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
+
+ // Set channel 1
+ CYGACC_CALL_IF_SET_CONSOLE_COMM(1);
+ comm = CYGACC_CALL_IF_CONSOLE_PROCS();
+ CYGACC_COMM_IF_CH_DATA_SET(*comm, &netarm_ser_channels[1]);
+ CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
+ CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
+ CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
+ CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
+ CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
+ CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
+ CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
+
+ // Restore original console
+ CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
+}
+
+void
+cyg_hal_plf_comms_init(void)
+{
+ static int initialized = 0;
+
+ if (initialized)
+ return;
+
+ initialized = 1;
+
+ cyg_hal_plf_serial_init();
+}
+
+//=============================================================================
+// Compatibility with older stubs
+//=============================================================================
+
+#ifndef CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+#include <cyg/hal/hal_stub.h> // cyg_hal_gdb_interrupt
+#endif
+
+// Assumption: all diagnostic output must be GDB packetized unless this is a ROM (i.e.
+// totally stand-alone) system.
+
+#ifdef CYGSEM_HAL_ROM_MONITOR
+#define CYG_HAL_STARTUP_ROM
+#undef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+#endif
+
+
+#if defined(CYG_HAL_STARTUP_ROM) && !defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
+#define HAL_DIAG_USES_HARDWARE
+#else
+#if !defined(CYGDBG_HAL_DIAG_TO_DEBUG_CHAN)
+#define HAL_DIAG_USES_HARDWARE
+#elif CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL != CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL
+#define HAL_DIAG_USES_HARDWARE
+#endif
+#endif
+
+#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 0
+# define __BASE ((volatile struct netarm_serial*)SERIALA)
+# define __IRQ CYGNUM_HAL_INTERRUPT_URXINT1
+#else
+# define __BASE ((volatile struct netarm_serial*)SERIALB)
+# define __IRQ CYGNUM_HAL_INTERRUPT_URXINT2
+#endif
+
+static channel_data_t netarm_ser_channel = {
+ __BASE, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+// NetARM Serial Port (UARTx) for Debug
+
+// Actually send character down the wire
+static void
+hal_diag_write_char_serial(char c)
+{
+ cyg_hal_plf_serial_putc(&netarm_ser_channel, c);
+}
+
+static bool
+hal_diag_read_serial(char *c)
+{
+ long timeout = 1000000000; // A long time...
+
+ for(;;) {
+
+ if(netarm_ser_channel.base->sr_a & SERIAL_RREADY) {
+ *c=cyg_hal_plf_serial_getc(&netarm_ser_channel);
+ return true;
+ break;
+ }
+
+ if(--timeout == 0) {
+ return false;
+ }
+
+ }
+
+}
+
+#ifdef HAL_DIAG_USES_HARDWARE
+
+void hal_diag_init(void)
+{
+ static int init = 0;
+#ifndef CYG_HAL_STARTUP_ROM
+ char *msg = "\n\rRAM NetARM eCos\n\r";
+#endif
+ if (init++) return;
+
+ cyg_hal_plf_serial_init_channel(&netarm_ser_channel);
+
+#ifndef CYG_HAL_STARTUP_ROM
+ while (*msg) hal_diag_write_char(*msg++);
+#endif
+}
+
+#ifdef DEBUG_DIAG
+#ifndef CYG_HAL_STARTUP_ROM
+#define DIAG_BUFSIZE 2048
+static char diag_buffer[DIAG_BUFSIZE];
+static int diag_bp = 0;
+#endif
+#endif
+
+void hal_diag_write_char(char c)
+{
+ hal_diag_init();
+#ifdef DEBUG_DIAG
+#ifndef CYG_HAL_STARTUP_ROM
+ diag_buffer[diag_bp++] = c;
+ if (diag_bp == sizeof(diag_buffer)) diag_bp = 0;
+#endif
+#endif
+ hal_diag_write_char_serial(c);
+}
+
+void hal_diag_read_char(char *c)
+{
+ while (!hal_diag_read_serial(c)) ;
+}
+
+#else // HAL_DIAG relies on GDB
+
+// Initialize diag port
+void hal_diag_init(void)
+{
+ // Assume port is already setup
+ if (0) cyg_hal_plf_serial_init_channel(&netarm_ser_channel);
+}
+
+void
+hal_diag_read_char(char *c)
+{
+ while (!hal_diag_read_serial(c)) ;
+}
+
+void
+hal_diag_write_char(char c)
+{
+ static char line[100];
+ static int pos = 0;
+
+ // No need to send CRs
+ if( c == '\r' ) return;
+
+ line[pos++] = c;
+
+ if( c == '\n' || pos == sizeof(line) )
+ {
+
+ CYG_INTERRUPT_STATE old;
+
+ // Disable interrupts. This prevents GDB trying to interrupt us
+ // while we are in the middle of sending a packet. The serial
+ // receive interrupt will be seen when we re-enable interrupts
+ // later.
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION(old);
+#else
+ HAL_DISABLE_INTERRUPTS(old);
+#endif
+
+ while(1)
+ {
+ static char hex[] = "0123456789ABCDEF";
+ cyg_uint8 csum = 0;
+ int i;
+ char c1;
+
+ hal_diag_write_char_serial('$');
+ hal_diag_write_char_serial('O');
+ csum += 'O';
+ for( i = 0; i < pos; i++ )
+ {
+ char ch = line[i];
+ char h = hex[(ch>>4)&0xF];
+ char l = hex[ch&0xF];
+ hal_diag_write_char_serial(h);
+ hal_diag_write_char_serial(l);
+ csum += h;
+ csum += l;
+ }
+ hal_diag_write_char_serial('#');
+ hal_diag_write_char_serial(hex[(csum>>4)&0xF]);
+ hal_diag_write_char_serial(hex[csum&0xF]);
+
+ // Wait for the ACK character '+' from GDB here and handle
+ // receiving a ^C instead. This is the reason for this clause
+ // being a loop.
+ if (!hal_diag_read_serial(&c1))
+ continue; // No response - try sending packet again
+
+ if( c1 == '+' )
+ break; // a good acknowledge
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+ cyg_drv_interrupt_acknowledge(__IRQ);
+ if( c1 == 3 ) {
+ // Ctrl-C: breakpoint.
+ cyg_hal_gdb_interrupt (__builtin_return_address(0));
+ break;
+ }
+#endif
+ // otherwise, loop round again
+ }
+
+ pos = 0;
+
+
+ // And re-enable interrupts
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+ CYG_HAL_GDB_LEAVE_CRITICAL_IO_REGION(old);
+#else
+ HAL_RESTORE_INTERRUPTS(old);
+#endif
+
+ }
+}
+#endif
+
+#endif // !CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+/*---------------------------------------------------------------------------*/
+/* End of hal_diag.c */
+
diff -urN -x CVS -x doc -x ChangeLog -x powerpc ecos/packages/hal/arm/netarm/current/src/netarm_misc.c ecos.my/packages/hal/arm/netarm/current/src/netarm_misc.c
--- ecos/packages/hal/arm/netarm/current/src/netarm_misc.c 1970-01-01 01:00:00.000000000 +0100
+++ ecos.my/packages/hal/arm/netarm/current/src/netarm_misc.c 2002-10-26 22:45:23.000000000 +0200
@@ -0,0 +1,169 @@
+//==========================================================================
+//
+// netarm_misc.c
+//
+// HAL misc board support code for NetSilicon ARM
+//
+//==========================================================================
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): Peter De Schrijver (p2@mind.be)
+// Contributors: Peter De Schrijver (p2@mind.be)
+// Date: 2002-10-25
+// Purpose: HAL board support
+// Description: Implementations of HAL board interfaces
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+#include <pkgconf/hal.h>
+#include <pkgconf/system.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#include <cyg/infra/cyg_type.h> // base types
+#include <cyg/infra/cyg_trac.h> // tracing macros
+#include <cyg/infra/cyg_ass.h> // assertion macros
+
+#include <cyg/hal/hal_io.h> // IO macros
+#include <cyg/hal/hal_arch.h> // Register state info
+#include <cyg/hal/hal_diag.h>
+#include <cyg/hal/hal_intr.h> // Interrupt names
+#include <cyg/hal/hal_cache.h>
+#include <cyg/hal/hal_netarm.h> // Hardware definitions
+#include <cyg/hal/hal_if.h> // calling interface API
+
+static cyg_uint32 _period;
+static cyg_uint32 _resolution;
+
+void hal_clock_initialize(cyg_uint32 period) {
+
+ _period=period;
+ if(period > 511) {
+ *TIMERCON1=TIMERCON_TPRE;
+ period>>=9;
+ _resolution=1000*1000/CYGNUM_HAL_RTC_PERIOD;
+ }
+ else {
+ *TIMERCON1=0;
+ _resolution=512*1000*1000/CYGNUM_HAL_RTC_PERIOD;
+ }
+
+ *TIMERCON1|=(TIMERCON_TE | TIMERCON_TIE) | (period & 0x1ff);
+}
+
+static void __inline__ enable_FIQ(void) {
+
+ asm volatile ("mrs r0,cpsr;"
+ "bic r0,r0,#0x40;"
+ "msr cpsr,r0");
+
+}
+
+void hal_clock_reset(cyg_uint32 vector, cyg_uint32 period) {
+
+ *TIMERSTAT1=TIMERSTAT_TIP;
+
+ if(period!=_period) {
+ hal_clock_initialize(period);
+ }
+
+}
+
+void hal_clock_read(cyg_uint32 *pvalue) {
+
+ static cyg_uint32 clock_val;
+
+ clock_val=*TIMERSTAT1 & 0x1ff;
+ *pvalue = (cyg_uint32)(_period - clock_val);
+
+}
+
+void hal_delay_us(int us) {
+
+ cyg_int32 val, prev;
+
+ while(us >= _resolution) {
+ prev = *TIMERSTAT1 & 0x1ff;
+ while (true) {
+ val=*TIMERSTAT1 & 0x1ff;
+ if(val!=prev)
+ break;
+ }
+ us-=_resolution;
+ }
+}
+
+void hal_hardware_init(void) {
+
+
+#ifdef ENABLECACHE
+ /* CS1 BSIZE = 4 */
+ *OR1&=~(3 << 4);
+ *OR1|=1 << 4;
+
+ HAL_ICACHE_ENABLE();
+#endif /* ENABLECACHE */
+
+
+ *INTENABLE_CLR=0xffffffff;
+
+ hal_clock_initialize(CYGNUM_HAL_RTC_PERIOD);
+
+ hal_if_init();
+
+// HAL_ICACHE_DISABLE();
+
+}
+
+int hal_spurious_ints;
+
+int hal_IRQ_handler(void) {
+
+ cyg_uint32 stat;
+ int i;
+
+ stat=*INTSTATUS;
+
+ for(i=0;i<CYGNUM_HAL_ISR_MAX;i++)
+ if(stat & (1<<i))
+ return i+1;
+
+ hal_spurious_ints++;
+ return CYGNUM_HAL_INTERRUPT_NONE;
+
+}
+
+void hal_interrupt_mask(int vector) {
+
+ *INTENABLE_CLR=1<<(vector-1);
+
+}
+
+void hal_interrupt_unmask(int vector) {
+
+ *INTENABLE_SET=1<<(vector-1);
+
+}
+
+void hal_interrupt_acknowledge(int vector) {
+}
+
+void hal_interrupt_configure(int vector, int level, int up) {
+
+ if((vector>=CYGNUM_HAL_INTERRUPT_C0) && (vector<=CYGNUM_HAL_INTERRUPT_C3)) {
+ *PORTC|=1<< (vector+23);
+ if(up)
+ *PORTC|=1<< (vector+15);
+ else
+ *PORTC&=~(1<< (vector+15));
+ }
+ *PORTC|=1<<(vector-1);
+
+}
+
+void hal_interrupt_set_level(int vector, int level) {
+ // No interrupts are configurable on this hardware
+}
+
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