[ECOS] powerpc serial driver

[Christoph Csebits]

On Thu, Nov 29, 2001 at 04:34:42AM +0000, Jonathan Larmour wrote:
> If quicc_smc1_txbuf isn't aligned, then it won't be
> CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxSIZE long any more.

You are right, i forgot to change some lines before diff.
patch enclosed.

> Also, got a ChangeLog entry?

Is this the way ChangeLog entries are usually made?

2001-11-29  Christoph Csebits  <christoph.csebits@frequentis.com>

        * src/quicc_smc_serial.c
        aligning buffer to cache lines,
        flushing buffer before flushing the device.


regards, christoph
-- 
-------------- next part --------------
--- quicc_smc_serial.c.orig	Thu Nov 29 10:21:38 2001
+++ quicc_smc_serial.c	Thu Nov 29 10:23:21 2001
@@ -54,6 +54,9 @@
 
 #ifdef CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC
 
+// macro for aligning buffers to cache lines
+#define ALIGN_TO_CACHELINES(b,s) (((unsigned long)(b) + (s-1)) & ~(s-1))
+
 // Buffer descriptor control bits
 #define QUICC_BD_CTL_Ready 0x8000  // Buffer contains data (tx) or is empty (rx)
 #define QUICC_BD_CTL_Wrap  0x2000  // Last buffer in list
@@ -154,8 +157,8 @@
     );
 #endif
 
-static unsigned char quicc_smc1_txbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxNUM][CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxSIZE];
-static unsigned char quicc_smc1_rxbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxNUM][CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxSIZE];
+static unsigned char quicc_smc1_txbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxNUM+1][CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxSIZE];
+static unsigned char quicc_smc1_rxbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxNUM+1][CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxSIZE];
 
 DEVTAB_ENTRY(quicc_smc_serial_io1, 
              CYGDAT_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_NAME,
@@ -198,8 +201,8 @@
                       CYG_SERIAL_FLAGS_DEFAULT
     );
 #endif
-static unsigned char quicc_smc2_txbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxNUM][CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxSIZE];
-static unsigned char quicc_smc2_rxbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxNUM][CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxSIZE];
+static unsigned char quicc_smc2_txbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxNUM+1][CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxSIZE];
+static unsigned char quicc_smc2_rxbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxNUM+1][CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxSIZE];
 
 DEVTAB_ENTRY(quicc_smc_serial_io2, 
              CYGDAT_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_NAME,
@@ -398,11 +401,11 @@
                                    TxBD, 
                                    CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxNUM,
                                    CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxSIZE,
-                                   &quicc_smc1_txbuf[0][0],
+                                   (cyg_uint8 *)ALIGN_TO_CACHELINES(&quicc_smc1_txbuf[0][0], 32),
                                    RxBD, 
                                    CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxNUM,
                                    CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxSIZE,
-                                   &quicc_smc1_rxbuf[0][0],
+                                   (cyg_uint8 *)ALIGN_TO_CACHELINES(&quicc_smc1_rxbuf[0][0], 32),
                                    0xC0, // PortB mask
                                    CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_BRG,
                                    12  // SI mask position
@@ -430,11 +433,11 @@
                                    TxBD, 
                                    CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxNUM,
                                    CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxSIZE,
-                                   &quicc_smc2_txbuf[0][0],
+                                   (cyg_uint8 *)ALIGN_TO_CACHELINES(&quicc_smc2_txbuf[0][0], 32),
                                    RxBD, 
                                    CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxNUM,
                                    CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxSIZE,
-                                   &quicc_smc2_rxbuf[0][0],
+                                   (cyg_uint8 *)ALIGN_TO_CACHELINES(&quicc_smc2_rxbuf[0][0], 32),
                                    0xC00, // PortB mask
                                    CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_BRG,
                                    28  // SI mask position
@@ -475,6 +478,13 @@
 quicc_smc_serial_flush(quicc_smc_serial_info *smc_chan)
 {
     volatile struct cp_bufdesc *txbd = smc_chan->txbd;
+    int cache_state;
+                                       
+    HAL_DCACHE_IS_ENABLED(cache_state);
+    if (cache_state) {
+      HAL_DCACHE_FLUSH(txbd->buffer, scc_chan->txsize);
+    }
+
     if ((txbd->length > 0) && 
         ((txbd->ctrl & (QUICC_BD_CTL_Ready|QUICC_BD_CTL_Int)) == 0)) {
         txbd->ctrl |= QUICC_BD_CTL_Ready|QUICC_BD_CTL_Int;  // Signal buffer ready