[ECOS] Bug in PPC 405 target.

Dennis Ehlin (ECS) Dennis.Ehlin@ecs.ericsson.se
Fri May 4 08:06:00 GMT 2001

The option "CYGHWR_HAL_POWERPC_VECTOR_BASE  (0xfff00000 or 0x00000000)" 
doesn't work as intended on the PPC405GP and (i think also the PPC403).
Because the MSR_IP bit is not valid for changing the exception vector offset (The IP_BIT is actually marked as reserved in the MSR register).
Instead the EVPR register should be used.
It would be great if I could fix this, but I'm not sure how to tackle the problem, because if I change something in the
"powerpc/arch/current/src/vectors.S" file the changes will affect all PPC targets, and that is not what I want, and
also the cdl file for the PPC arch needs to be changed to allow setting of other exception vector offsets than 0x00000000 and 0xfff00000 for the PPC40x targets.
"User's Manual page 95"
23:25 Reserved
"User's Manual page 884"

Exception Vector Prefix Register

SPR 0x3D6

See "Exception Vector Prefix Register (EVPR)" on page 10-30.

Figure 25-13. Exception Vector Prefix Register (EVPR)

0:15 EVP Exception Vector Prefix 16:31 Reserved


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