[ECOS] x86 floating point exception handler bug(s)

[Neils Nesse]

	There appears to be a bug in the implementation of the floating
point exception hander for x86. The floating point context switching occurs
inside a DSR. If the scheduler is locked when the first floating point
operation since a task switch occurs, then then ISR will execute in an
infinite loop because the TS flag never gets cleared. This whole thing
should really be inside a VSR anyways because the the interrupt overhead is
not really acceptable for this perpose. The ISR and DSR paramaters are
pushed for every FPE, but they are useless to it, they aren't even
referenced. Then the scheduler has to go and check that it doesn't have to
"reschedule" for the FPE which is also useless. Another note, a
read/modify/write on the cr0 register is used to clear the task flag. The
CLTS instruction should be used instead because reads and writes on cr0 are
expensive.

	-Neils