[ECOS] DAI driver and I2S interrupt on edb7xxx

[Franck MAMALET FT-R&D DIH/OCF]

Hi,
I'm trying to install a driver for DAI codec on the edb7xxx.
I had a look to hal/arm/edb7xxx/current/misc/i2s_audio...  to
devellop a i2s_ISR and i2s_DSR and then create and attach them 
to CYGNUM_HAL_INTERRUPT_I2SINT.
Looking at eCos interrupt handling I found something  weird: in
hal_IRQ_handler(hal/arm/edb7xxx/current/src/edb7xxx_misc.c), eCos scans
all interrupts to find the vector number of the first interrupt to handle:
    while (map->first_int) {
        stat = *(volatile cyg_uint32
*)map->stat_reg & *(volatile cyg_uint32 *)map->mask_reg;
        for (vector = map->first_int; 
vector <= map->last_int;  vector++) {
           
if (stat & hal_interrupt_bitmap[vector]) return vector;
        }
        map++;  // Next interrupt
status register
    }
But I2S interrupt vector number is 22 and  is the last one,
so it will be handled after all pending interrupts (even some IRQs)
I think it is not a good idea for a FIQ, and actually it doesn't work. 
I had to change hal_interrupt_status_regmap table to fix it:
"./arm/edb7xxx/current/src/edb7xxx_misc.c"  line 284
static struct regmap {
    int        first_int,
last_int;
    cyg_uint32 stat_reg, mask_reg;
} hal_interrupt_status_regmap[] = {
    { CYGNUM_HAL_INTERRUPT_EXTFIQ, CYGNUM_HAL_INTERRUPT_MCINT, 
INTSR1, INTMR1},
#if defined(__EDB7211)
    { CYGNUM_HAL_INTERRUPT_MCPINT, CYGNUM_HAL_INTERRUPT_MCPINT, 
INTSR3, INTMR3},
#endif
#if defined(__EDB7209)
    { CYGNUM_HAL_INTERRUPT_I2SINT, CYGNUM_HAL_INTERRUPT_I2SINT, 
INTSR3, INTMR3},
#endif
   { CYGNUM_HAL_INTERRUPT_CSINT, CYGNUM_HAL_INTERRUPT_SSEOTI, 
INTSR1, INTMR1},
    { CYGNUM_HAL_INTERRUPT_KBDINT, CYGNUM_HAL_INTERRUPT_URXINT2,
INTSR2, INTMR2},
    { 0, 0, 0}
};
Could you please tell me if  my modification is OK (I mean safe)
? and if the same kind of selection is applied for DSR handling? and
where?
Thanks,
Best regards,
Franck.
 
 
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Mamalet Franck
FTR&D DIH/OCF
Tél  : 04 76 76 45 71   Fax : 04 76 90 34 43
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