[ECOS] Example ISR,DSR for ARM AEB-1

[Gary Thomas]

On 09-Feb-00 k e wrote:
> So, the creation of the ISR in the example you provide
> below will not interfere with the other ISRs?
> Maybe I'm confusing myself by reading the ARM chip
> sheets, but don't all external interrupts cause the
> same IRQ or FIQ to be activated?  And, then it's up
> to the ISR to determine whether or not the external
> interrupt was from ext0 or ext1 or whatever?  Maybe
> the OS is doing more than I thought it was.
> I thought I'd have to have my ISR poll the various
> states to see if the reason for the interrupt was
> ext0 and then somehow tell the OS to stage the DSR
> for ext0.
> If you can help clarify, it would be much appreciated.
> I will try the code example, below.
> 

No, this is all managed by the HAL.  That's [exactly] why there
are separate interrupts which can be connected to ISR/DSR combos.

The idea is to provide sufficient abstraction in the HAL so most
programs don't need to understand the underlying [hardware] that
supports interrupts, just that there may be many of them.  By
setting up the notion of an "interrupt object" which you can
create, you tell the system (HAL) that "when this interrupt occurs,
I want this set of routines to be called".  You don't need to tell
the HAL how to do this - that's its job.

Clear enough?