[ECOS] EDB/EP7212 internal SRAM - only 4K of 37.5K seems usa
Wed Aug 16 12:40:00 GMT 2000
I tried to get this latest fix and it was not there yet so I tried using the patch command and the embedded patch file below.
The patch failed probably because the version Gary was comparing against was also new and not yet posted.
This is where I was looking for the latest CVS:
I also did a full CVS update, but only 1.7 of hal_platform_setup.h was loaded.
In a message dated Wed, 16 Aug 2000 7:05:40 AM Eastern Daylight Time, Gary Thomas <firstname.lastname@example.org> writes:
On 16-Aug-2000 AshCan@aol.com wrote:
> I am using an eCOS build for the Cirrus EP7212 development board. I need to
> use the internal SRAM for some time critical data and in my old environment,
> which is non OS, all 37.5KBytes were available.
> With eCOS, I noticed my code did not work and so I wrote a program to write
> sequentially and read back the internal SRAM (virtual and actual adr =
> 0x60000000). I am only able to read back the first 4KBytes back as if the
> remaining 33.5KBytes were not there. For now I am placing this data in DRAM,
> but need to use internal SRAM eventually.
> I started looking into possible MMU settings in the HAL include files and
> memory map configuration files, but I was getting lost, being new to eCOS.
> 1) I was hoping someone here had an easy answer to what is going on and why.
> 2) Also, how can I read the MMU registers to see what is in there.
Oops, this is something I meant to fix a long time ago :-) Here's a patch:
RCS file: /local/cvsfiles/ecc/ecc/hal/arm/edb7xxx/current/include/hal_platform_setup.h,v
retrieving revision 18.104.22.168
diff -u -5 -p -r22.214.171.124 hal_platform_setup.h
--- hal/arm/edb7xxx/current/include/hal_platform_setup.h 2000/08/15 15:45:02 126.96.36.199
+++ hal/arm/edb7xxx/current/include/hal_platform_setup.h 2000/08/16 10:54:57
@@ -102,11 +102,15 @@
#define PCMCIA0_LA_START 0x40000000
#define PCMCIA0_PA 0x40000000
#define PCMCIA1_LA_START 0x50000000
#define PCMCIA1_PA 0x50000000
#define SRAM_LA_START 0x60000000
+#ifdef CYGHWR_HAL_ARM_EDB7XXX_VARIANT_CL_PS7111 // 4K SRAM
#define SRAM_LA_END 0x60001000
+#else // 72xx - 37.5K SRAM
+#define SRAM_LA_END 0x6000A000
#define SRAM_PA 0x60000000
#define IO_LA_START 0x80000000
#define IO_LA_END 0x80003000
#define IO_PA 0x80000000
@@ -352,17 +356,20 @@
/* SRAM */ ;\
ldr r3,=SRAM_LA_START ;\
ldr r4,=MMU_L1_TYPE_Page|MMU_DOMAIN(0) ;\
orr r4,r4,r2 ;\
str r4,[r1],#4 ;\
- ldr r4,=MMU_L2_TYPE_Small|MMU_AP_Any|MMU_Bufferable|MMU_Cacheable;\
+ ldr r7,=MMU_PAGE_SIZE ;\
+ ldr r5,=SRAM_LA_END ;\
+05: ldr r4,=MMU_L2_TYPE_Small|MMU_AP_Any|MMU_Bufferable|MMU_Cacheable;\
orr r4,r3,r4 ;\
str r4,[r2],#4 ;\
- ldr r3,=SRAM_LA_START+MMU_PAGE_SIZE ;\
+ add r3,r3,r7 ;\
+ cmp r3,r5 ;\
+ bne 05b ;\
ldr r4,=SRAM_LA_START+MMU_SECTION_SIZE ;\
ldr r5,=MMU_L2_TYPE_Fault ;\
- ldr r7,=MMU_PAGE_SIZE ;\
10: str r5,[r2],#4 ;\
add r3,r3,r7 ;\
cmp r3,r4 ;\
bne 10b ;\
ldr r4,=IO_LA_START ;\
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