[ECOS] ppc603e cache sync

[Daniel Kahlin]

Jesper Skov wrote:
> The few other CPUs that have to do this use either a dedicated chunk
> of the address space or read from the ROM. See the TX39 var_cache.h
> file.

Ok, but I have the FLASH marked as cache-inhibited for now, and then it
doesn't work. :(

> The only other place were we do this by steam is in the kcache
> tests. There the array is called 'dca' - data cache array or some
> such. Not something that has been blessed with official policy (yet).

I will have to put and ifdef:ed array somewhere in the hal. 
maybe in arch/hal_misc.c.
 cyg_uint8 hal_data_cache_array[HAL_DCACHE_SIZE]

> Doesn't it have the implementation specific flush-all command as the
> 603? I don't have my manuals close by, unfortunately, but the 603
> definitely has a one-shot operation for flushing (or is it clearing?)
> the cache.

You probably mean the DCFI bit in HID0.  It invalidates the cache, and
that would be fine, if it wasn't for the cache being writeback.
But maybe I've missed something in the documentation.

> If not, maybe something like the below would be better (from my
> Linux/APUS sources):

The problem with using the 'dcbz' (and all other) cache instructions is
that the operate on memory addresses instead of indexes into the cache.
Normally that is what you want, but if you want to flush all cache
entries into memory you would have to scan the entire 32 bit address
range.   
Trick: Allocate all entries of the cache to an unused area.  

/Daniel

-- 
Daniel Kahlin <daniel.kahlin@netinsight.se>
Hardware System Designer
Net Insight AB
URL: http://www.netinsight.se/