ARM-PXA toolchain

[Yann E. MORIN]

Mircea, Richard, All,

On Tuesday 08 November 2011 18:18:49 Richard Earnshaw wrote:
> On 08/11/11 12:23, Mircea Gherzan wrote:
> > I can't check the coding for I can't compile a simple:
> > 	void my_vstmia(void)
> > 	{
> >     		__asm__("stc     p11, cr8, [ip], #64");
> >     		__asm__("vstmia  ip!, {d8 - d51}");
> > 	}
> 
> That's a heck of a lot of double-precision registers!  Perhaps you meant
> D15, not D51.

Aha! Good catch! :-)

Compiled with Mircea's original toolchain settings, and changing 'd51'
to 'd15' as spotted by Richard, I was able to compile that code snippet
(notice however the -O0 to not optimise at all):

  $ arm-unknown-linux-gnueabi-gcc -march=armv7-a -mcpu=cortex-a9 \
                                  -mfpu=vfpv3-d16 -mhard-float   \
                                  -O0 -o ess.o -c ess.c
  $ arm-unknown-linux-gnueabi-objdump -d ess.o
[--SNIP--]
  00000000 <my_vstmia>:
     0: e52db004        push    {fp}            ; (str fp, [sp, #-4]!)
     4: e28db000        add     fp, sp, #0
     8: ecac8b10        vstmia  ip!, {d8-d15}
     c: ecac8b10        vstmia  ip!, {d8-d15}
    10: e28bd000        add     sp, fp, #0
    14: e8bd0800        pop     {fp}
    18: e12fff1e        bx      lr

At any optimisation level,  -O{s,1,2,3}, the assembly now looks like:

  00000000 <my_vstmia>:
     0:   ecac8b10        vstmia  ip!, {d8-d15}
     4:   ecac8b10        vstmia  ip!, {d8-d15}
     8:   e12fff1e        bx      lr

So yes, the stc and the vstmia opcodes in the code snippet above are both
encoded into the same assembly instruction. But still, it does not tell
whether it's due to 'as' being smart, or the two opcodes actually being
the same in that situation...

Anyway, I would highly be surprised that eglibc would not run on non-VFP
hardware at all. So definitely, it looks (to me) like a bug in QEMU.

Regards,
Yann E. MORIN.

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