More ARM binutils fuckage

[Martin Guy]

> > accesses the code segment thorough the data cache, causing a cache
> > flush.
>
> ITYM cache miss.

A cache miss would be no big deal. But (modern) ARMs have separate
instruction and data caches. As I understand it, it has to access the
code segment with a data-fetch instruction, which refetches the data
from RAM through the data cache. I would have thought that invalidates
the version of that page cached in the instruction cache to avoid
cache conflict, so when the system call returns, the code page gets
fetched yet again into the instruction cache.

But I may be wrong :)

    M

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