EABI and ARM context switching
Michael K. Edwards
Wed Dec 6 04:25:00 GMT 2006
(Added firstname.lastname@example.org in hope of obtaining comments on
TLS/NPTL from someone who knows more than I do about context switching
on the ARM. Sending again with a revised subject.)
On 12/5/06, Lennert Buytenhek <email@example.com> wrote:
> No, it doesn't, it's a vanilla xscale v2 based CPU.
Are you using a particular CPU tuning? I am working with (and tuning
for) an ARM926EJ-S, and will need to choose a tuning for an IXP425
soon. You need at least armv5t for EABI, right?
> I didn't try until 2.6.19-rc1 or so, but that works fine. I haven't
> tried with any external patches but I don't see why it wouldn't work.
Have you run into any problems with EABI and early boot stages? My
last couple of kernel build attempts resulted in strangely scrambled
text in the "Uncompressing linux...." message, followed by a hang. I
am starting to wonder whether some of the arch/mach assembly for this
CPU/board (not that different from a Versatile) is incompatible with
>> You wouldn't happen to have benchmarked a thread-intensive load on
>> your hardware with and without NPTL, would you? I would expect the
>> gain to be significant from not blowing MMU context on every thread
>> switch, but I haven't seen hard numbers on ARM.
> Why would LinuxThreads 'blow MMU context on every thread switch'?
TLB and cache impacts of context switching on (some) ARMs are
discussed in http://www.ertos.nicta.com.au/publications/papers/Wiggins_TUH_03.ps.gz.
This is not my area of expertise and I don't know to what extent
newer ARM and XScale cores or the current mechanisms of TLS/NPTL
improve the situation. I have copied firstname.lastname@example.org,
which appears to be a good way to reach people who have studied this
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