Building a mips toolchain for an AMD Alchemy processor and problems

[Ted Schroeder]

I'm trying to build a toolchain using the crossgcc scripts for an AMD 
Alchmey processor. I'm configuring with gcc-3.4.2, glibc-2.3.3, 
binutils-2.15 and a kernel based on 2.4.20 (some modifications to 
support our specific hardware platform).

When I begin running the script things go pretty well until I start 
building the glibc-headers. At that point I get an error caused by 
picking up the wordsize.h file from sysdeps/mips/bits directory. The 
problem I get here is that instead of specifying a specific wordsize 
__WORDSIZE is defined to _MIPS_SZPTR. Now, I presume, that this should 
get #defined someplace, but it's not obvious how this is supposed to be 
done. I "patched" this to just #define _MIPS_SZPTR to 32 in that same 
file, but then I run into the next problem.

When I'm building the main glibc I get errors in the memcpy.S file 
assembly. The registers t4-t7 are not defined. This appears to be 
because the _MIPS_SIM preprocessor symbol is not being defined to 
MIPS_SIM_ABI32. (I don't know for sure what it's being defined to, but 
it's some sort of builtin, as far as I can tell).

At any rate, it seems that both of these errors are related and there is 
something fundamentally wrong in the way that I am running or 
configuring the script or something.

Any hints or suggestions greatfully accepted.

Thanks,

Ted Schroeder
FreeHand Systems, Inc.

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