Optimiser and memory mapped I/O

[Ken Rose]

Toralf Lund wrote:
> OK, this time I think I've found a genuine problem with the optimiser.
> 
> Consider the following code:
> 
>  *(char *)0xfe8001= 0x4;       /* call msg at level4 */
>  *(char *)0xfe8003= 0x6;       /* generate vector, edge interrupt */
> 
>  *(char *)0xfe8001= 0x6;       /* timer interrupt level 6 */
>  *(char *)0xfe8003= 0x0;       /* level interrupt */
> 
>  *(char *)0xfe8001= 0x2;       /* parallel interrupt level 2 */
>  *(char *)0xfe8003= 0x2;       /* edge interrupt */
> 
>  *(char *)0xfe8005= 0x18;      /* vectors $18, $19, .. $1F */
> 
>  *(char *)0xfe8007= 0xff;      /* enable all interupts */
> 
> Simply put, the optimizer seems to think this is equivalent to
>  *(char *)0xfe8001= 0x2;       /* parallel interrupt level 2 */
>  *(char *)0xfe8003= 0x2;       /* edge interrupt */
> 
>  *(char *)0xfe8005= 0x18;      /* vectors $18, $19, .. $1F */
> 
>  *(char *)0xfe8007= 0xff;      /* enable all interrupts */
> 
> which it would be if 0xfe8001 and 0xfe8003 were normal memory locations. 
> The problem is, they aren't; they are I/O maps. Write to 0xfe8001 is 
> used for register select, and 0xfe8003 gets the actual value of the 
> register. Any ways around this (besides not optimising at all)?

Yes.

s/(char *)/(volatile char *)/

  - ken


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