powerpc-eabi subroutine calls

Peter Barada pbarada@mail.wm.sps.mot.com
Tue Dec 11 20:52:00 GMT 2001


>> GCC generates a "bl" (Opcode 0x48000000) for procedure
>> calls. Unfortunately this PPC instruction allows only 24bit (signed)
>> relative offset, i.e. the branch destination must be within +-8MByte
>> distance from the caller.
>>
>
>This is not true... gcc is generating absolutely correct code in this
>case! 
>
>The "bl" instruction uses the link register (LR) as a target address,
>and with link register the core can achieve every position within
>4Gbytes of the PowerPC 32-bit implementation) address space... 
>
>Please, take a look into "PowerPC Microprocessor Family: The
>Programming Environments for 32-Bit Microprocessor". It's free on the
>Motorola web site. 

I'm sorry to disagree, but from the documentaion, the 'bl' instruction
will branch to a address specified as PC-relative using 24 bits of
address, and updates the LR with the return address.  The 'blrl'
branches to the contents of the LR.  THe issue is that the two memory
segments are farther apart than the 16MB that the 24 offset bits in
the 'bl' instruction can encode, which is why you get the linker error:

>       relocation truncated to fit: R_PPC_REL24 foo

--

Peter Barada                                   Peter.Barada@motorola.com
Wizard                                         781-852-2768 (direct)
WaveMark Solutions(wholly owned by Motorola)   781-270-0193 (fax)

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