PowerPC and Volatile

[Julien Ducourthial]

Michael Schwingen wrote:
On Fri, Dec 01, 2000 at 03:36:56PM -0500, Roger Racine
wrote:
> Naturally, the locations we are talking about are declared volatile,
so the
> compiler does not optimize the code, but the PowerPC has its own
> optimization in the form of pipelining, and it seems to be causing
this
> problem.
>
> The question is, should the compiler be inserting an "eieio" instruction
at
> the sequence points in the code, such as the end of the loop mentioned
> above?  This PPC instruction tells the processor to hold off
its
> pipelining.  We have been inserting them in the code ourselves,
but it is a
> bit of a pain to have to do it.
If this memory is in some IO space, it might be easier to set up the
MMU so
that this address range is set to noncached/serialzed mode[1], ie.
read/write accesses are not re-ordered by the bus logic.
cu
Michael
[1] Not sure about the exact term on the PPC, this is from the 68040
manual,
but the PPC has the same under a different name.
 
Unfortunately there is no such thing on PowerPC, even when set as non-cached
and guarded (the most conservative setting) you may get out of order accesses.
-- 
Julien Ducourthial       julien.ducourthial@detexis.thomson-csf.com 
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