Register save/restore options.
Bill Pringlemeir
bpringle@teklogix.com
Mon May 3 14:09:00 GMT 1999
Sorry, this isn't directly involved with cross-compiler building.
Please refer me to any mailing list that is more relavent.
I have run across several situation where gcc and now egcs will do
a spill of registers to the stack using nifty instructions like:
PowerPC : lswi / stswi
ARM : ldm / stm
68k : movem / movem
x86 : pusha / popa (?? long time no see)
These instructions are usually atomic and aren't nice when you want
to minimize system interrupt latency. An alternative I have seen is
to replace the multiple instruction with many moves. This tends to
explode the code.
Would a code generation option that made longest register spill
instruction used equivalent to the next longest instruction length be
possible? I suppose this is heavily dependant on the wait states (memory
speed) of the particular processor. For instances, many multiply and
divide instructions are about a 1/4 or half the time to spill the
registers.
If the compiler would generate two multiple move instructions instead of
one, the interrupt latency would be cut in half, without a huge expansion
of code.
I looked through the latest info pages and couldn't find an option that
would relate to what I am talking about. I think that it could be more
than just a target dependant option. I don't think it is important to
have exacting control, just being able to graduate the amount of 'atomic
spilling' would be nice.
thanks,
Bill Pringlemeir
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