Aaron J. Grier
Mon Dec 6 14:33:00 GMT 1999

I finally got a 5-chip interface together from the Canadian schematics,
but it's still not working quite as expected.  The schematics label the
one-shot driving the BERR line as supposedly putting out a 10µs pulse,
but using a 2.2nf cap and 4.7k resistor only gives a 4µs pulse.

Without the bus monitor enabled, I get garbage back for memory reads.
(0x40159580, to be specific.)  With the bus monitor enabled, memory
reads appear as they're working, but my initial problem of not being
able to set SIM registers still stands:

(gdb) set *(short *)0xfffa00 = 0x62ff
BDM error: Target Bus Error

however, now I can continue to read memory.  (Previously, any subsequent
memory read would give me a bus error.)

The question I have is how exactly does BERR\ on the BDM connector tie
in to sending / receiving BDM commands?  What's the theory behind the
one-shot that drives BERR\?

I'm also clocking my 68331 with a 32kHz crystal, and planning on using
the '331 synthesizer to run at 25Mhz.  Of course when starting a BDM
session, the clock hasn't been ramped up yet.  Could this be a problem?

  Aaron J. Grier   |   Frye Electronics, Tigard, OR   |
  "The simplistic anthropomorphism which asserts that source code has a
   life separate from its creator or maintainer is the product of one
   too many viewings of Tron."  -- paraphrasing of anonymous post on /.

Want more information?  See the CrossGCC FAQ,
Want to unsubscribe? Send a note to

More information about the crossgcc mailing list