BUG: non-fixed-length ISAs are unsupported for now

[Jose E. Marchesi]

    Z80 has istructions from 1 byte (nop for example) up to 4 bytes long (eZ80
    up to 6 bytes) including operands 0..2 bytes (eZ80 0..3 bytes). So
    base-insn-bitsize is set to 8. And it is not enought for 1-3 bytes (eZ80
    1-4) insn code size (w/o immediate operands).

Then your base-insn-bitsize should be 8.

The key here is: how are opcodes expressed in your ISA?  Do they appear
in the first base insn only, or they are scattered in the optional bytes
in long instructions?

CGEN currently has two limitations in its implementation:
1) It does not support having opcodes (i.e. entries of the form (f-FOO
   VAL) in (+ ) field descriptions) past the first 64 bits of an
   instruction.
2) It does not support to have opcode fields placed in their own word.

These limitations have bitten me in the BPF port and, at the moment, I
have a couple of workarounds in place, but it would be nice to remove
them.

For an example of an instruction set with variable length instructions
see cpu/ia32.cpu in the CGEN distribution for an example of
variable-length instruction set.  However, the "FIXME" annotations in
instructions that (f-reg/opcode 0) are most probably there because that
opcode field is not applied properly, since it is defined to be in the
second word of the instruction (limitation (2) above.)