[PATCH] Experimental 24-bit wordsize cpu model [was Re: Assignment papers needed]

[Dave Korn]

Frank Ch. Eigler wrote:
> Hi -
> 
> On Sat, Jul 25, 2009 at 08:43:16PM +0100, Dave Korn wrote:
> 
>> [...] I'm sure it needs an assign, so can someone put the wheels in
>> motion to get the papers snailed out to me?  (I'll send my details
>> off-list to whoever needs them.)
> 
> At the present moment, no such assignments are required.  You're
> welcome to keep copyright to the cpu files.  Should data from them be
> generated for inclusion in binutils or elsewhere, then you'll need FSF
> assignments for those (generated) files.
> 
> We are in negotiations with the FSF about donating cgen to the
> binutils project, at which point any current cgen-side code would have
> to be reassigned.  If you have an FSF assignment on file, this could
> semi-automatically apply to the .cpu file at that time.

  Excellent.  Well, with no further ado, here is the new port.  It's a
thoroughly toy implementation to serve as a proof of concept and help shake
out bugs or limitations in cgen and the wider binutils toolchain relating to
unusually-sized machine words.

  In order for cgen not to fall down in a heap with an "unable to find precise
mode to match cpu word-bitsize 24" error, it also requires the attached patch
to cgen/mode.scm and include/opcode/cgen.h to add 24-bit-wide integer modes.

  I have assignments on file for gcc, gdb and binutils (and no current
employer), and indeed have bfd/binutils/gas/ld working for this port and
intend to contribute them upstream.  The original thread in the list archive
is (split across a quarter boundary):

http://sourceware.org/ml/cgen/2009-q2/threads.html#00056
http://sourceware.org/ml/cgen/2009-q3/threads.html#00009

cgen/ChangeLog:

	* cpu/toy24.cpu: New CPU description file.
	* cpu/toy24.opc: Corresponding new opcodes support file.
	* mode.scm (TQI, UTQI): Add new 24-bit integer modes.

include/opcode/ChangeLog:

	* cgen.h (CGEN_MODE_TQI, CGEN_MODE_UTQI): Add new enum
	cgen_mode values corresponding to new modes.

  How does that all look?  I know there are a bunch of repeated insn
definitions that I could clean up with some pmacros, but that's an
optimisation that I thought I'd leave for later - I'll probably want to add a
bunch more ALU ops sometime soon anyway so I'll do it then.

    cheers,
      DaveK

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