unable to find precise mode to match cpu word-bitsize 24

[Doug Evans]

Dave Korn wrote:
> Doug Evans wrote:
>   
>> Dave Korn wrote:
>>     
>>> Doug Evans wrote:
>>>
>>>  
>>>       
>>>> This is new ground so we can decide how we want things to look, and then
>>>> make it work.
>>>>     
>>>>         
>>>   Well, what I'd particularly like in this case would be for my pc to
>>> increment by one for each 24-bit insn, rather than have the model
>>> pretend to
>>> be an 8-bit CISC machine processing all 3-byte instructions, if you
>>> see what I
>>> mean.
>>>   
>>>       
>> Righto.  That should be doable regardless.
>>     
>
>   I hope so.  Should I just take the blunt sledgehammer approach, and define
> setters and getters for hardware units h-addr and h-iaddr that multiply/divide
> by 3 on the fly, and let the underlying framework pretend it's a CISC machine
> that uses 3-byte operands and data?  Or is there a cleaner way to go?
>
>   

Sorry for the slow reply.

Regarding "and let the underlying framework pretend ...", I think it 
depends on the framework.  If you want to run a simulator on linux, say, 
what would you *want* it to look like?

I think it should be possible to define things as you want in the 
description file, and then have the app source generators deal with the 
mapping from the architecture description to the app's implementation of 
that description.  We'll probably need to extend the opcodes and 
simulator generators, but if it's the right thing to do, let's do it.

IOW I'm not sure I'd add hardware setters/getters to do the mapping.  
Instead I'd like to see if the appropriate information could be passed 
to the simulator generator and it would generate its own getters/setters 
(or just make calls to something that is then provided by the underlying 
framework).