how can one achieve pipelined operation?

[Joseph A]

As was suggested I have been trying to implement a pipeline with the (delay N
(set ... ...)) directive using the directions given in the [RFA:] Fix
breakage of manually building SID CPU thread, however my port has multiple
ISAs.  I get two errors which say "error: invalid initialization of
reference of type '%ISA1%::write_stacks&' from expression of type
'%CPU%::write_stacks'" and "error: invalid initialization of reference of
type '%ISA2%::write_stacks&' from expression of type '%CPU%::write_stacks'". 
Also, the machine generated reset() and writeback() functions are empty. 
Did I miss something stupid?
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