branch-delay slot semantics questions

[Ben Elliston]

>>>>> "lehotsky" == lehotsky  <lehotsky@earthlink.net> writes:

  lehotsky> Is there also any support for dealing with the semantics that
  lehotsky> "a branch in the delay-slot is always annulled".  I think I can
  lehotsky> implement this by having two bits in the ISA's (setup-semantics (..))
  lehotsky> code.  

On some architectures, certain classes of instructions are forbidden
in the delay slot.  If this is what you really want, it's easiest to
detect this condition during instruction extraction ("fetching").
Again, see the fr30/mloop.in for an illustration.

Ben