memory usage

[Ben Elliston]

   I have a question relating to the simulator part of CGEN.  In the
   future, will it be possible to define different caches (both for insn
   and data) or should this be handled with the simulator "backend"
   (i.e., hardware types).

Do you mean "address spaces" or "caches"?  CGEN doesn't take care of
modelling data or instruction caches.  It already differentiates between
insn and data fetches (see GETIMEM* in generated code, for instance).

Ben