multi-length instruction words

[Eric Christopher]

Okay, I've got a chip that has a multi-issue dispatch unit, and a
strange instruction word format.  I'm thinking that cgen should be able
to deal with this, but it may need an extension.

Here's the instruction word:

[prefix][insn][insn]

Where prefix is 8 bits, and each insn is 28 bits.  I'd like to get it to
where I can define the instruction word to cgen - something like:

(define-liw
	(prefix (length foo)
		(decode-assist x y z)
		(unit u-exec-3))
	(insn	(length foo)
		(decode-assist 25 26 27 32 33)
		(unit u-exec-4))

	.
	.
	.
)

And so on.  Scalable for different types of instruction words. 
Currently (afaict) all of the liw and vliw features that we have assume
that all we're doing is pulling multiple instructions of the same length
- i doubt that this will be the case most of the time.

Any advice?  Is there actually some way to do this that I've been
missing?  Is this something that we want to do in cgen?

-eric