From 374c5706ee00afc3767c67f15da01d8f8cbe1ef1 Mon Sep 17 00:00:00 2001
From: MayShao-oc <MayShao-oc@zhaoxin.com>
Date: Fri, 17 Jan 2025 19:05:15 +0800
Subject: [PATCH] x86: Add CpuGMISM2 and CpuGMICCS
Hi all:
  There are separate CPUID feature bits for SM2 and CCS instructions.
CCS is the acronym of chinese cipher system, it includes SM3 and SM4 
instructions. This patch adds CpuGMISM2 and CpuGMICCS to replace CpuGMI on 
corresponding instructions.

BR
MayShao 

gas/ChangeLog:

	* config/tc-i386.c: Add gmism2 and gmiccs to replace gmi.
	* doc/c-i386.texi: Ditto.

opcodes/ChangeLog:

	* i386-gen.c: Add GMISM2 and GMICCS to replace GMI.
	* i386-opc.h (enum i386_cpu): Add  CpuGMISM2 and CpuGMICCS to
	  replace CpuGMI.
	* i386-opc.tbl: Replace GMI with GMISM2 on sm2 instruction. Replace GMI
	  with GMICCS on sm3 and sm4 instructions.
	* i386-tbl.h: Regenerated.
	* i386-mnem.h: Ditto.
	* i386-init.h: Ditto.

---
 gas/config/tc-i386.c |  3 ++-
 gas/doc/c-i386.texi  |  7 ++++---
 opcodes/i386-gen.c   |  3 ++-
 opcodes/i386-opc.h   |  9 ++++++---
 opcodes/i386-opc.tbl | 10 ++++++----
 5 files changed, 20 insertions(+), 12 deletions(-)

diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index ea370071282..6ca28d7cee1 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1225,7 +1225,8 @@ static const arch_entry cpu_arch[] =
   SUBARCH (user_msr, USER_MSR, USER_MSR, false),
   SUBARCH (apx_f, APX_F, APX_F, false),
   VECARCH (avx10.2, AVX10_2, ANY_AVX10_2, set),
-  SUBARCH (gmi, GMI, GMI, false),
+  SUBARCH (gmism2, GMISM2, GMISM2, false),
+  SUBARCH (gmiccs, GMICCS, GMICCS, false),
   SUBARCH (msr_imm, MSR_IMM, MSR_IMM, false),
   SUBARCH (padlockrng2, PADLOCKRNG2, PADLOCKRNG2, false),
   SUBARCH (padlockphe2, PADLOCKPHE2, PADLOCKPHE2, false),
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index 06bef9048c5..723dbef1c37 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -282,7 +282,8 @@ accept various extension mnemonics.  For example,
 @code{invlpgb},
 @code{tlbsync},
 @code{svme},
-@code{gmi},
+@code{gmism2},
+@code{gmiccs},
 @code{padlockrng2},
 @code{padlockphe2} and
 @code{padlock}.
@@ -1718,8 +1719,8 @@ supported on the CPU specified.  The choices for @var{cpu_type} are:
 @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
 @item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx} @tab @samp{.rdpru}
 @item @samp{.mcommit} @tab @samp{.sev_es} @tab @samp{.snp} @tab @samp{.invlpgb}
-@item @samp{.tlbsync} @tab @samp{.apx_f} @tab @samp{.gmi} @tab @samp{.padlockrng2}
-@item @samp{.padlockphe2}
+@item @samp{.tlbsync} @tab @samp{.apx_f} @tab @samp{.gmism2} @samp{.gmiccs}
+@item @samp{.padlockrng2} @samp{.padlockphe2}
 
 @end multitable
 
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index d2d9b5de006..ae23734156d 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -352,7 +352,8 @@ static bitfield cpu_flags[] =
   BITFIELD (3dnow),
   BITFIELD (3dnowA),
   BITFIELD (PadLock),
-  BITFIELD (GMI),
+  BITFIELD (GMISM2),
+  BITFIELD (GMICCS),
   BITFIELD (PadLockRNG2),
   BITFIELD (PadLockPHE2),
   BITFIELD (SVME),
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index c4751130d29..8ce850ee713 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -66,8 +66,10 @@ enum i386_cpu
   CpuSSE3,
   /* VIA PadLock required */
   CpuPadLock,
-  /* Zhaoxin GMI required */
-  CpuGMI,
+  /* Zhaoxin GMI SM2 required */
+  CpuGMISM2,
+  /* Zhaoxin GMI CCS required */
+  CpuGMICCS,
   /* Zhaoxin PadLock RNG2 required */
   CpuPadLockRNG2,
   /* Zhaoxin PadLock PHE2 required */
@@ -422,7 +424,8 @@ typedef union i386_cpu_flags
       unsigned int cpusse2:1;
       unsigned int cpusse3:1;
       unsigned int cpupadlock:1;
-      unsigned int cpugmi:1;
+      unsigned int cpugmism2:1;
+      unsigned int cpugmiccs:1;
       unsigned int cpupadlockrng2:1;
       unsigned int cpupadlockphe2:1;
       unsigned int cpusvme:1;
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 8b1d155941d..06b1a9d8bdf 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -2134,10 +2134,12 @@ xcryptofb, 0xf30fa7e8, PadLock, NoSuf|RepPrefixOk, {}
 // Alias for xstore-rng.
 xstore, 0xfa7c0, PadLock, NoSuf|RepPrefixOk, {}
 
-// Zhaoxin GMI instructions
-sm2, 0xf20fa6c0, GMI, NoSuf, {}
-sm3, 0xf30fa6e8, GMI, NoSuf, {}
-sm4, 0xf30fa7f0, GMI, NoSuf, {}
+// Zhaoxin GMI SM2 instruction
+sm2, 0xf20fa6c0, GMISM2, NoSuf, {}
+
+// Zhaoxin GMI CCS instructions
+sm3, 0xf30fa6e8, GMICCS, NoSuf, {}
+sm4, 0xf30fa7f0, GMICCS, NoSuf, {}
 
 // Zhaoxin PadLock RNG2 instruction
 xrng2, 0xf30fa7f8, PadLockRNG2, NoSuf|RepPrefixOk, {}
-- 
2.27.0