From 836bf88a8176b1a1d47c89bffe81615a54acad9f Mon Sep 17 00:00:00 2001 From: MayShao-oc Date: Wed, 15 Jan 2025 15:22:04 +0800 Subject: [PATCH] x86: Support x86 Zhaoxin PadLock PHE2 instructions Hi all: This patch adds support for Zhaoxin PadLockPHE2 instructions. The CPUID EDX bit[26] indicates its enablement, and it includes REP XSHA384 and REP XSHA512. Test ok, ok for trunk? BR MayShao gas/ChangeLog: * NEWS: Support Zhaoxin PadLock PHE2 instructions. * config/tc-i386.c (add_branch_prefix_frag_p): Don't add prefix to PadLockPHE2 instructions. (output_insn): Handle PadLockPHE2 instructions. * doc/c-i386.texi: Document PadLockPHE2. * testsuite/gas/i386/i386.exp: Add PadLockPHE2 test. * testsuite/gas/i386/padlock_phe2.d: Ditto. * testsuite/gas/i386/padlock_phe2.s: Ditto. opcodes/ChangeLog: * i386-dis.c: Add PadLockPHE2. * i386-gen.c: Ditto * i386-opc.h (CpuPadLockPHE2): New. * i386-opc.tbl: Add Zhaoxin PadLock PHE2 instructions. * i386-tbl.h: Regenerated. * i386-mnem.h: Ditto. * i386-init.h: Ditto. --- gas/NEWS | 2 ++ gas/config/tc-i386.c | 5 ++++- gas/doc/c-i386.texi | 4 +++- gas/testsuite/gas/i386/i386.exp | 1 + gas/testsuite/gas/i386/padlockphe2.d | 13 +++++++++++++ gas/testsuite/gas/i386/padlockphe2.s | 9 +++++++++ opcodes/i386-dis.c | 4 ++-- opcodes/i386-gen.c | 3 +++ opcodes/i386-opc.h | 3 +++ opcodes/i386-opc.tbl | 4 ++++ 10 files changed, 44 insertions(+), 4 deletions(-) create mode 100644 gas/testsuite/gas/i386/padlockphe2.d create mode 100644 gas/testsuite/gas/i386/padlockphe2.s diff --git a/gas/NEWS b/gas/NEWS index 5c8975dbc44..5251569e8bb 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -1,5 +1,7 @@ -*- text -*- +* Add support for the x86 Zhaoxin PadLock PHE2 instructions. + * Add support for the x86 Zhaoxin PadLock RNG2 instruction. * Add support for AArch64 SME and SVE non-widening BFloat16 (SVE_B16B16 and diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index af1b9988dd8..0b65690aef2 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -1226,6 +1226,7 @@ static const arch_entry cpu_arch[] = SUBARCH (gmi, GMI, GMI, false), SUBARCH (msr_imm, MSR_IMM, MSR_IMM, false), SUBARCH (padlockrng2, PADLOCKRNG2, PADLOCKRNG2, false), + SUBARCH (padlockphe2, PADLOCKPHE2, PADLOCKPHE2, false), }; #undef SUBARCH @@ -12033,6 +12034,7 @@ add_branch_prefix_frag_p (const struct last_insn *last_insn) || now_seg == absolute_section || is_cpu (&i.tm, CpuPadLock) || is_cpu (&i.tm, CpuPadLockRNG2) + || is_cpu (&i.tm, CpuPadLockPHE2) || !cpu_arch_flags.bitfield.cpui386) return 0; @@ -12408,7 +12410,8 @@ output_insn (const struct last_insn *last_insn) break; case PREFIX_0XF3: if ((!is_cpu (&i.tm, CpuPadLock) - && !is_cpu (&i.tm, CpuPadLockRNG2)) + && !is_cpu (&i.tm, CpuPadLockRNG2) + && !is_cpu (&i.tm, CpuPadLockPHE2)) || (i.prefix[REP_PREFIX] != 0xf3)) add_prefix (0xf3); break; diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index 20e21405053..578ae872f0e 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -280,7 +280,8 @@ accept various extension mnemonics. For example, @code{tlbsync}, @code{svme}, @code{gmi}, -@code{padlockrng2} and +@code{padlockrng2}, +@code{padlockphe2} and @code{padlock}. Note that these extension mnemonics can be prefixed with @code{no} to revoke the respective (and any dependent) functionality. Note further that the @@ -1713,6 +1714,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are: @item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx} @tab @samp{.rdpru} @item @samp{.mcommit} @tab @samp{.sev_es} @tab @samp{.snp} @tab @samp{.invlpgb} @item @samp{.tlbsync} @tab @samp{.apx_f} @tab @samp{.gmi} @tab @samp{.padlockrng2} +@item @samp{.padlockphe2} @end multitable diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index fed9283d4ed..1c81909f83e 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -116,6 +116,7 @@ if [gas_32_check] then { run_dump_test "padlock" run_dump_test "gmi" run_dump_test "padlockrng2" + run_dump_test "padlockphe2" run_dump_test "crx" run_list_test "cr-err" "" run_dump_test "cdr" diff --git a/gas/testsuite/gas/i386/padlockphe2.d b/gas/testsuite/gas/i386/padlockphe2.d new file mode 100644 index 00000000000..794e0823a9b --- /dev/null +++ b/gas/testsuite/gas/i386/padlockphe2.d @@ -0,0 +1,13 @@ +#objdump: -dw +#name: Zhaoxin PadLock PHE2 + +.*: +file format .* + +Disassembly of section .text: + +0+000 : + 0:[ ]*f3 0f a6 d8 [ ]*repz xsha384 + 4:[ ]*f3 0f a6 d8 [ ]*repz xsha384 + 8:[ ]*f3 0f a6 e0 [ ]*repz xsha512 + c:[ ]*f3 0f a6 e0 [ ]*repz xsha512 +#pass diff --git a/gas/testsuite/gas/i386/padlockphe2.s b/gas/testsuite/gas/i386/padlockphe2.s new file mode 100644 index 00000000000..0068cb79bbb --- /dev/null +++ b/gas/testsuite/gas/i386/padlockphe2.s @@ -0,0 +1,9 @@ +# Zhaoxin PadLock PHE2 instructions + + .text +foo: + xsha384 + rep xsha384 + xsha512 + rep xsha512 + .p2align 4,0 diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index f9b6cf30fd0..f00062d8dc3 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -2939,8 +2939,8 @@ static const struct dis386 reg_table[][8] = { { PREFIX_TABLE (PREFIX_0FA6_REG_0) }, { "xsha1", { { OP_0f07, 0 } }, 0 }, { "xsha256", { { OP_0f07, 0 } }, 0 }, - { Bad_Opcode }, - { Bad_Opcode }, + { "xsha384", { { OP_0f07, 0 } }, 0 }, + { "xsha512", { { OP_0f07, 0 } }, 0 }, { PREFIX_TABLE (PREFIX_0FA6_REG_5) }, }, /* REG_0FA7 */ diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index 60aa8ddbad7..e1dacfbdf7e 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -293,6 +293,8 @@ static const dependency isa_dependencies[] = "XSAVE|64" }, { "PadLockRNG2", "PadLock" }, + { "PadLockPHE2", + "PadLock" }, }; /* This array is populated as process_i386_initializers() walks cpu_flags[]. */ @@ -348,6 +350,7 @@ static bitfield cpu_flags[] = BITFIELD (PadLock), BITFIELD (GMI), BITFIELD (PadLockRNG2), + BITFIELD (PadLockPHE2), BITFIELD (SVME), BITFIELD (VMX), BITFIELD (SMX), diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index 5d330550205..9e73b3df8b0 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -70,6 +70,8 @@ enum i386_cpu CpuGMI, /* Zhaoxin PadLock RNG2 required */ CpuPadLockRNG2, + /* Zhaoxin PadLock PHE2 required */ + CpuPadLockPHE2, /* AMD Secure Virtual Machine Ext-s required */ CpuSVME, /* VMX Instructions required */ @@ -416,6 +418,7 @@ typedef union i386_cpu_flags unsigned int cpupadlock:1; unsigned int cpugmi:1; unsigned int cpupadlockrng2:1; + unsigned int cpupadlockphe2:1; unsigned int cpusvme:1; unsigned int cpuvmx:1; unsigned int cpusmx:1; diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 32dd883926c..db5f5e750e4 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -2142,6 +2142,10 @@ sm4, 0xf30fa7f0, GMI, NoSuf, {} // Zhaoxin PadLock RNG2 instruction xrng2, 0xf30fa7f8, PadLockRNG2, NoSuf|RepPrefixOk, {} +// Zhaoxin PadLock PHE2 instructions +xsha384, 0xf30fa6d8, PadLockPHE2, NoSuf|RepPrefixOk, {} +xsha512, 0xf30fa6e0, PadLockPHE2, NoSuf|RepPrefixOk, {} + // Multy-precision Add Carry, rdseed instructions. adx, 0x66, ADX&APX_F, C|Modrm|CheckOperandSize|No_bSuf|No_wSuf|No_sSuf|DstVVVV|EVexMap4, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } -- 2.27.0