<div dir="ltr"><div dir="ltr">Committed after passing the regression of riscv-gnu-toolchain. I also merged the fixup-pcrel testcase into the existing fixup-local-pcrel testcase.<br></div><div dir="ltr"><br></div><div>Thanks</div><div>Nelson</div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Thu, Jul 4, 2024 at 11:04 AM Sun Sunny <<a href="mailto:sunny.sun@corelabtech.com">sunny.sun@corelabtech.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">In commit dff565fcca8137954d6ad571ef39f6aec5c0429c, the fixups<br>
for PCREL_LO12_I and PCREL_LO12_S were mixed, so the "IMM"<br>
field were applied to incorrect position, this caused incorrect<br>
src registers to be encoded.<br>
<br>
gas/<br>
* config/tc-riscv.c (md_apply_fix): Fix PCREL_LO12_S issue.<br>
gas/<br>
* testsuite/gas/riscv/fixup-pcrel*: New tests.<br>
<br>
Signed-off-by: Jianwei Sun <<a href="mailto:sunny.sun@corelabtech.com" target="_blank">sunny.sun@corelabtech.com</a>><br>
---<br>
gas/config/tc-riscv.c | 5 +++-<br>
gas/testsuite/gas/riscv/fixup-pcrel.d | 41 +++++++++++++++++++++++++++<br>
gas/testsuite/gas/riscv/fixup-pcrel.s | 11 +++++++<br>
3 files changed, 56 insertions(+), 1 deletion(-)<br>
create mode 100644 gas/testsuite/gas/riscv/fixup-pcrel.d<br>
create mode 100644 gas/testsuite/gas/riscv/fixup-pcrel.s<br>
<br>
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c<br>
index e0083702fbd..4529cf5d75d 100644<br>
--- a/gas/config/tc-riscv.c<br>
+++ b/gas/config/tc-riscv.c<br>
@@ -4707,7 +4707,10 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)<br>
{<br>
bfd_vma target = entry->target;<br>
bfd_vma value = target - entry->address;<br>
- bfd_putl32 (bfd_getl32 (buf) | ENCODE_ITYPE_IMM (value), buf);<br>
+ if (fixP->fx_r_type == BFD_RELOC_RISCV_PCREL_LO12_S)<br>
+ bfd_putl32 (bfd_getl32 (buf) | ENCODE_STYPE_IMM (value), buf);<br>
+ else<br>
+ bfd_putl32 (bfd_getl32 (buf) | ENCODE_ITYPE_IMM (value), buf);<br>
/* Relaxations should never be enabled by `.option relax'. */<br>
if (!riscv_opts.relax)<br>
fixP->fx_done = 1;<br>
diff --git a/gas/testsuite/gas/riscv/fixup-pcrel.d b/gas/testsuite/gas/riscv/fixup-pcrel.d<br>
new file mode 100644<br>
index 00000000000..8ce71ddc0bb<br>
--- /dev/null<br>
+++ b/gas/testsuite/gas/riscv/fixup-pcrel.d<br>
@@ -0,0 +1,41 @@<br>
+#as: -march=rv32i -mabi=ilp32<br>
+#source: fixup-pcrel.s<br>
+#objdump: -dr<br>
+<br>
+.*:[ ]+file format elf32-littleriscv<br>
+<br>
+<br>
+Disassembly of section .text:<br>
+<br>
+00000000 <main>:<br>
+ 0: 00000517 auipc a0,0x0<br>
+ 0: R_RISCV_PCREL_HI20 insn<br>
+ 0: R_RISCV_RELAX *ABS*<br>
+ 4: 00051503 lh a0,0(a0) # 0 <main><br>
+ 4: R_RISCV_PCREL_LO12_I .L0 <br>
+ 4: R_RISCV_RELAX *ABS*<br>
+ 8: 00000597 auipc a1,0x0<br>
+ 8: R_RISCV_PCREL_HI20 insn+0x2<br>
+ 8: R_RISCV_RELAX *ABS*+0x2<br>
+ c: 00059583 lh a1,0(a1) # 8 <main+0x8><br>
+ c: R_RISCV_PCREL_LO12_I .L0 <br>
+ c: R_RISCV_RELAX *ABS*<br>
+ 10: 00000297 auipc t0,0x0<br>
+ 10: R_RISCV_PCREL_HI20 .L1^B1<br>
+ 10: R_RISCV_RELAX *ABS*<br>
+ 14: 00a29823 sh a0,16(t0) # 20 <.L1^B1><br>
+ 14: R_RISCV_PCREL_LO12_S .L0 <br>
+ 14: R_RISCV_RELAX *ABS*<br>
+ 18: 00000297 auipc t0,0x0<br>
+ 18: R_RISCV_PCREL_HI20 .L1^B1+0x2<br>
+ 18: R_RISCV_RELAX *ABS*+0x2<br>
+ 1c: 00b29523 sh a1,10(t0) # 22 <.L1^B1+0x2><br>
+ 1c: R_RISCV_PCREL_LO12_S .L0 <br>
+ 1c: R_RISCV_RELAX *ABS*<br>
+<br>
+00000020 <.L1^B1>:<br>
+ 20: 0de68693 addi a3,a3,222<br>
+ 24: 00008067 ret<br>
+<br>
+00000028 <insn>:<br>
+ 28: 14d68693 addi a3,a3,333<br>
diff --git a/gas/testsuite/gas/riscv/fixup-pcrel.s b/gas/testsuite/gas/riscv/fixup-pcrel.s<br>
new file mode 100644<br>
index 00000000000..0cb1f6e1eb1<br>
--- /dev/null<br>
+++ b/gas/testsuite/gas/riscv/fixup-pcrel.s<br>
@@ -0,0 +1,11 @@<br>
+.global main<br>
+main:<br>
+ lh a0, insn<br>
+ lh a1, insn+2<br>
+ sh a0, 1f, t0<br>
+ sh a1, 1f+2, t0<br>
+1:<br>
+ addi a3, a3, 222<br>
+ ret<br>
+insn:<br>
+ addi a3, a3, 333<br>
-- <br>
2.34.1</blockquote></div></div>