diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 02cf0ade654..2d74ba9d4b1 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -6861,9 +6861,6 @@ parse_operands (char *str, const aarch64_opcode *opcode) case AARCH64_OPND_SVE_ZtxN: case AARCH64_OPND_SME_Zdnx2: case AARCH64_OPND_SME_Zdnx4: - case AARCH64_OPND_SME_Zt2: - case AARCH64_OPND_SME_Zt3: - case AARCH64_OPND_SME_Zt4: case AARCH64_OPND_SME_Zmx2: case AARCH64_OPND_SME_Zmx4: case AARCH64_OPND_SME_Znx2: @@ -7701,6 +7698,7 @@ parse_operands (char *str, const aarch64_opcode *opcode) case AARCH64_OPND_SVE_ADDR_RX_LSL1: case AARCH64_OPND_SVE_ADDR_RX_LSL2: case AARCH64_OPND_SVE_ADDR_RX_LSL3: + case AARCH64_OPND_SVE_ADDR_RX_LSL4: /* [, {, lsl #}] but recognizing SVE registers. */ po_misc_or_fail (parse_sve_address (&str, info, &base_qualifier, diff --git a/gas/testsuite/gas/aarch64/illegal-sve2.l b/gas/testsuite/gas/aarch64/illegal-sve2.l index 20b7a5e1d4d..ca69c2d3cb1 100644 --- a/gas/testsuite/gas/aarch64/illegal-sve2.l +++ b/gas/testsuite/gas/aarch64/illegal-sve2.l @@ -491,7 +491,7 @@ [^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ldnt1b {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]' [^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1b {z0\.d},p0/m,\[z0\.d\]' [^ :]+:[0-9]+: Info: did you mean this\? -[^ :]+:[0-9]+: Info: ldnt1b {z0\.d}, p0/z, \[z0\.d, xzr\] +[^ :]+:[0-9]+: Info: ldnt1b {z0\.d}, p0/z, \[z0\.d\] [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ldnt1b {z32\.d},p0/z,\[z0\.d\]' [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1b {z0\.d},p8/z,\[z0\.d\]' [^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1b {z0\.d},p0/z,\[z32\.d\]' @@ -501,14 +501,14 @@ [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1b {z0\.d},p0/z,\[z0\.d,z0\.d\]' [^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1b {z0\.s},p0/z,\[z0\.d\]' [^ :]+:[0-9]+: Info: did you mean this\? -[^ :]+:[0-9]+: Info: ldnt1b {z0\.s}, p0/z, \[z0\.s, xzr\] +[^ :]+:[0-9]+: Info: ldnt1b {z0\.s}, p0/z, \[z0\.s\] [^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1b {z0\.d},p0/z,\[z0\.s\]' [^ :]+:[0-9]+: Info: did you mean this\? -[^ :]+:[0-9]+: Info: ldnt1b {z0\.s}, p0/z, \[z0\.s, xzr\] +[^ :]+:[0-9]+: Info: ldnt1b {z0\.s}, p0/z, \[z0\.s\] [^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -- `ldnt1b {z0\.s,z1\.d},p0/z,\[z0\.s,x0\]' [^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1b {z0\.s},p0/m,\[z0\.s\]' [^ :]+:[0-9]+: Info: did you mean this\? -[^ :]+:[0-9]+: Info: ldnt1b {z0\.s}, p0/z, \[z0\.s, xzr\] +[^ :]+:[0-9]+: Info: ldnt1b {z0\.s}, p0/z, \[z0\.s\] [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ldnt1b {z32\.s},p0/z,\[z0\.s\]' [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1b {z0\.s},p8/z,\[z0\.s\]' [^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1b {z0\.s},p0/z,\[z32\.s\]' @@ -518,7 +518,7 @@ [^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ldnt1d {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]' [^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1d {z0\.d},p0/m,\[z0\.d\]' [^ :]+:[0-9]+: Info: did you mean this\? -[^ :]+:[0-9]+: Info: ldnt1d {z0\.d}, p0/z, \[z0\.d, xzr\] +[^ :]+:[0-9]+: Info: ldnt1d {z0\.d}, p0/z, \[z0\.d\] [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ldnt1d {z32\.d},p0/z,\[z0\.d\]' [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1d {z0\.d},p8/z,\[z0\.d\]' [^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1d {z0\.d},p0/z,\[z32\.d\]' @@ -528,17 +528,17 @@ [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1d {z0\.d},p0/z,\[z0\.d,z0\.d\]' [^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1d {z0\.s},p0/z,\[z0\.d\]' [^ :]+:[0-9]+: Info: did you mean this\? -[^ :]+:[0-9]+: Info: ldnt1d {z0\.d}, p0/z, \[z0\.d, xzr\] +[^ :]+:[0-9]+: Info: ldnt1d {z0\.d}, p0/z, \[z0\.d\] [^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1d {z0\.d},p0/z,\[z0\.s\]' [^ :]+:[0-9]+: Info: did you mean this\? -[^ :]+:[0-9]+: Info: ldnt1d {z0\.d}, p0/z, \[z0\.d, xzr\] +[^ :]+:[0-9]+: Info: ldnt1d {z0\.d}, p0/z, \[z0\.d\] [^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1d {z0\.d},p0/m,\[z0\.d\]' [^ :]+:[0-9]+: Info: did you mean this\? -[^ :]+:[0-9]+: Info: ldnt1d {z0\.d}, p0/z, \[z0\.d, xzr\] +[^ :]+:[0-9]+: Info: ldnt1d {z0\.d}, p0/z, \[z0\.d\] [^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ldnt1h {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]' [^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1h {z0\.d},p0/m,\[z0\.d\]' [^ :]+:[0-9]+: Info: did you mean this\? -[^ :]+:[0-9]+: Info: ldnt1h {z0\.d}, p0/z, \[z0\.d, xzr\] +[^ :]+:[0-9]+: Info: ldnt1h {z0\.d}, p0/z, \[z0\.d\] [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ldnt1h {z32\.d},p0/z,\[z0\.d\]' [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1h {z0\.d},p8/z,\[z0\.d\]' [^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1h {z0\.d},p0/z,\[z32\.d\]' @@ -548,7 +548,7 @@ [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1h {z0\.d},p0/z,\[z0\.d,z0\.d\]' [^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1h {z0\.s},p0/z,\[z0\.d\]' [^ :]+:[0-9]+: Info: did you mean this\? -[^ :]+:[0-9]+: Info: ldnt1h {z0\.s}, p0/z, \[z0\.s, xzr\] +[^ :]+:[0-9]+: Info: ldnt1h {z0\.s}, p0/z, \[z0\.s\] [^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -- `ldnt1h {z0\.s,z1\.d},p0/z,\[z0\.s,x0\]' [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ldnt1h {z32\.s},p0/z,\[z0\.s\]' [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1h {z0\.s},p8/z,\[z0\.s\]' @@ -559,9 +559,9 @@ [^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ldnt1sb {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]' [^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1sb {z0\.d},p0/m,\[z0\.d\]' [^ :]+:[0-9]+: Info: did you mean this\? -[^ :]+:[0-9]+: Info: ldnt1sb {z0\.d}, p0/z, \[z0\.d, xzr\] +[^ :]+:[0-9]+: Info: ldnt1sb {z0\.d}, p0/z, \[z0\.d\] [^ :]+:[0-9]+: Info: other valid variant\(s\): -[^ :]+:[0-9]+: Info: ldnt1sb {z0\.s}, p0/z, \[z0\.s, xzr\] +[^ :]+:[0-9]+: Info: ldnt1sb {z0\.s}, p0/z, \[z0\.s\] [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ldnt1sb {z32\.d},p0/z,\[z0\.d\]' [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1sb {z0\.d},p8/z,\[z0\.d\]' [^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1sb {z0\.d},p0/z,\[z32\.d\]' @@ -572,9 +572,9 @@ [^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ldnt1sh {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]' [^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1sh {z0\.d},p0/m,\[z0\.d\]' [^ :]+:[0-9]+: Info: did you mean this\? -[^ :]+:[0-9]+: Info: ldnt1sh {z0\.d}, p0/z, \[z0\.d, xzr\] +[^ :]+:[0-9]+: Info: ldnt1sh {z0\.d}, p0/z, \[z0\.d\] [^ :]+:[0-9]+: Info: other valid variant\(s\): -[^ :]+:[0-9]+: Info: ldnt1sh {z0\.s}, p0/z, \[z0\.s, xzr\] +[^ :]+:[0-9]+: Info: ldnt1sh {z0\.s}, p0/z, \[z0\.s\] [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ldnt1sh {z32\.d},p0/z,\[z0\.d\]' [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1sh {z0\.d},p8/z,\[z0\.d\]' [^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z32\.d\]' @@ -585,9 +585,9 @@ [^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ldnt1sh {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]' [^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1sh {z0\.d},p0/m,\[z0\.d\]' [^ :]+:[0-9]+: Info: did you mean this\? -[^ :]+:[0-9]+: Info: ldnt1sh {z0\.d}, p0/z, \[z0\.d, xzr\] +[^ :]+:[0-9]+: Info: ldnt1sh {z0\.d}, p0/z, \[z0\.d\] [^ :]+:[0-9]+: Info: other valid variant\(s\): -[^ :]+:[0-9]+: Info: ldnt1sh {z0\.s}, p0/z, \[z0\.s, xzr\] +[^ :]+:[0-9]+: Info: ldnt1sh {z0\.s}, p0/z, \[z0\.s\] [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ldnt1sh {z32\.d},p0/z,\[z0\.d\]' [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1sh {z0\.d},p8/z,\[z0\.d\]' [^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z32\.d\]' @@ -598,7 +598,7 @@ [^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ldnt1w {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]' [^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1w {z0\.d},p0/m,\[z0\.d\]' [^ :]+:[0-9]+: Info: did you mean this\? -[^ :]+:[0-9]+: Info: ldnt1w {z0\.d}, p0/z, \[z0\.d, xzr\] +[^ :]+:[0-9]+: Info: ldnt1w {z0\.d}, p0/z, \[z0\.d\] [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ldnt1w {z32\.d},p0/z,\[z0\.d\]' [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1w {z0\.d},p8/z,\[z0\.d\]' [^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1w {z0\.d},p0/z,\[z32\.d\]' @@ -608,7 +608,7 @@ [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1w {z0\.d},p0/z,\[z0\.d,z0\.d\]' [^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1w {z0\.s},p0/z,\[z0\.d\]' [^ :]+:[0-9]+: Info: did you mean this\? -[^ :]+:[0-9]+: Info: ldnt1w {z0\.s}, p0/z, \[z0\.s, xzr\] +[^ :]+:[0-9]+: Info: ldnt1w {z0\.s}, p0/z, \[z0\.s\] [^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -- `ldnt1w {z0\.s,z1\.d},p0/z,\[z0\.s,x0\]' [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ldnt1w {z32\.s},p0/z,\[z0\.s\]' [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1w {z0\.s},p8/z,\[z0\.s\]' @@ -2219,7 +2219,7 @@ [^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `stnt1b {z0\.d,z1\.d},p0,\[z0\.d,x0\]' [^ :]+:[0-9]+: Error: operand mismatch -- `stnt1b {z0\.d},p0/m,\[z0\.d\]' [^ :]+:[0-9]+: Info: did you mean this\? -[^ :]+:[0-9]+: Info: stnt1b {z0\.d}, p0, \[z0\.d, xzr\] +[^ :]+:[0-9]+: Info: stnt1b {z0\.d}, p0, \[z0\.d\] [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `stnt1b {z32\.d},p0,\[z0\.d\]' [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1b {z0\.d},p8,\[z0\.d\]' [^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `stnt1b {z0\.d},p0,\[z32\.d\]' @@ -2229,7 +2229,7 @@ [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1b {z0\.d},p0,\[z0\.d,z0\.d\]' [^ :]+:[0-9]+: Error: operand mismatch -- `stnt1b {z0\.s},p0,\[z0\.d\]' [^ :]+:[0-9]+: Info: did you mean this\? -[^ :]+:[0-9]+: Info: stnt1b {z0\.s}, p0, \[z0\.s, xzr\] +[^ :]+:[0-9]+: Info: stnt1b {z0\.s}, p0, \[z0\.s\] [^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -- `stnt1b {z0\.s,z1\.d},p0,\[z0\.s,x0\]' [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `stnt1b {z32\.s},p0,\[z0\.s\]' [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1b {z0\.s},p8,\[z0\.s\]' @@ -2240,7 +2240,7 @@ [^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `stnt1d {z0\.d,z1\.d},p0,\[z0\.d,x0\]' [^ :]+:[0-9]+: Error: operand mismatch -- `stnt1d {z0\.d},p0/m,\[z0\.d\]' [^ :]+:[0-9]+: Info: did you mean this\? -[^ :]+:[0-9]+: Info: stnt1d {z0\.d}, p0, \[z0\.d, xzr\] +[^ :]+:[0-9]+: Info: stnt1d {z0\.d}, p0, \[z0\.d\] [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `stnt1d {z32\.d},p0,\[z0\.d\]' [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1d {z0\.d},p8,\[z0\.d\]' [^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `stnt1d {z0\.d},p0,\[z32\.d\]' @@ -2250,11 +2250,11 @@ [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1d {z0\.d},p0,\[z0\.d,z0\.d\]' [^ :]+:[0-9]+: Error: operand mismatch -- `stnt1d {z0\.s},p0,\[z0\.d\]' [^ :]+:[0-9]+: Info: did you mean this\? -[^ :]+:[0-9]+: Info: stnt1d {z0\.d}, p0, \[z0\.d, xzr\] +[^ :]+:[0-9]+: Info: stnt1d {z0\.d}, p0, \[z0\.d\] [^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `stnt1h {z0\.d,z1\.d},p0,\[z0\.d,x0\]' [^ :]+:[0-9]+: Error: operand mismatch -- `stnt1h {z0\.d},p0/m,\[z0\.d\]' [^ :]+:[0-9]+: Info: did you mean this\? -[^ :]+:[0-9]+: Info: stnt1h {z0\.d}, p0, \[z0\.d, xzr\] +[^ :]+:[0-9]+: Info: stnt1h {z0\.d}, p0, \[z0\.d\] [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `stnt1h {z32\.d},p0,\[z0\.d\]' [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1h {z0\.d},p8,\[z0\.d\]' [^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `stnt1h {z0\.d},p0,\[z32\.d\]' @@ -2264,7 +2264,7 @@ [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1h {z0\.d},p0,\[z0\.d,z0\.d\]' [^ :]+:[0-9]+: Error: operand mismatch -- `stnt1h {z0\.s},p0,\[z0\.d\]' [^ :]+:[0-9]+: Info: did you mean this\? -[^ :]+:[0-9]+: Info: stnt1h {z0\.s}, p0, \[z0\.s, xzr\] +[^ :]+:[0-9]+: Info: stnt1h {z0\.s}, p0, \[z0\.s\] [^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -- `stnt1h {z0\.s,z1\.d},p0,\[z0\.s,x0\]' [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `stnt1h {z32\.s},p0,\[z0\.s\]' [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1h {z0\.s},p8,\[z0\.s\]' @@ -2275,7 +2275,7 @@ [^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `stnt1w {z0\.d,z1\.d},p0,\[z0\.d,x0\]' [^ :]+:[0-9]+: Error: operand mismatch -- `stnt1w {z0\.d},p0/m,\[z0\.d\]' [^ :]+:[0-9]+: Info: did you mean this\? -[^ :]+:[0-9]+: Info: stnt1w {z0\.d}, p0, \[z0\.d, xzr\] +[^ :]+:[0-9]+: Info: stnt1w {z0\.d}, p0, \[z0\.d\] [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `stnt1w {z32\.d},p0,\[z0\.d\]' [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1w {z0\.d},p8,\[z0\.d\]' [^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `stnt1w {z0\.d},p0,\[z32\.d\]' @@ -2285,7 +2285,7 @@ [^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1w {z0\.d},p0,\[z0\.d,z0\.d\]' [^ :]+:[0-9]+: Error: operand mismatch -- `stnt1w {z0\.s},p0,\[z0\.d\]' [^ :]+:[0-9]+: Info: did you mean this\? -[^ :]+:[0-9]+: Info: stnt1w {z0\.s}, p0, \[z0\.s, xzr\] +[^ :]+:[0-9]+: Info: stnt1w {z0\.s}, p0, \[z0\.s\] [^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -- `stnt1w {z0\.s,z1\.d},p0,\[z0\.s,x0\]' [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `stnt1w {z32\.s},p0,\[z0\.s\]' [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1w {z0\.s},p8,\[z0\.s\]' diff --git a/gas/testsuite/gas/aarch64/sme-5-illegal.l b/gas/testsuite/gas/aarch64/sme-5-illegal.l index c4bfc1f8b5a..b0736e0fcd6 100644 --- a/gas/testsuite/gas/aarch64/sme-5-illegal.l +++ b/gas/testsuite/gas/aarch64/sme-5-illegal.l @@ -35,10 +35,10 @@ [^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- `ld1d {za7h.d\[w15,2\]},p7/z,\[sp\]' [^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- `ld1d {za7v.d\[w15,2\]},p7/z,\[x0,x17,lsl#3\]' [^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- `ld1d {za7h.d\[w15,2\]},p7/z,\[sp,x17,lsl#3\]' -[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 1 -- `ld1q {za16v.q\[w12\]},p0/z,\[x0\]' -[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 1 -- `ld1q {za16h.q\[w12\]},p0/z,\[sp\]' -[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 1 -- `ld1q {za16v.q\[w12\]},p0/z,\[x0,x0,lsl#4\]' -[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 1 -- `ld1q {za16h.q\[w12\]},p0/z,\[sp,x0,lsl#4\]' +[^:]*:[0-9]+: Error: expected an SVE vector register or ZA tile slice at operand 1 -- `ld1q {za16v.q\[w12\]},p0/z,\[x0\]' +[^:]*:[0-9]+: Error: expected an SVE vector register or ZA tile slice at operand 1 -- `ld1q {za16h.q\[w12\]},p0/z,\[sp\]' +[^:]*:[0-9]+: Error: expected an SVE vector register or ZA tile slice at operand 1 -- `ld1q {za16v.q\[w12\]},p0/z,\[x0,x0,lsl#4\]' +[^:]*:[0-9]+: Error: expected an SVE vector register or ZA tile slice at operand 1 -- `ld1q {za16h.q\[w12\]},p0/z,\[sp,x0,lsl#4\]' [^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `ld1q {za15v.q\[w15,1\]},p7/z,\[x17\]' [^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `ld1q {za15h.q\[w15,1\]},p7/z,\[sp\]' [^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `ld1q {za15v.q\[w15,1\]},p7/z,\[x0,x17,lsl#4\]' diff --git a/gas/testsuite/gas/aarch64/sme-6-illegal.l b/gas/testsuite/gas/aarch64/sme-6-illegal.l index b98b76faaed..10c2a51204b 100644 --- a/gas/testsuite/gas/aarch64/sme-6-illegal.l +++ b/gas/testsuite/gas/aarch64/sme-6-illegal.l @@ -35,10 +35,10 @@ [^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- `st1d {za7h.d\[w15,2\]},p7,\[sp\]' [^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- `st1d {za7v.d\[w15,2\]},p7,\[x0,x17,lsl#3\]' [^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- `st1d {za7h.d\[w15,2\]},p7,\[sp,x17,lsl#3\]' -[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 1 -- `st1q {za16v.q\[w12\]},p0,\[x0\]' -[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 1 -- `st1q {za16h.q\[w12\]},p0,\[sp\]' -[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 1 -- `st1q {za16v.q\[w12\]},p0,\[x0,x0,lsl#4\]' -[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 1 -- `st1q {za16h.q\[w12\]},p0,\[sp,x0,lsl#4\]' +[^:]*:[0-9]+: Error: expected an SVE vector register or ZA tile slice at operand 1 -- `st1q {za16v.q\[w12\]},p0,\[x0\]' +[^:]*:[0-9]+: Error: expected an SVE vector register or ZA tile slice at operand 1 -- `st1q {za16h.q\[w12\]},p0,\[sp\]' +[^:]*:[0-9]+: Error: expected an SVE vector register or ZA tile slice at operand 1 -- `st1q {za16v.q\[w12\]},p0,\[x0,x0,lsl#4\]' +[^:]*:[0-9]+: Error: expected an SVE vector register or ZA tile slice at operand 1 -- `st1q {za16h.q\[w12\]},p0,\[sp,x0,lsl#4\]' [^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `st1q {za15v.q\[w15,1\]},p7,\[x17\]' [^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `st1q {za15h.q\[w15,1\]},p7,\[sp\]' [^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `st1q {za15v.q\[w15,1\]},p7,\[x0,x17,lsl#4\]' diff --git a/gas/testsuite/gas/aarch64/sve2.d b/gas/testsuite/gas/aarch64/sve2.d index 6c0d94203cb..e9a5bcd7120 100644 --- a/gas/testsuite/gas/aarch64/sve2.d +++ b/gas/testsuite/gas/aarch64/sve2.d @@ -181,50 +181,50 @@ Disassembly of section \.text: *[0-9a-f]+: 4520a000 histseg z0\.b, z0\.b, z0\.b *[0-9a-f]+: c41bd6b1 ldnt1b {z17\.d}, p5/z, \[z21\.d, x27\] *[0-9a-f]+: c400c000 ldnt1b {z0\.d}, p0/z, \[z0\.d, x0\] - *[0-9a-f]+: c41fc000 ldnt1b {z0\.d}, p0/z, \[z0\.d, xzr\] - *[0-9a-f]+: c41fc000 ldnt1b {z0\.d}, p0/z, \[z0\.d, xzr\] + *[0-9a-f]+: c41fc000 ldnt1b {z0\.d}, p0/z, \[z0\.d\] + *[0-9a-f]+: c41fc000 ldnt1b {z0\.d}, p0/z, \[z0\.d\] *[0-9a-f]+: 841bb6b1 ldnt1b {z17\.s}, p5/z, \[z21\.s, x27\] *[0-9a-f]+: 8400a000 ldnt1b {z0\.s}, p0/z, \[z0\.s, x0\] - *[0-9a-f]+: 841fa000 ldnt1b {z0\.s}, p0/z, \[z0\.s, xzr\] - *[0-9a-f]+: 841fa000 ldnt1b {z0\.s}, p0/z, \[z0\.s, xzr\] + *[0-9a-f]+: 841fa000 ldnt1b {z0\.s}, p0/z, \[z0\.s\] + *[0-9a-f]+: 841fa000 ldnt1b {z0\.s}, p0/z, \[z0\.s\] *[0-9a-f]+: c59bd6b1 ldnt1d {z17\.d}, p5/z, \[z21\.d, x27\] *[0-9a-f]+: c580c000 ldnt1d {z0\.d}, p0/z, \[z0\.d, x0\] - *[0-9a-f]+: c59fc000 ldnt1d {z0\.d}, p0/z, \[z0\.d, xzr\] - *[0-9a-f]+: c59fc000 ldnt1d {z0\.d}, p0/z, \[z0\.d, xzr\] + *[0-9a-f]+: c59fc000 ldnt1d {z0\.d}, p0/z, \[z0\.d\] + *[0-9a-f]+: c59fc000 ldnt1d {z0\.d}, p0/z, \[z0\.d\] *[0-9a-f]+: c49bd6b1 ldnt1h {z17\.d}, p5/z, \[z21\.d, x27\] *[0-9a-f]+: c480c000 ldnt1h {z0\.d}, p0/z, \[z0\.d, x0\] - *[0-9a-f]+: c49fc000 ldnt1h {z0\.d}, p0/z, \[z0\.d, xzr\] - *[0-9a-f]+: c49fc000 ldnt1h {z0\.d}, p0/z, \[z0\.d, xzr\] + *[0-9a-f]+: c49fc000 ldnt1h {z0\.d}, p0/z, \[z0\.d\] + *[0-9a-f]+: c49fc000 ldnt1h {z0\.d}, p0/z, \[z0\.d\] *[0-9a-f]+: 849bb6b1 ldnt1h {z17\.s}, p5/z, \[z21\.s, x27\] *[0-9a-f]+: 8480a000 ldnt1h {z0\.s}, p0/z, \[z0\.s, x0\] - *[0-9a-f]+: 849fa000 ldnt1h {z0\.s}, p0/z, \[z0\.s, xzr\] - *[0-9a-f]+: 849fa000 ldnt1h {z0\.s}, p0/z, \[z0\.s, xzr\] + *[0-9a-f]+: 849fa000 ldnt1h {z0\.s}, p0/z, \[z0\.s\] + *[0-9a-f]+: 849fa000 ldnt1h {z0\.s}, p0/z, \[z0\.s\] *[0-9a-f]+: 841b96b1 ldnt1sb {z17\.s}, p5/z, \[z21\.s, x27\] *[0-9a-f]+: 84008000 ldnt1sb {z0\.s}, p0/z, \[z0\.s, x0\] - *[0-9a-f]+: 841f8000 ldnt1sb {z0\.s}, p0/z, \[z0\.s, xzr\] - *[0-9a-f]+: 841f8000 ldnt1sb {z0\.s}, p0/z, \[z0\.s, xzr\] + *[0-9a-f]+: 841f8000 ldnt1sb {z0\.s}, p0/z, \[z0\.s\] + *[0-9a-f]+: 841f8000 ldnt1sb {z0\.s}, p0/z, \[z0\.s\] *[0-9a-f]+: c4008000 ldnt1sb {z0\.d}, p0/z, \[z0\.d, x0\] - *[0-9a-f]+: c41f8000 ldnt1sb {z0\.d}, p0/z, \[z0\.d, xzr\] - *[0-9a-f]+: c41f8000 ldnt1sb {z0\.d}, p0/z, \[z0\.d, xzr\] + *[0-9a-f]+: c41f8000 ldnt1sb {z0\.d}, p0/z, \[z0\.d\] + *[0-9a-f]+: c41f8000 ldnt1sb {z0\.d}, p0/z, \[z0\.d\] *[0-9a-f]+: 849b96b1 ldnt1sh {z17\.s}, p5/z, \[z21\.s, x27\] *[0-9a-f]+: 84808000 ldnt1sh {z0\.s}, p0/z, \[z0\.s, x0\] - *[0-9a-f]+: 849f8000 ldnt1sh {z0\.s}, p0/z, \[z0\.s, xzr\] - *[0-9a-f]+: 849f8000 ldnt1sh {z0\.s}, p0/z, \[z0\.s, xzr\] + *[0-9a-f]+: 849f8000 ldnt1sh {z0\.s}, p0/z, \[z0\.s\] + *[0-9a-f]+: 849f8000 ldnt1sh {z0\.s}, p0/z, \[z0\.s\] *[0-9a-f]+: c4808000 ldnt1sh {z0\.d}, p0/z, \[z0\.d, x0\] - *[0-9a-f]+: c49f8000 ldnt1sh {z0\.d}, p0/z, \[z0\.d, xzr\] - *[0-9a-f]+: c49f8000 ldnt1sh {z0\.d}, p0/z, \[z0\.d, xzr\] + *[0-9a-f]+: c49f8000 ldnt1sh {z0\.d}, p0/z, \[z0\.d\] + *[0-9a-f]+: c49f8000 ldnt1sh {z0\.d}, p0/z, \[z0\.d\] *[0-9a-f]+: c51b96b1 ldnt1sw {z17\.d}, p5/z, \[z21\.d, x27\] *[0-9a-f]+: c5008000 ldnt1sw {z0\.d}, p0/z, \[z0\.d, x0\] - *[0-9a-f]+: c51f8000 ldnt1sw {z0\.d}, p0/z, \[z0\.d, xzr\] - *[0-9a-f]+: c51f8000 ldnt1sw {z0\.d}, p0/z, \[z0\.d, xzr\] + *[0-9a-f]+: c51f8000 ldnt1sw {z0\.d}, p0/z, \[z0\.d\] + *[0-9a-f]+: c51f8000 ldnt1sw {z0\.d}, p0/z, \[z0\.d\] *[0-9a-f]+: 851bb6b1 ldnt1w {z17\.s}, p5/z, \[z21\.s, x27\] *[0-9a-f]+: 8500a000 ldnt1w {z0\.s}, p0/z, \[z0\.s, x0\] - *[0-9a-f]+: 851fa000 ldnt1w {z0\.s}, p0/z, \[z0\.s, xzr\] - *[0-9a-f]+: 851fa000 ldnt1w {z0\.s}, p0/z, \[z0\.s, xzr\] + *[0-9a-f]+: 851fa000 ldnt1w {z0\.s}, p0/z, \[z0\.s\] + *[0-9a-f]+: 851fa000 ldnt1w {z0\.s}, p0/z, \[z0\.s\] *[0-9a-f]+: c51bd6b1 ldnt1w {z17\.d}, p5/z, \[z21\.d, x27\] *[0-9a-f]+: c500c000 ldnt1w {z0\.d}, p0/z, \[z0\.d, x0\] - *[0-9a-f]+: c51fc000 ldnt1w {z0\.d}, p0/z, \[z0\.d, xzr\] - *[0-9a-f]+: c51fc000 ldnt1w {z0\.d}, p0/z, \[z0\.d, xzr\] + *[0-9a-f]+: c51fc000 ldnt1w {z0\.d}, p0/z, \[z0\.d\] + *[0-9a-f]+: c51fc000 ldnt1w {z0\.d}, p0/z, \[z0\.d\] *[0-9a-f]+: 45359629 match p9\.b, p5/z, z17\.b, z21\.b *[0-9a-f]+: 45358220 match p0\.b, p0/z, z17\.b, z21\.b *[0-9a-f]+: 45208000 match p0\.b, p0/z, z0\.b, z0\.b @@ -876,32 +876,32 @@ Disassembly of section \.text: *[0-9a-f]+: 45c05400 ssubwt z0\.d, z0\.d, z0\.s *[0-9a-f]+: e45b36b1 stnt1b {z17\.s}, p5, \[z21\.s, x27\] *[0-9a-f]+: e4402000 stnt1b {z0\.s}, p0, \[z0\.s, x0\] - *[0-9a-f]+: e45f2000 stnt1b {z0\.s}, p0, \[z0\.s, xzr\] - *[0-9a-f]+: e45f2000 stnt1b {z0\.s}, p0, \[z0\.s, xzr\] + *[0-9a-f]+: e45f2000 stnt1b {z0\.s}, p0, \[z0\.s\] + *[0-9a-f]+: e45f2000 stnt1b {z0\.s}, p0, \[z0\.s\] *[0-9a-f]+: e41b36b1 stnt1b {z17\.d}, p5, \[z21\.d, x27\] *[0-9a-f]+: e4002000 stnt1b {z0\.d}, p0, \[z0\.d, x0\] - *[0-9a-f]+: e41f2000 stnt1b {z0\.d}, p0, \[z0\.d, xzr\] - *[0-9a-f]+: e41f2000 stnt1b {z0\.d}, p0, \[z0\.d, xzr\] + *[0-9a-f]+: e41f2000 stnt1b {z0\.d}, p0, \[z0\.d\] + *[0-9a-f]+: e41f2000 stnt1b {z0\.d}, p0, \[z0\.d\] *[0-9a-f]+: e59b36b1 stnt1d {z17\.d}, p5, \[z21\.d, x27\] *[0-9a-f]+: e5802000 stnt1d {z0\.d}, p0, \[z0\.d, x0\] - *[0-9a-f]+: e59f2000 stnt1d {z0\.d}, p0, \[z0\.d, xzr\] - *[0-9a-f]+: e59f2000 stnt1d {z0\.d}, p0, \[z0\.d, xzr\] + *[0-9a-f]+: e59f2000 stnt1d {z0\.d}, p0, \[z0\.d\] + *[0-9a-f]+: e59f2000 stnt1d {z0\.d}, p0, \[z0\.d\] *[0-9a-f]+: e4db36b1 stnt1h {z17\.s}, p5, \[z21\.s, x27\] *[0-9a-f]+: e4c02000 stnt1h {z0\.s}, p0, \[z0\.s, x0\] - *[0-9a-f]+: e4df2000 stnt1h {z0\.s}, p0, \[z0\.s, xzr\] - *[0-9a-f]+: e4df2000 stnt1h {z0\.s}, p0, \[z0\.s, xzr\] + *[0-9a-f]+: e4df2000 stnt1h {z0\.s}, p0, \[z0\.s\] + *[0-9a-f]+: e4df2000 stnt1h {z0\.s}, p0, \[z0\.s\] *[0-9a-f]+: e49b36b1 stnt1h {z17\.d}, p5, \[z21\.d, x27\] *[0-9a-f]+: e4802000 stnt1h {z0\.d}, p0, \[z0\.d, x0\] - *[0-9a-f]+: e49f2000 stnt1h {z0\.d}, p0, \[z0\.d, xzr\] - *[0-9a-f]+: e49f2000 stnt1h {z0\.d}, p0, \[z0\.d, xzr\] + *[0-9a-f]+: e49f2000 stnt1h {z0\.d}, p0, \[z0\.d\] + *[0-9a-f]+: e49f2000 stnt1h {z0\.d}, p0, \[z0\.d\] *[0-9a-f]+: e55b36b1 stnt1w {z17\.s}, p5, \[z21\.s, x27\] *[0-9a-f]+: e5402000 stnt1w {z0\.s}, p0, \[z0\.s, x0\] - *[0-9a-f]+: e55f2000 stnt1w {z0\.s}, p0, \[z0\.s, xzr\] - *[0-9a-f]+: e55f2000 stnt1w {z0\.s}, p0, \[z0\.s, xzr\] + *[0-9a-f]+: e55f2000 stnt1w {z0\.s}, p0, \[z0\.s\] + *[0-9a-f]+: e55f2000 stnt1w {z0\.s}, p0, \[z0\.s\] *[0-9a-f]+: e51b36b1 stnt1w {z17\.d}, p5, \[z21\.d, x27\] *[0-9a-f]+: e5002000 stnt1w {z0\.d}, p0, \[z0\.d, x0\] - *[0-9a-f]+: e51f2000 stnt1w {z0\.d}, p0, \[z0\.d, xzr\] - *[0-9a-f]+: e51f2000 stnt1w {z0\.d}, p0, \[z0\.d, xzr\] + *[0-9a-f]+: e51f2000 stnt1w {z0\.d}, p0, \[z0\.d\] + *[0-9a-f]+: e51f2000 stnt1w {z0\.d}, p0, \[z0\.d\] *[0-9a-f]+: 457b72b1 subhnb z17\.b, z21\.h, z27\.h *[0-9a-f]+: 45607000 subhnb z0\.b, z0\.h, z0\.h *[0-9a-f]+: 45a07000 subhnb z0\.h, z0\.s, z0\.s diff --git a/gas/testsuite/gas/aarch64/sve2p1-1-bad.l b/gas/testsuite/gas/aarch64/sve2p1-1-bad.l index 90c54fdc901..888504de74e 100644 --- a/gas/testsuite/gas/aarch64/sve2p1-1-bad.l +++ b/gas/testsuite/gas/aarch64/sve2p1-1-bad.l @@ -80,17 +80,3 @@ .*: Error: selected processor does not support `fminqv v4.2d,p3,z2.d' .*: Error: selected processor does not support `fminqv v8.2d,p4,z1.d' .*: Error: selected processor does not support `fminqv v16.4s,p7,z0.s' -.*: Error: selected processor does not support `ld1q Z0.Q,p4/Z,\[Z16.D,x0\]' -.*: Error: selected processor does not support `ld2q {Z0.Q,Z1.Q},p4/Z,\[x0,#-4,MUL VL\]' -.*: Error: selected processor does not support `ld3q .* -.*: Error: selected processor does not support `ld4q .* -.*: Error: selected processor does not support `ld2q {Z0.Q,Z1.Q},p4/Z,\[x0,x2,lsl#4\]' -.*: Error: selected processor does not support `ld3q {Z0.Q,Z1.Q,Z2.Q},p4/Z,\[x0,x4,lsl#4\]' -.*: Error: selected processor does not support `ld4q {Z0.Q,Z1.Q,Z2.Q,Z3.Q},p4/Z,\[x0,x6,lsl#4\]' -.*: Error: selected processor does not support `st1q Z0.Q,p4,\[Z16.D,x0\]' -.*: Error: selected processor does not support `st2q {Z0.Q,Z1.Q},p4,\[x0,#-4,MUL VL\]' -.*: Error: selected processor does not support `st3q .* -.*: Error: selected processor does not support `st4q .* -.*: Error: selected processor does not support `st2q {Z0.Q,Z1.Q},p4,\[x0,x2,lsl#4\]' -.*: Error: selected processor does not support `st3q {Z0.Q,Z1.Q,Z2.Q},p4,\[x0,x4,lsl#4\]' -.*: Error: selected processor does not support `st4q {Z0.Q,Z1.Q,Z2.Q,Z3.Q},p4,\[x0,x6,lsl#4\]' diff --git a/gas/testsuite/gas/aarch64/sve2p1-1.d b/gas/testsuite/gas/aarch64/sve2p1-1.d index 8635d334442..da57edf7e81 100644 --- a/gas/testsuite/gas/aarch64/sve2p1-1.d +++ b/gas/testsuite/gas/aarch64/sve2p1-1.d @@ -89,17 +89,3 @@ .*: 64d7ac44 fminqv v4.2d, p3, z2.d .*: 64d7b028 fminqv v8.2d, p4, z1.d .*: 6497bc10 fminqv v16.4s, p7, z0.s -.*: c400b200 ld1q z0.q, p4/z, \[z16.d, x0\] -.*: a49ef000 ld2q {z0.q, z1.q}, p4/z, \[x0, #-4, mul vl\] -.*: a51ef000 ld3q {z0.q, z1.q, z2.q}, p4/z, \[x0, #-6, mul vl\] -.*: a59ef000 ld4q {z0.q, z1.q, z2.q, z3.q}, p4/z, \[x0, #-8, mul vl\] -.*: a4a29000 ld2q {z0.q, z1.q}, p4/z, \[x0, x2, lsl #4\] -.*: a5249000 ld3q {z0.q, z1.q, z2.q}, p4/z, \[x0, x4, lsl #4\] -.*: a5a69000 ld4q {z0.q, z1.q, z2.q, z3.q}, p4/z, \[x0, x6, lsl #4\] -.*: e4203200 st1q z0.q, p4, \[z16.d, x0\] -.*: e44e1000 st2q {z0.q, z1.q}, p4, \[x0, #-4, mul vl\] -.*: e48e1000 st3q {z0.q, z1.q, z2.q}, p4, \[x0, #-6, mul vl\] -.*: e4ce1000 st4q {z0.q, z1.q, z2.q, z3.q}, p4, \[x0, #-8, mul vl\] -.*: e4621000 st2q {z0.q, z1.q}, p4, \[x0, x2, lsl #4\] -.*: e4a41000 st3q {z0.q, z1.q, z2.q}, p4, \[x0, x4, lsl #4\] -.*: e4e61000 st4q {z0.q, z1.q, z2.q, z3.q}, p4, \[x0, x6, lsl #4\] diff --git a/gas/testsuite/gas/aarch64/sve2p1-1.s b/gas/testsuite/gas/aarch64/sve2p1-1.s index 0e33c603361..718ebccbf75 100644 --- a/gas/testsuite/gas/aarch64/sve2p1-1.s +++ b/gas/testsuite/gas/aarch64/sve2p1-1.s @@ -90,18 +90,3 @@ fminqv v2.4s, p2, z4.s fminqv v4.2d, p3, z2.d fminqv v8.2d, p4, z1.d fminqv v16.4s, p7, z0.s -ld1q Z0.Q, p4/Z, [Z16.D, x0] -ld2q {Z0.Q, Z1.Q}, p4/Z, [x0, #-4, MUL VL] -ld3q {Z0.Q, Z1.Q, Z2.Q}, p4/Z, [x0, #-6, MUL VL] -ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p4/Z, [x0, #-8, MUL VL] -ld2q {Z0.Q, Z1.Q}, p4/Z, [x0, x2, lsl #4] -ld3q {Z0.Q, Z1.Q, Z2.Q}, p4/Z, [x0, x4, lsl #4] -ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p4/Z, [x0, x6, lsl #4] - -st1q Z0.Q, p4, [Z16.D, x0] -st2q {Z0.Q, Z1.Q}, p4, [x0, #-4, MUL VL] -st3q {Z0.Q, Z1.Q, Z2.Q}, p4, [x0, #-6, MUL VL] -st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p4, [x0, #-8, MUL VL] -st2q {Z0.Q, Z1.Q}, p4, [x0, x2, lsl #4] -st3q {Z0.Q, Z1.Q, Z2.Q}, p4, [x0, x4, lsl #4] -st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p4, [x0, x6, lsl #4] diff --git a/gas/testsuite/gas/aarch64/sve2p1-4-invalid.d b/gas/testsuite/gas/aarch64/sve2p1-4-invalid.d new file mode 100644 index 00000000000..2363a12484d --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve2p1-4-invalid.d @@ -0,0 +1,3 @@ +#name: Test of illegal SVE2.1 ld[1-4]q/st[1-4]q instructions. +#as: -march=armv9.4-a +#error_output: sve2p1-4-invalid.l diff --git a/gas/testsuite/gas/aarch64/sve2p1-4-invalid.l b/gas/testsuite/gas/aarch64/sve2p1-4-invalid.l new file mode 100644 index 00000000000..c903664b698 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve2p1-4-invalid.l @@ -0,0 +1,122 @@ +.*: Assembler messages: +.*: Error: p0-p7 expected at operand 2 -- `ld1q {Z0.Q},P8/Z,\[Z0.D,x0\]' +.*: Error: invalid base register at operand 3 -- `ld1q {Z0.Q},P0/Z,\[Z31.Q,x0\]' +.*: Error: invalid addressing mode at operand 3 -- `ld1q {Z0.Q},P0/Z,\[Z0.D,x31\]' +.*: Error: operand mismatch -- `ld1q {Z31.D},P7/Z,\[Z31.D,x30\]' +.*: Info: did you mean this\? +.*: Info: ld1q {z31.q}, p7/z, \[z31.d, x30\] +.*: Error: invalid offset register at operand 3 -- `ld1q Z0.Q,P0/Z,\[Z0.D,sp\]' +.*: Error: operand mismatch -- `ld1q Z0.Q,P0/Z,\[Z0.S,x15\]' +.*: Info: did you mean this\? +.*: Info: ld1q {z0.q}, p0/z, \[z0.d, x15\] +.*: Error: invalid use of 32-bit register offset at operand 3 -- `ld1q Z0.Q,P0/Z,\[Z0.D,w10\]' +.*: Error: the register list must have a stride of 1 at operand 1 -- `ld2q {Z0.Q,Z2.Q},p0/Z,\[x0,#-2,MUL VL\]' +.*: Error: invalid register list at operand 1 -- `ld2q {Z31.Q,Z31.Q},p0/Z,\[x0,#-2,MUL VL\]' +.*: Error: p0-p7 expected at operand 2 -- `ld2q {Z0.Q,Z1.Q},p8/Z,\[x0,#-2,MUL VL\]' +.*: Error: invalid base register at operand 3 -- `ld2q {Z0.Q,Z1.Q},p0/Z,\[x31,#-2,MUL VL\]' +.*: Error: immediate value must be a multiple of 2 at operand 3 -- `ld2q {Z30.Q,Z31.Q},p7/Z,\[x30,#-3,MUL VL\]' +.*: Error: invalid base register at operand 3 -- `ld2q {Z0.Q,Z1.Q},p0/Z,\[x31,#-20,MUL VL\]' +.*: Error: invalid base register at operand 3 -- `ld2q {Z0.Q,Z1.Q},p0/Z,\[xzr,#-20,MUL VL\]' +.*: Error: invalid register list at operand 1 -- `ld3q {Z0.Q,Z1.Q,Z3.Q},p0/Z,\[x0,#-3,MUL VL\]' +.*: Error: operand mismatch -- `ld3q {Z29.Q,Z30.Q,Z31.Q},p8/M,\[x0,#-3,MUL VL\]' +.*: Info: did you mean this\? +.*: Info: ld3q {z29.q-z31.q}, p8/z, \[x0, #-3, mul vl\] +.*: Error: immediate value must be a multiple of 3 at operand 3 -- `ld3q {Z0.Q,Z1.Q,Z2.Q},p7/Z,\[x0,#-2,MUL VL\]' +.*: Error: invalid base register at operand 3 -- `ld3q {Z0.Q,Z1.Q,Z2.Q},p0/Z,\[x31,#-3,MUL VL\]' +.*: Error: type mismatch in vector register list at operand 1 -- `ld3q {Z29.Q,Z30.Q,Z31.D},p7/Z,\[x30,#-3,MUL VL\]' +.*: Error: type mismatch in vector register list at operand 1 -- `ld3q {Z29.Q,Z30.Q,Z31.D},p7/Z,\[x30,#-30,MUL VL\]' +.*: Error: type mismatch in vector register list at operand 1 -- `ld3q {Z29.Q,Z30.Q,Z31.D},p7/Z,\[xzr,#-30,MUL VL\]' +.*: Error: expected a list of 4 registers at operand 1 -- `ld4q {Z0.Q,Z1.Q,Z2.Q},p0/Z,\[x0,#-4,MUL VL\]' +.*: Error: p0-p7 expected at operand 2 -- `ld4q {Z28.Q,Z29.Q,Z30.Q,Z31.Q},p9/Z,\[x0,#-4,MUL VL\]' +.*: Error: immediate value must be a multiple of 4 at operand 3 -- `ld4q {Z0.Q,Z1.Q,Z2.Q,Z3.Q},p7/Z,\[x0,#-3,MUL VL\]' +.*: Error: invalid base register at operand 3 -- `ld4q {Z0.Q,Z1.Q,Z2.Q,Z3.Q},p0/Z,\[x31,#-4,MUL VL\]' +.*: Error: type mismatch in vector register list at operand 1 -- `ld4q {Z28.Q,Z29.Q,Z30.D,Z31.Q},p7/Z,\[x30,#-4,MUL VL\]' +.*: Error: type mismatch in vector register list at operand 1 -- `ld4q {Z28.Q,Z29.Q,Z30.D,Z31.Q},p7/Z,\[x30,#-100,MUL VL\]' +.*: Error: type mismatch in vector register list at operand 1 -- `ld4q {Z28.Q,Z29.Q,Z30.D,Z31.Q},p7/Z,\[xzr,#-100,MUL VL\]' +.*: Error: invalid addressing mode at operand 3 -- `ld2q {Z0.Q,Z1.Q},p0/Z,\[x0,x0,LSL#3\]' +.*: Error: invalid addressing mode at operand 3 -- `ld2q {Z0.Q,Z1.Q},p0/Z,\[sp,x0,LSL#3\]' +.*: Error: invalid offset register at operand 3 -- `ld2q {Z0.Q,Z1.Q},p0/Z,\[x0,sp,LSL#3\]' +.*: Error: invalid register list at operand 1 -- `ld2q {Z31.Q,Z31.Q},p0/Z,\[x0,x0,LSL#4\]' +.*: Error: index register xzr is not allowed at operand 3 -- `ld2q {Z31.Q,Z0.Q},p0/Z,\[x0,xzr,LSL#2\]' +.*: Error: p0-p7 expected at operand 2 -- `ld2q {Z0.Q,Z1.Q},p8/Z,\[x0,x0,LSL#4\]' +.*: Error: invalid base register at operand 3 -- `ld2q {Z0.Q,Z1.Q},p0/Z,\[x31,x0,LSL#4\]' +.*: Error: only 'MUL VL' is permitted at operand 3 -- `ld2q {Z0.Q,Z1.Q},p0/Z,\[x0,x31,LSL#4\]' +.*: Error: invalid base register at operand 3 -- `ld2q {Z30.Q,Z31.Q},p7/Z,\[x31,x31,LSL#4\]' +.*: Error: shift expression expected at operand 3 -- `ld3q {Z0.Q,Z1.Q,Z2.Q},p0/Z,\[x0,x0,#4\]' +.*: Error: shift expression expected at operand 3 -- `ld3q {Z0.Q,Z1.Q,Z2.Q},p0/Z,\[sp,x0,#4\]' +.*: Error: invalid offset register at operand 3 -- `ld3q {Z0.Q,Z1.Q,Z2.Q},p0/Z,\[x0,sp,#4\]' +.*: Error: invalid addressing mode at operand 3 -- `ld3q {Z29.Q,Z30.Q,Z31.Q},p0/Z,\[x0,x0,LSL#2\]' +.*: Error: index register xzr is not allowed at operand 3 -- `ld3q {Z29.Q,Z30.Q,Z31.Q},p0/Z,\[x0,xzr,LSL#3\]' +.*: Error: operand mismatch -- `ld3q {Z0.Q,Z1.Q,Z2.Q},p7/M,\[x0,x0,LSL#4\]' +.*: Info: did you mean this\? +.*: Info: ld3q {z0.q-z2.q}, p7/z, \[x0, x0, lsl #4\] +.*: Error: p0-p7 expected at operand 2 -- `ld3q {Z0.Q,Z1.Q,Z2.Q},p8/Z,\[x30,x0,LSL#4\]' +.*: Error: invalid register list at operand 1 -- `ld3q {Z4.Q,Z1.Q,Z2.Q},p0/Z,\[x31,x30,LSL#4\]' +.*: Error: type mismatch in vector register list at operand 1 -- `ld3q {Z29.D,Z30.Q,Z31.Q},p7/Z,\[x31,x30,LSL#4\]' +.*: Error: invalid register list at operand 1 -- `ld4q {Z1.Q,Z1.Q,Z2.Q,Z3.Q},p0/Z,\[x0,x0,LSL#4\]' +.*: Error: invalid register list at operand 1 -- `ld4q {Z1.Q,Z1.Q,Z2.Q,Z3.Q},p0/Z,\[sp,x0,LSL#4\]' +.*: Error: invalid register list at operand 1 -- `ld4q {Z1.Q,Z1.Q,Z2.Q,Z3.Q},p0/Z,\[x0,sp,LSL#4\]' +.*: Error: invalid register list at operand 1 -- `ld4q {Z30.Q,Z29.Q,Z30.Q,Z31.Q},p8/Z,\[x0,x0,LSL#4\]' +.*: Error: index register xzr is not allowed at operand 3 -- `ld4q {Z28.Q,Z29.Q,Z30.Q,Z31.Q},p7/Z,\[x0,xzr,LSL#4\]' +.*: Error: invalid addressing mode at operand 3 -- `ld4q {Z0.Q,Z1.Q,Z2.Q,Z3.Q},p7/Z,\[x0,x0,LSL#2\]' +.*: Error: invalid base register at operand 3 -- `ld4q {Z0.Q,Z1.Q,Z2.Q,Z3.Q},p0/Z,\[x31,x0,LSL#4\]' +.*: Error: type mismatch in vector register list at operand 1 -- `ld4q {Z0.Q,Z1.Q,Z2.D,Z3.Q},p0/Z,\[x1,x30,LSL#4\]' +.*: Error: invalid register list at operand 1 -- `ld4q {Z2.Q,Z29.Q,Z30.Q,Z31.Q},p7/Z,\[x30,x30,LSL#4\]' +.*: Error: p0-p7 expected at operand 2 -- `st1q {Z0.Q},P8,\[Z0.D,x0\]' +.*: Error: invalid base register at operand 3 -- `st1q {Z0.Q},P0,\[Z31.Q,x0\]' +.*: Error: invalid addressing mode at operand 3 -- `st1q {Z0.Q},P0,\[Z0.D,x31\]' +.*: Error: operand mismatch -- `st1q {Z31.D},P7,\[Z31.D,x30\]' +.*: Info: did you mean this\? +.*: Info: st1q {z31.q}, p7, \[z31.d, x30\] +.*: Error: invalid offset register at operand 3 -- `st1q Z0.Q,P0,\[Z0.D,sp\]' +.*: Error: operand mismatch -- `st1q Z0.Q,P0,\[Z0.S,x15\]' +.*: Info: did you mean this\? +.*: Info: st1q {z0.q}, p0, \[z0.d, x15\] +.*: Error: invalid use of 32-bit register offset at operand 3 -- `st1q Z0.Q,P0,\[Z0.D,w10\]' +.*: Error: the register list must have a stride of 1 at operand 1 -- `st2q {Z0.Q,Z2.Q},p0,\[x0,#-2,MUL VL\]' +.*: Error: invalid register list at operand 1 -- `st2q {Z31.Q,Z31.Q},p0,\[x0,#-2,MUL VL\]' +.*: Error: p0-p7 expected at operand 2 -- `st2q {Z0.Q,Z1.Q},p8,\[x0,#-2,MUL VL\]' +.*: Error: invalid base register at operand 3 -- `st2q {Z0.Q,Z1.Q},p0,\[x31,#-2,MUL VL\]' +.*: Error: immediate value must be a multiple of 2 at operand 3 -- `st2q {Z30.Q,Z31.Q},p7,\[x30,#-3,MUL VL\]' +.*: Error: invalid base register at operand 3 -- `st2q {Z0.Q,Z1.Q},p0,\[x31,#-20,MUL VL\]' +.*: Error: invalid base register at operand 3 -- `st2q {Z0.Q,Z1.Q},p0,\[xzr,#-20,MUL VL\]' +.*: Error: invalid register list at operand 1 -- `st3q {Z0.Q,Z1.Q,Z3.Q},p0,\[x0,#-3,MUL VL\]' +.*: Error: p0-p7 expected at operand 2 -- `st3q {Z29.Q,Z30.Q,Z31.Q},p8,\[x0,#-3,MUL VL\]' +.*: Error: immediate value must be a multiple of 3 at operand 3 -- `st3q {Z0.Q,Z1.Q,Z2.Q},p7,\[x0,#-2,MUL VL\]' +.*: Error: invalid base register at operand 3 -- `st3q {Z0.Q,Z1.Q,Z2.Q},p0,\[x31,#-3,MUL VL\]' +.*: Error: type mismatch in vector register list at operand 1 -- `st3q {Z29.Q,Z30.Q,Z31.D},p7,\[x30,#-3,MUL VL\]' +.*: Error: type mismatch in vector register list at operand 1 -- `st3q {Z29.Q,Z30.Q,Z31.D},p7,\[x30,#-30,MUL VL\]' +.*: Error: type mismatch in vector register list at operand 1 -- `st3q {Z29.Q,Z30.Q,Z31.D},p7,\[xzr,#-30,MUL VL\]' +.*: Error: expected a list of 4 registers at operand 1 -- `st4q {Z0.Q,Z1.Q,Z2.Q},p0,\[x0,#-4,MUL VL\]' +.*: Error: p0-p7 expected at operand 2 -- `st4q {Z28.Q,Z29.Q,Z30.Q,Z31.Q},p9,\[x0,#-4,MUL VL\]' +.*: Error: immediate value must be a multiple of 4 at operand 3 -- `st4q {Z0.Q,Z1.Q,Z2.Q,Z3.Q},p7,\[x0,#-3,MUL VL\]' +.*: Error: invalid base register at operand 3 -- `st4q {Z0.Q,Z1.Q,Z2.Q,Z3.Q},p0,\[x31,#-4,MUL VL\]' +.*: Error: type mismatch in vector register list at operand 1 -- `st4q {Z28.Q,Z29.Q,Z30.D,Z31.Q},p7,\[x30,#-4,MUL VL\]' +.*: Error: type mismatch in vector register list at operand 1 -- `st4q {Z28.Q,Z29.Q,Z30.D,Z31.Q},p7,\[x30,#-100,MUL VL\]' +.*: Error: type mismatch in vector register list at operand 1 -- `st4q {Z28.Q,Z29.Q,Z30.D,Z31.Q},p7,\[xzr,#-100,MUL VL\]' +.*: Error: invalid addressing mode at operand 3 -- `st2q {Z0.Q,Z1.Q},p0,\[x0,x0,LSL#3\]' +.*: Error: invalid addressing mode at operand 3 -- `st2q {Z0.Q,Z1.Q},p0,\[sp,x0,LSL#3\]' +.*: Error: invalid offset register at operand 3 -- `st2q {Z0.Q,Z1.Q},p0,\[x0,sp,LSL#3\]' +.*: Error: invalid register list at operand 1 -- `st2q {Z31.Q,Z31.Q},p0,\[x0,x0,LSL#4\]' +.*: Error: index register xzr is not allowed at operand 3 -- `st2q {Z30.Q,Z31.Q},p0,\[x0,xzr,LSL#2\]' +.*: Error: p0-p7 expected at operand 2 -- `st2q {Z0.Q,Z1.Q},p8,\[x0,x0,LSL#4\]' +.*: Error: invalid base register at operand 3 -- `st2q {Z0.Q,Z1.Q},p0,\[x31,x0,LSL#4\]' +.*: Error: only 'MUL VL' is permitted at operand 3 -- `st2q {Z0.Q,Z1.Q},p0,\[x0,x31,LSL#4\]' +.*: Error: invalid base register at operand 3 -- `st2q {Z30.Q,Z31.Q},p7,\[x31,x31,LSL#4\]' +.*: Error: shift expression expected at operand 3 -- `st3q {Z0.Q,Z1.Q,Z2.Q},p0,\[x0,x0,#4\]' +.*: Error: shift expression expected at operand 3 -- `st3q {Z0.Q,Z1.Q,Z2.Q},p0,\[sp,x0,#4\]' +.*: Error: invalid offset register at operand 3 -- `st3q {Z0.Q,Z1.Q,Z2.Q},p0,\[x0,sp,#4\]' +.*: Error: invalid addressing mode at operand 3 -- `st3q {Z29.Q,Z30.Q,Z31.Q},p0,\[x0,x0,LSL#2\]' +.*: Error: index register xzr is not allowed at operand 3 -- `st3q {Z29.Q,Z30.Q,Z31.Q},p0,\[x0,xzr,LSL#3\]' +.*: Error: p0-p7 expected at operand 2 -- `st3q {Z0.Q,Z1.Q,Z2.Q},p8,\[x30,x0,LSL#4\]' +.*: Error: invalid register list at operand 1 -- `st3q {Z4.Q,Z1.Q,Z2.Q},p0,\[x31,x30,LSL#4\]' +.*: Error: type mismatch in vector register list at operand 1 -- `st3q {Z29.D,Z30.Q,Z31.Q},p7,\[x31,x30,LSL#4\]' +.*: Error: invalid register list at operand 1 -- `st4q {Z1.Q,Z1.Q,Z2.Q,Z3.Q},p0,\[x0,x0,LSL#4\]' +.*: Error: invalid register list at operand 1 -- `st4q {Z1.Q,Z1.Q,Z2.Q,Z3.Q},p0,\[sp,x0,LSL#4\]' +.*: Error: invalid register list at operand 1 -- `st4q {Z1.Q,Z1.Q,Z2.Q,Z3.Q},p0,\[x0,sp,LSL#4\]' +.*: Error: invalid register list at operand 1 -- `st4q {Z30.Q,Z29.Q,Z30.Q,Z31.Q},p8,\[x0,x0,LSL#4\]' +.*: Error: index register xzr is not allowed at operand 3 -- `st4q {Z28.Q,Z29.Q,Z30.Q,Z31.Q},p7,\[x0,xzr,LSL#4\]' +.*: Error: invalid addressing mode at operand 3 -- `st4q {Z0.Q,Z1.Q,Z2.Q,Z3.Q},p7,\[x0,x0,LSL#2\]' +.*: Error: invalid base register at operand 3 -- `st4q {Z0.Q,Z1.Q,Z2.Q,Z3.Q},p0,\[x31,x0,LSL#4\]' +.*: Error: type mismatch in vector register list at operand 1 -- `st4q {Z0.Q,Z1.Q,Z2.D,Z3.Q},p0,\[x1,x30,LSL#4\]' +.*: Error: invalid register list at operand 1 -- `st4q {Z2.Q,Z29.Q,Z30.Q,Z31.Q},p7,\[x30,x30,LSL#4\]' diff --git a/gas/testsuite/gas/aarch64/sve2p1-4-invalid.s b/gas/testsuite/gas/aarch64/sve2p1-4-invalid.s new file mode 100644 index 00000000000..789209f2eda --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve2p1-4-invalid.s @@ -0,0 +1,125 @@ +ld1q Z0.Q , P0/Z, [Z0.D, x0] +ld1q { Z0.Q }, P8/Z, [Z0.D, x0] +ld1q { Z0.Q }, P0/Z, [Z31.Q, x0] +ld1q { Z0.Q }, P0/Z, [Z0.D, x31] +ld1q { Z31.D }, P7/Z, [Z31.D, x30] +ld1q Z0.Q , P0/Z, [Z0.D, sp] +ld1q Z0.Q , P0/Z, [Z0.S, x15] +ld1q Z0.Q , P0/Z, [Z0.D, w10] + +ld2q {Z0.Q, Z2.Q}, p0/Z, [x0, #-2, MUL VL] +ld2q {Z31.Q, Z31.Q}, p0/Z, [x0, #-2, MUL VL] +ld2q {Z0.Q, Z1.Q}, p8/Z, [x0, #-2, MUL VL] +ld2q {Z0.Q, Z1.Q}, p0/Z, [x31, #-2, MUL VL] +ld2q {Z30.Q, Z31.Q}, p7/Z, [x30, #-3, MUL VL] +ld2q {Z0.Q, Z1.Q}, p0/Z, [x31, #-20, MUL VL] +ld2q {Z0.Q, Z1.Q}, p0/Z, [xzr, #-20, MUL VL] + +ld3q {Z0.Q, Z1.Q, Z3.Q}, p0/Z, [x0, #-3, MUL VL] +ld3q {Z29.Q, Z30.Q, Z31.Q}, p8/M, [x0, #-3, MUL VL] +ld3q {Z0.Q, Z1.Q, Z2.Q}, p7/Z, [x0, #-2, MUL VL] +ld3q {Z0.Q, Z1.Q, Z2.Q}, p0/Z, [x31, #-3, MUL VL] +ld3q {Z29.Q, Z30.Q, Z31.D}, p7/Z, [x30, #-3, MUL VL] +ld3q {Z29.Q, Z30.Q, Z31.D}, p7/Z, [x30, #-30, MUL VL] +ld3q {Z29.Q, Z30.Q, Z31.D}, p7/Z, [xzr, #-30, MUL VL] + +ld4q {Z0.Q, Z1.Q, Z2.Q}, p0/Z, [x0, #-4, MUL VL] +ld4q {Z28.Q, Z29.Q, Z30.Q,Z31.Q}, p9/Z, [x0, #-4, MUL VL] +ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p7/Z, [x0, #-3, MUL VL] +ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0/Z, [x31, #-4, MUL VL] +ld4q {Z28.Q, Z29.Q, Z30.D, Z31.Q}, p7/Z, [x30, #-4, MUL VL] +ld4q {Z28.Q, Z29.Q, Z30.D, Z31.Q}, p7/Z, [x30, #-100, MUL VL] +ld4q {Z28.Q, Z29.Q, Z30.D, Z31.Q}, p7/Z, [xzr, #-100, MUL VL] + +ld2q {Z0.Q, Z1.Q}, p0/Z, [x0, x0, LSL #3] +ld2q {Z0.Q, Z1.Q}, p0/Z, [sp, x0, LSL #3] +ld2q {Z0.Q, Z1.Q}, p0/Z, [x0, sp, LSL #3] +ld2q {Z31.Q, Z31.Q}, p0/Z, [x0, x0, LSL #4] +ld2q {Z31.Q, Z0.Q}, p0/Z, [x0, xzr, LSL #2] +ld2q {Z0.Q, Z1.Q}, p8/Z, [x0, x0, LSL #4] +ld2q {Z0.Q, Z1.Q}, p0/Z, [x31, x0, LSL #4] +ld2q {Z0.Q, Z1.Q}, p0/Z, [x0, x31, LSL #4] +ld2q {Z30.Q, Z31.Q}, p7/Z, [x31, x31, LSL #4] + +ld3q {Z0.Q, Z1.Q, Z2.Q}, p0/Z, [x0, x0, #4] +ld3q {Z0.Q, Z1.Q, Z2.Q}, p0/Z, [sp, x0, #4] +ld3q {Z0.Q, Z1.Q, Z2.Q}, p0/Z, [x0, sp, #4] +ld3q {Z29.Q, Z30.Q, Z31.Q}, p0/Z, [x0, x0, LSL #2] +ld3q {Z29.Q, Z30.Q, Z31.Q}, p0/Z, [x0, xzr, LSL #3] +ld3q {Z0.Q, Z1.Q, Z2.Q}, p7/M, [x0, x0, LSL #4] +ld3q {Z0.Q, Z1.Q, Z2.Q}, p8/Z, [x30, x0, LSL #4] +ld3q {Z4.Q, Z1.Q, Z2.Q}, p0/Z, [x31, x30, LSL #4] +ld3q {Z29.D, Z30.Q, Z31.Q}, p7/Z, [x31, x30, LSL #4] + +ld4q {Z1.Q, Z1.Q, Z2.Q, Z3.Q}, p0/Z, [x0, x0, LSL #4] +ld4q {Z1.Q, Z1.Q, Z2.Q, Z3.Q}, p0/Z, [sp, x0, LSL #4] +ld4q {Z1.Q, Z1.Q, Z2.Q, Z3.Q}, p0/Z, [x0, sp, LSL #4] +ld4q {Z30.Q, Z29.Q, Z30.Q,Z31.Q}, p8/Z, [x0, x0, LSL #4] +ld4q {Z28.Q, Z29.Q, Z30.Q,Z31.Q}, p7/Z, [x0, xzr, LSL #4] +ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p7/Z, [x0, x0, LSL #2] +ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0/Z, [x31, x0, LSL #4] +ld4q {Z0.Q, Z1.Q, Z2.D, Z3.Q}, p0/Z, [x1, x30, LSL #4] +ld4q {Z2.Q, Z29.Q, Z30.Q, Z31.Q}, p7/Z, [x30, x30, LSL #4] + +st1q Z0.Q , P0, [Z0.D, x0] +st1q { Z0.Q }, P8, [Z0.D, x0] +st1q { Z0.Q }, P0, [Z31.Q, x0] +st1q { Z0.Q }, P0, [Z0.D, x31] +st1q { Z31.D }, P7, [Z31.D, x30] +st1q Z0.Q , P0, [Z0.D, sp] +st1q Z0.Q , P0, [Z0.S, x15] +st1q Z0.Q , P0, [Z0.D, w10] + +st2q {Z0.Q, Z2.Q}, p0, [x0, #-2, MUL VL] +st2q {Z31.Q, Z31.Q}, p0, [x0, #-2, MUL VL] +st2q {Z0.Q, Z1.Q}, p8, [x0, #-2, MUL VL] +st2q {Z0.Q, Z1.Q}, p0, [x31, #-2, MUL VL] +st2q {Z30.Q, Z31.Q}, p7, [x30, #-3, MUL VL] +st2q {Z0.Q, Z1.Q}, p0, [x31, #-20, MUL VL] +st2q {Z0.Q, Z1.Q}, p0, [xzr, #-20, MUL VL] + +st3q {Z0.Q, Z1.Q, Z3.Q}, p0, [x0, #-3, MUL VL] +st3q {Z29.Q, Z30.Q, Z31.Q}, p8, [x0, #-3, MUL VL] +st3q {Z0.Q, Z1.Q, Z2.Q}, p7, [x0, #-2, MUL VL] +st3q {Z0.Q, Z1.Q, Z2.Q}, p0, [x31, #-3, MUL VL] +st3q {Z29.Q, Z30.Q, Z31.D}, p7, [x30, #-3, MUL VL] +st3q {Z29.Q, Z30.Q, Z31.D}, p7, [x30, #-30, MUL VL] +st3q {Z29.Q, Z30.Q, Z31.D}, p7, [xzr, #-30, MUL VL] + +st4q {Z0.Q, Z1.Q, Z2.Q}, p0, [x0, #-4, MUL VL] +st4q {Z28.Q, Z29.Q, Z30.Q,Z31.Q}, p9, [x0, #-4, MUL VL] +st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p7, [x0, #-3, MUL VL] +st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0, [x31, #-4, MUL VL] +st4q {Z28.Q, Z29.Q, Z30.D, Z31.Q}, p7, [x30, #-4, MUL VL] +st4q {Z28.Q, Z29.Q, Z30.D, Z31.Q}, p7, [x30, #-100, MUL VL] +st4q {Z28.Q, Z29.Q, Z30.D, Z31.Q}, p7, [xzr, #-100, MUL VL] + +st2q {Z0.Q, Z1.Q}, p0, [x0, x0, LSL #3] +st2q {Z0.Q, Z1.Q}, p0, [sp, x0, LSL #3] +st2q {Z0.Q, Z1.Q}, p0, [x0, sp, LSL #3] +st2q {Z31.Q, Z31.Q}, p0, [x0, x0, LSL #4] +st2q {Z30.Q, Z31.Q}, p0, [x0, xzr, LSL #2] +st2q {Z0.Q, Z1.Q}, p8, [x0, x0, LSL #4] +st2q {Z0.Q, Z1.Q}, p0, [x31, x0, LSL #4] +st2q {Z0.Q, Z1.Q}, p0, [x0, x31, LSL #4] +st2q {Z30.Q, Z31.Q}, p7, [x31, x31, LSL #4] + +st3q {Z0.Q, Z1.Q, Z2.Q}, p0, [x0, x0, #4] +st3q {Z0.Q, Z1.Q, Z2.Q}, p0, [sp, x0, #4] +st3q {Z0.Q, Z1.Q, Z2.Q}, p0, [x0, sp, #4] +st3q {Z29.Q, Z30.Q, Z31.Q}, p0, [x0, x0, LSL #2] +st3q {Z29.Q, Z30.Q, Z31.Q}, p0, [x0, xzr, LSL #3] +st3q {Z0.Q, Z1.Q, Z2.Q}, p7, [x0, x0, LSL #4] +st3q {Z0.Q, Z1.Q, Z2.Q}, p8, [x30, x0, LSL #4] +st3q {Z4.Q, Z1.Q, Z2.Q}, p0, [x31, x30, LSL #4] +st3q {Z29.D, Z30.Q, Z31.Q}, p7, [x31, x30, LSL #4] + +st4q {Z1.Q, Z1.Q, Z2.Q, Z3.Q}, p0, [x0, x0, LSL #4] +st4q {Z1.Q, Z1.Q, Z2.Q, Z3.Q}, p0, [sp, x0, LSL #4] +st4q {Z1.Q, Z1.Q, Z2.Q, Z3.Q}, p0, [x0, sp, LSL #4] +st4q {Z30.Q, Z29.Q, Z30.Q,Z31.Q}, p8, [x0, x0, LSL #4] +st4q {Z28.Q, Z29.Q, Z30.Q,Z31.Q}, p7, [x0, xzr, LSL #4] +st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p7, [x0, x0, LSL #2] +st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0, [x31, x0, LSL #4] +st4q {Z0.Q, Z1.Q, Z2.D, Z3.Q}, p0, [x1, x30, LSL #4] +st4q {Z2.Q, Z29.Q, Z30.Q, Z31.Q}, p7, [x30, x30, LSL #4] diff --git a/gas/testsuite/gas/aarch64/sve2p1-4.d b/gas/testsuite/gas/aarch64/sve2p1-4.d new file mode 100644 index 00000000000..390c63d8acf --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve2p1-4.d @@ -0,0 +1,152 @@ +#name: Test of SVE2.1 ld[1-4]q/st[1-4]q instructions. +#as: -march=armv9.4-a +#objdump: -dr + +[^:]+: file format .* + + +[^:]+: + +[^:]+: +.*: c400a000 ld1q {z0.q}, p0/z, \[z0.d, x0\] +.*: c400a01f ld1q {z31.q}, p0/z, \[z0.d, x0\] +.*: c400bc00 ld1q {z0.q}, p7/z, \[z0.d, x0\] +.*: c400a3e0 ld1q {z0.q}, p0/z, \[z31.d, x0\] +.*: c41ea000 ld1q {z0.q}, p0/z, \[z0.d, x30\] +.*: c41fa000 ld1q {z0.q}, p0/z, \[z0.d\] +.*: c41fa000 ld1q {z0.q}, p0/z, \[z0.d\] +.*: c41ebfff ld1q {z31.q}, p7/z, \[z31.d, x30\] +.*: c404acef ld1q {z15.q}, p3/z, \[z7.d, x4\] +.*: a490e000 ld2q {z0.q-z1.q}, p0/z, \[x0\] +.*: a490e01f ld2q {z31.q-z0.q}, p0/z, \[x0\] +.*: a490fc00 ld2q {z0.q-z1.q}, p7/z, \[x0\] +.*: a490e3c0 ld2q {z0.q-z1.q}, p0/z, \[x30\] +.*: a490e3c0 ld2q {z0.q-z1.q}, p0/z, \[x30\] +.*: a498e000 ld2q {z0.q-z1.q}, p0/z, \[x0, #-16, mul vl\] +.*: a497e000 ld2q {z0.q-z1.q}, p0/z, \[x0, #14, mul vl\] +.*: a498ffdf ld2q {z31.q-z0.q}, p7/z, \[x30, #-16, mul vl\] +.*: a49be7e1 ld2q {z1.q-z2.q}, p1/z, \[sp, #-10, mul vl\] +.*: a49fe47e ld2q {z30.q-z31.q}, p1/z, \[x3, #-2, mul vl\] +.*: a510e000 ld3q {z0.q-z2.q}, p0/z, \[x0\] +.*: a510e01f ld3q {z31.q-z1.q}, p0/z, \[x0\] +.*: a510fc00 ld3q {z0.q-z2.q}, p7/z, \[x0\] +.*: a510e3c0 ld3q {z0.q-z2.q}, p0/z, \[x30\] +.*: a510e3c0 ld3q {z0.q-z2.q}, p0/z, \[x30\] +.*: a518e000 ld3q {z0.q-z2.q}, p0/z, \[x0, #-24, mul vl\] +.*: a517e000 ld3q {z0.q-z2.q}, p0/z, \[x0, #21, mul vl\] +.*: a518ffdf ld3q {z31.q-z1.q}, p7/z, \[x30, #-24, mul vl\] +.*: a51fffdd ld3q {z29.q-z31.q}, p7/z, \[x30, #-3, mul vl\] +.*: a51fffdd ld3q {z29.q-z31.q}, p7/z, \[x30, #-3, mul vl\] +.*: a51ce7e1 ld3q {z1.q-z3.q}, p1/z, \[sp, #-12, mul vl\] +.*: a51fffdd ld3q {z29.q-z31.q}, p7/z, \[x30, #-3, mul vl\] +.*: a590e000 ld4q {z0.q-z3.q}, p0/z, \[x0\] +.*: a590e01f ld4q {z31.q-z2.q}, p0/z, \[x0\] +.*: a590fc00 ld4q {z0.q-z3.q}, p7/z, \[x0\] +.*: a590e3c0 ld4q {z0.q-z3.q}, p0/z, \[x30\] +.*: a590e3c0 ld4q {z0.q-z3.q}, p0/z, \[x30\] +.*: a598e000 ld4q {z0.q-z3.q}, p0/z, \[x0, #-32, mul vl\] +.*: a597e000 ld4q {z0.q-z3.q}, p0/z, \[x0, #28, mul vl\] +.*: a598ffdf ld4q {z31.q-z2.q}, p7/z, \[x30, #-32, mul vl\] +.*: a59fffdc ld4q {z28.q-z31.q}, p7/z, \[x30, #-4, mul vl\] +.*: a59fffdc ld4q {z28.q-z31.q}, p7/z, \[x30, #-4, mul vl\] +.*: a59cf3e1 ld4q {z1.q-z4.q}, p4/z, \[sp, #-16, mul vl\] +.*: a59fffdc ld4q {z28.q-z31.q}, p7/z, \[x30, #-4, mul vl\] +.*: a4a08000 ld2q {z0.q-z1.q}, p0/z, \[x0, x0, lsl #4\] +.*: a4a0801f ld2q {z31.q-z0.q}, p0/z, \[x0, x0, lsl #4\] +.*: a4a09c00 ld2q {z0.q-z1.q}, p7/z, \[x0, x0, lsl #4\] +.*: a4a083c0 ld2q {z0.q-z1.q}, p0/z, \[x30, x0, lsl #4\] +.*: a4bd8000 ld2q {z0.q-z1.q}, p0/z, \[x0, x29, lsl #4\] +.*: a4bd9fdf ld2q {z31.q-z0.q}, p7/z, \[x30, x29, lsl #4\] +.*: a4b4914f ld2q {z15.q-z16.q}, p4/z, \[x10, x20, lsl #4\] +.*: a4b48ff4 ld2q {z20.q-z21.q}, p3/z, \[sp, x20, lsl #4\] +.*: a5208000 ld3q {z0.q-z2.q}, p0/z, \[x0, x0, lsl #4\] +.*: a520801f ld3q {z31.q-z1.q}, p0/z, \[x0, x0, lsl #4\] +.*: a5209c00 ld3q {z0.q-z2.q}, p7/z, \[x0, x0, lsl #4\] +.*: a52083c0 ld3q {z0.q-z2.q}, p0/z, \[x30, x0, lsl #4\] +.*: a53d8000 ld3q {z0.q-z2.q}, p0/z, \[x0, x29, lsl #4\] +.*: a53d9fdf ld3q {z31.q-z1.q}, p7/z, \[x30, x29, lsl #4\] +.*: a534894a ld3q {z10.q-z12.q}, p2/z, \[x10, x20, lsl #4\] +.*: a534894a ld3q {z10.q-z12.q}, p2/z, \[x10, x20, lsl #4\] +.*: a534894a ld3q {z10.q-z12.q}, p2/z, \[x10, x20, lsl #4\] +.*: a53497ef ld3q {z15.q-z17.q}, p5/z, \[sp, x20, lsl #4\] +.*: a5a08000 ld4q {z0.q-z3.q}, p0/z, \[x0, x0, lsl #4\] +.*: a5a0801f ld4q {z31.q-z2.q}, p0/z, \[x0, x0, lsl #4\] +.*: a5a09c00 ld4q {z0.q-z3.q}, p7/z, \[x0, x0, lsl #4\] +.*: a5a083c0 ld4q {z0.q-z3.q}, p0/z, \[x30, x0, lsl #4\] +.*: a5bd8000 ld4q {z0.q-z3.q}, p0/z, \[x0, x29, lsl #4\] +.*: a5bd9fdf ld4q {z31.q-z2.q}, p7/z, \[x30, x29, lsl #4\] +.*: a5a4886a ld4q {z10.q-z13.q}, p2/z, \[x3, x4, lsl #4\] +.*: a5a4886a ld4q {z10.q-z13.q}, p2/z, \[x3, x4, lsl #4\] +.*: a5a4886a ld4q {z10.q-z13.q}, p2/z, \[x3, x4, lsl #4\] +.*: a5a48bea ld4q {z10.q-z13.q}, p2/z, \[sp, x4, lsl #4\] +.*: e4202000 st1q {z0.q}, p0, \[z0.d, x0\] +.*: e420201f st1q {z31.q}, p0, \[z0.d, x0\] +.*: e4203c00 st1q {z0.q}, p7, \[z0.d, x0\] +.*: e42023e0 st1q {z0.q}, p0, \[z31.d, x0\] +.*: e43e2000 st1q {z0.q}, p0, \[z0.d, x30\] +.*: e43f2000 st1q {z0.q}, p0, \[z0.d\] +.*: e43f2000 st1q {z0.q}, p0, \[z0.d\] +.*: e43e3fff st1q {z31.q}, p7, \[z31.d, x30\] +.*: e4242cef st1q {z15.q}, p3, \[z7.d, x4\] +.*: e4400000 st2q {z0.q-z1.q}, p0, \[x0\] +.*: e440001f st2q {z31.q-z0.q}, p0, \[x0\] +.*: e4401c00 st2q {z0.q-z1.q}, p7, \[x0\] +.*: e44003c0 st2q {z0.q-z1.q}, p0, \[x30\] +.*: e44003c0 st2q {z0.q-z1.q}, p0, \[x30\] +.*: e4480000 st2q {z0.q-z1.q}, p0, \[x0, #-16, mul vl\] +.*: e4470000 st2q {z0.q-z1.q}, p0, \[x0, #14, mul vl\] +.*: e4481fdf st2q {z31.q-z0.q}, p7, \[x30, #-16, mul vl\] +.*: e44b07e1 st2q {z1.q-z2.q}, p1, \[sp, #-10, mul vl\] +.*: e44f047e st2q {z30.q-z31.q}, p1, \[x3, #-2, mul vl\] +.*: e4800000 st3q {z0.q-z2.q}, p0, \[x0\] +.*: e480001f st3q {z31.q-z1.q}, p0, \[x0\] +.*: e4801c00 st3q {z0.q-z2.q}, p7, \[x0\] +.*: e48003c0 st3q {z0.q-z2.q}, p0, \[x30\] +.*: e48003c0 st3q {z0.q-z2.q}, p0, \[x30\] +.*: e4880000 st3q {z0.q-z2.q}, p0, \[x0, #-24, mul vl\] +.*: e4870000 st3q {z0.q-z2.q}, p0, \[x0, #21, mul vl\] +.*: e4881fdf st3q {z31.q-z1.q}, p7, \[x30, #-24, mul vl\] +.*: e48f1fdd st3q {z29.q-z31.q}, p7, \[x30, #-3, mul vl\] +.*: e48f1fdd st3q {z29.q-z31.q}, p7, \[x30, #-3, mul vl\] +.*: e48c07e1 st3q {z1.q-z3.q}, p1, \[sp, #-12, mul vl\] +.*: e48f1fdd st3q {z29.q-z31.q}, p7, \[x30, #-3, mul vl\] +.*: e4c00000 st4q {z0.q-z3.q}, p0, \[x0\] +.*: e4c0001f st4q {z31.q-z2.q}, p0, \[x0\] +.*: e4c01c00 st4q {z0.q-z3.q}, p7, \[x0\] +.*: e4c003c0 st4q {z0.q-z3.q}, p0, \[x30\] +.*: e4c003c0 st4q {z0.q-z3.q}, p0, \[x30\] +.*: e4c80000 st4q {z0.q-z3.q}, p0, \[x0, #-32, mul vl\] +.*: e4c70000 st4q {z0.q-z3.q}, p0, \[x0, #28, mul vl\] +.*: e4c81fdf st4q {z31.q-z2.q}, p7, \[x30, #-32, mul vl\] +.*: e4cf1fdc st4q {z28.q-z31.q}, p7, \[x30, #-4, mul vl\] +.*: e4cf1fdc st4q {z28.q-z31.q}, p7, \[x30, #-4, mul vl\] +.*: e4cc13e1 st4q {z1.q-z4.q}, p4, \[sp, #-16, mul vl\] +.*: e4cf1fdc st4q {z28.q-z31.q}, p7, \[x30, #-4, mul vl\] +.*: e4600000 st2q {z0.q-z1.q}, p0, \[x0, x0, lsl #4\] +.*: e460001f st2q {z31.q-z0.q}, p0, \[x0, x0, lsl #4\] +.*: e4601c00 st2q {z0.q-z1.q}, p7, \[x0, x0, lsl #4\] +.*: e46003c0 st2q {z0.q-z1.q}, p0, \[x30, x0, lsl #4\] +.*: e47d0000 st2q {z0.q-z1.q}, p0, \[x0, x29, lsl #4\] +.*: e47d1fdf st2q {z31.q-z0.q}, p7, \[x30, x29, lsl #4\] +.*: e474114f st2q {z15.q-z16.q}, p4, \[x10, x20, lsl #4\] +.*: e4740ff4 st2q {z20.q-z21.q}, p3, \[sp, x20, lsl #4\] +.*: e4a00000 st3q {z0.q-z2.q}, p0, \[x0, x0, lsl #4\] +.*: e4a0001f st3q {z31.q-z1.q}, p0, \[x0, x0, lsl #4\] +.*: e4a01c00 st3q {z0.q-z2.q}, p7, \[x0, x0, lsl #4\] +.*: e4a003c0 st3q {z0.q-z2.q}, p0, \[x30, x0, lsl #4\] +.*: e4bd0000 st3q {z0.q-z2.q}, p0, \[x0, x29, lsl #4\] +.*: e4bd1fdf st3q {z31.q-z1.q}, p7, \[x30, x29, lsl #4\] +.*: e4b4094a st3q {z10.q-z12.q}, p2, \[x10, x20, lsl #4\] +.*: e4b4094a st3q {z10.q-z12.q}, p2, \[x10, x20, lsl #4\] +.*: e4b4094a st3q {z10.q-z12.q}, p2, \[x10, x20, lsl #4\] +.*: e4b417ef st3q {z15.q-z17.q}, p5, \[sp, x20, lsl #4\] +.*: e4e00000 st4q {z0.q-z3.q}, p0, \[x0, x0, lsl #4\] +.*: e4e0001f st4q {z31.q-z2.q}, p0, \[x0, x0, lsl #4\] +.*: e4e01c00 st4q {z0.q-z3.q}, p7, \[x0, x0, lsl #4\] +.*: e4e003c0 st4q {z0.q-z3.q}, p0, \[x30, x0, lsl #4\] +.*: e4fd0000 st4q {z0.q-z3.q}, p0, \[x0, x29, lsl #4\] +.*: e4fd1fdf st4q {z31.q-z2.q}, p7, \[x30, x29, lsl #4\] +.*: e4e4086a st4q {z10.q-z13.q}, p2, \[x3, x4, lsl #4\] +.*: e4e4086a st4q {z10.q-z13.q}, p2, \[x3, x4, lsl #4\] +.*: e4e4086a st4q {z10.q-z13.q}, p2, \[x3, x4, lsl #4\] +.*: e4e40bea st4q {z10.q-z13.q}, p2, \[sp, x4, lsl #4\] diff --git a/gas/testsuite/gas/aarch64/sve2p1-4.s b/gas/testsuite/gas/aarch64/sve2p1-4.s new file mode 100644 index 00000000000..70d5044bcaa --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve2p1-4.s @@ -0,0 +1,155 @@ +ld1q { Z0.Q }, P0/Z, [Z0.D, x0] +ld1q { Z31.Q }, P0/Z, [Z0.D, x0] +ld1q { Z0.Q }, P7/Z, [Z0.D, x0] +ld1q { Z0.Q }, P0/Z, [Z31.D, x0] +ld1q { Z0.Q }, P0/Z, [Z0.D, x30] +ld1q { Z0.Q }, P0/Z, [Z0.D, xzr] +ld1q { Z0.Q }, P0/Z, [Z0.D] +ld1q { Z31.Q }, P7/Z, [Z31.D, x30] +ld1q { Z15.Q }, P3/Z, [Z7.D, x4] + +ld2q {Z0.Q, Z1.Q}, p0/Z, [x0, #0, MUL VL] +ld2q {Z31.Q, Z0.Q}, p0/Z, [x0, #0, MUL VL] +ld2q {Z0.Q, Z1.Q}, p7/Z, [x0, #0, MUL VL] +ld2q {Z0.Q, Z1.Q}, p0/Z, [x30, #0, MUL VL] +ld2q {Z0.Q, Z1.Q}, p0/Z, [x30] +ld2q {Z0.Q, Z1.Q}, p0/Z, [x0, #-16, MUL VL] +ld2q {Z0.Q, Z1.Q}, p0/Z, [x0, #14, MUL VL] +ld2q {Z31.Q, Z0.Q}, p7/Z, [x30, #-16, MUL VL] +ld2q {Z1.Q, Z2.Q}, p1/Z, [sp, #-10, MUL VL] +ld2q {Z30.Q, Z31.Q}, p1/Z, [x3, #-2, MUL VL] + +ld3q {Z0.Q, Z1.Q, Z2.Q}, p0/Z, [x0, #0, MUL VL] +ld3q {Z31.Q, Z0.Q, Z1.Q}, p0/Z, [x0, #0, MUL VL] +ld3q {Z0.Q, Z1.Q, Z2.Q}, p7/Z, [x0, #0, MUL VL] +ld3q {Z0.Q, Z1.Q, Z2.Q}, p0/Z, [x30, #0, MUL VL] +ld3q {Z0.Q, Z1.Q, Z2.Q}, p0/Z, [x30] +ld3q {Z0.Q, Z1.Q, Z2.Q}, p0/Z, [x0, #-24, MUL VL] +ld3q {Z0.Q, Z1.Q, Z2.Q}, p0/Z, [x0, #21, MUL VL] +ld3q {Z31.Q, Z0.Q, Z1.Q}, p7/Z, [x30, #-24, MUL VL] +ld3q {Z29.Q, Z30.Q, Z31.Q}, p7/Z, [x30, #-3, MUL VL] +ld3q {Z29.Q - Z30.Q - Z31.Q}, p7/Z, [x30, #-3, MUL VL] +ld3q {Z1.Q, Z2.Q, z3.Q}, p1/Z, [sp, #-12, MUL VL] +ld3q {Z29.Q - Z31.Q}, p7/Z, [x30, #-3, MUL VL] + +ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0/Z, [x0, #0, MUL VL] +ld4q {Z31.Q, Z0.Q, Z1.Q, Z2.Q}, p0/Z, [x0, #0, MUL VL] +ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p7/Z, [x0, #0, MUL VL] +ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0/Z, [x30, #0, MUL VL] +ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0/Z, [x30] +ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0/Z, [x0, #-32, MUL VL] +ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0/Z, [x0, #28, MUL VL] +ld4q {Z31.Q, Z0.Q, Z1.Q, Z2.Q}, p7/Z, [x30, #-32, MUL VL] +ld4q {Z28.Q, Z29.Q, Z30.Q, Z31.Q}, p7/Z, [x30, #-4, MUL VL] +ld4q {Z28.Q - Z29.Q - Z30.Q - Z31.Q}, p7/Z, [x30, #-4, MUL VL] +ld4q {Z1.Q, Z2.Q, z3.Q, Z4.Q}, p4/Z, [sp, #-16, MUL VL] +ld4q {Z28.Q - Z31.Q}, p7/Z, [x30, #-4, MUL VL] + +ld2q {Z0.Q, Z1.Q}, p0/Z, [x0, x0, LSL #4] +ld2q {Z31.Q, Z0.Q}, p0/Z, [x0, x0, LSL #4] +ld2q {Z0.Q, Z1.Q}, p7/Z, [x0, x0, LSL #4] +ld2q {Z0.Q, Z1.Q}, p0/Z, [x30, x0, LSL #4] +ld2q {Z0.Q, Z1.Q}, p0/Z, [x0, x29, LSL #4] +ld2q {Z31.Q, Z0.Q}, p7/Z, [x30, x29, LSL #4] +ld2q {Z15.Q, Z16.Q}, p4/Z, [x10, x20, LSL #4] +ld2q {Z20.Q, Z21.Q}, p3/Z, [sp, x20, LSL #4] + +ld3q {Z0.Q, Z1.Q, Z2.Q}, p0/Z, [x0, x0, LSL #4] +ld3q {Z31.Q, Z0.Q, Z1.Q}, p0/Z, [x0, x0, LSL #4] +ld3q {Z0.Q, Z1.Q, Z2.Q}, p7/Z, [x0, x0, LSL #4] +ld3q {Z0.Q, Z1.Q, Z2.Q}, p0/Z, [x30, x0, LSL #4] +ld3q {Z0.Q, Z1.Q, Z2.Q}, p0/Z, [x0, x29, LSL #4] +ld3q {Z31.Q, Z0.Q, Z1.Q}, p7/Z, [x30, x29, LSL #4] +ld3q {Z10.Q, Z11.Q, Z12.Q}, p2/Z, [x10, x20, LSL #4] +ld3q {Z10.Q - Z11.Q - Z12.Q}, p2/Z, [x10, x20, LSL #4] +ld3q {Z10.Q - Z12.Q}, p2/Z, [x10, x20, LSL #4] +ld3q {Z15.Q - Z17.Q}, p5/Z, [sp, x20, LSL #4] + +ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0/Z, [x0, x0, LSL #4] +ld4q {Z31.Q, Z0.Q, Z1.Q, Z2.Q}, p0/Z, [x0, x0, LSL #4] +ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p7/Z, [x0, x0, LSL #4] +ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0/Z, [x30, x0, LSL #4] +ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0/Z, [x0, x29, LSL #4] +ld4q {Z31.Q, Z0.Q, Z1.Q, Z2.Q}, p7/Z, [x30, x29, LSL #4] +ld4q {Z10.Q, Z11.Q, Z12.Q, Z13.Q}, p2/Z, [x3, x4, LSL #4] +ld4q {Z10.Q - Z11.Q - Z12.Q - Z13.Q}, p2/Z, [x3, x4, LSL #4] +ld4q {Z10.Q - Z13.Q}, p2/Z, [x3, x4, LSL #4] +ld4q {Z10.Q, Z11.Q, Z12.Q, Z13.Q}, p2/Z, [sp, x4, LSL #4] + +st1q { Z0.Q }, P0, [Z0.D, x0] +st1q { Z31.Q }, P0, [Z0.D, x0] +st1q { Z0.Q }, P7, [Z0.D, x0] +st1q { Z0.Q }, P0, [Z31.D, x0] +st1q { Z0.Q }, P0, [Z0.D, x30] +st1q { Z0.Q }, P0, [Z0.D, xzr] +st1q { Z0.Q }, P0, [Z0.D] +st1q { Z31.Q }, P7, [Z31.D, x30] +st1q { Z15.Q }, P3, [Z7.D, x4] + +st2q {Z0.Q, Z1.Q}, p0, [x0, #0, MUL VL] +st2q {Z31.Q, Z0.Q}, p0, [x0, #0, MUL VL] +st2q {Z0.Q, Z1.Q}, p7, [x0, #0, MUL VL] +st2q {Z0.Q, Z1.Q}, p0, [x30, #0, MUL VL] +st2q {Z0.Q, Z1.Q}, p0, [x30] +st2q {Z0.Q, Z1.Q}, p0, [x0, #-16, MUL VL] +st2q {Z0.Q, Z1.Q}, p0, [x0, #14, MUL VL] +st2q {Z31.Q, Z0.Q}, p7, [x30, #-16, MUL VL] +st2q {Z1.Q, Z2.Q}, p1, [sp, #-10, MUL VL] +st2q {Z30.Q, Z31.Q}, p1, [x3, #-2, MUL VL] + +st3q {Z0.Q, Z1.Q, Z2.Q}, p0, [x0, #0, MUL VL] +st3q {Z31.Q, Z0.Q, Z1.Q}, p0, [x0, #0, MUL VL] +st3q {Z0.Q, Z1.Q, Z2.Q}, p7, [x0, #0, MUL VL] +st3q {Z0.Q, Z1.Q, Z2.Q}, p0, [x30, #0, MUL VL] +st3q {Z0.Q, Z1.Q, Z2.Q}, p0, [x30] +st3q {Z0.Q, Z1.Q, Z2.Q}, p0, [x0, #-24, MUL VL] +st3q {Z0.Q, Z1.Q, Z2.Q}, p0, [x0, #21, MUL VL] +st3q {Z31.Q, Z0.Q, Z1.Q}, p7, [x30, #-24, MUL VL] +st3q {Z29.Q, Z30.Q, Z31.Q}, p7, [x30, #-3, MUL VL] +st3q {Z29.Q - Z30.Q - Z31.Q}, p7, [x30, #-3, MUL VL] +st3q {Z1.Q, Z2.Q, z3.Q}, p1, [sp, #-12, MUL VL] +st3q {Z29.Q - Z31.Q}, p7, [x30, #-3, MUL VL] + +st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0, [x0, #0, MUL VL] +st4q {Z31.Q, Z0.Q, Z1.Q, Z2.Q}, p0, [x0, #0, MUL VL] +st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p7, [x0, #0, MUL VL] +st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0, [x30, #0, MUL VL] +st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0, [x30] +st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0, [x0, #-32, MUL VL] +st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0, [x0, #28, MUL VL] +st4q {Z31.Q, Z0.Q, Z1.Q, Z2.Q}, p7, [x30, #-32, MUL VL] +st4q {Z28.Q, Z29.Q, Z30.Q, Z31.Q}, p7, [x30, #-4, MUL VL] +st4q {Z28.Q - Z29.Q - Z30.Q - Z31.Q}, p7, [x30, #-4, MUL VL] +st4q {Z1.Q, Z2.Q, z3.Q, Z4.Q}, p4, [sp, #-16, MUL VL] +st4q {Z28.Q - Z31.Q}, p7, [x30, #-4, MUL VL] + +st2q {Z0.Q, Z1.Q}, p0, [x0, x0, LSL #4] +st2q {Z31.Q, Z0.Q}, p0, [x0, x0, LSL #4] +st2q {Z0.Q, Z1.Q}, p7, [x0, x0, LSL #4] +st2q {Z0.Q, Z1.Q}, p0, [x30, x0, LSL #4] +st2q {Z0.Q, Z1.Q}, p0, [x0, x29, LSL #4] +st2q {Z31.Q, Z0.Q}, p7, [x30, x29, LSL #4] +st2q {Z15.Q, Z16.Q}, p4, [x10, x20, LSL #4] +st2q {Z20.Q, Z21.Q}, p3, [sp, x20, LSL #4] + +st3q {Z0.Q, Z1.Q, Z2.Q}, p0, [x0, x0, LSL #4] +st3q {Z31.Q, Z0.Q, Z1.Q}, p0, [x0, x0, LSL #4] +st3q {Z0.Q, Z1.Q, Z2.Q}, p7, [x0, x0, LSL #4] +st3q {Z0.Q, Z1.Q, Z2.Q}, p0, [x30, x0, LSL #4] +st3q {Z0.Q, Z1.Q, Z2.Q}, p0, [x0, x29, LSL #4] +st3q {Z31.Q, Z0.Q, Z1.Q}, p7, [x30, x29, LSL #4] +st3q {Z10.Q, Z11.Q, Z12.Q}, p2, [x10, x20, LSL #4] +st3q {Z10.Q - Z11.Q - Z12.Q}, p2, [x10, x20, LSL #4] +st3q {Z10.Q - Z12.Q}, p2, [x10, x20, LSL #4] +st3q {Z15.Q - Z17.Q}, p5, [sp, x20, LSL #4] + +st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0, [x0, x0, LSL #4] +st4q {Z31.Q, Z0.Q, Z1.Q, Z2.Q}, p0, [x0, x0, LSL #4] +st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p7, [x0, x0, LSL #4] +st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0, [x30, x0, LSL #4] +st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0, [x0, x29, LSL #4] +st4q {Z31.Q, Z0.Q, Z1.Q, Z2.Q}, p7, [x30, x29, LSL #4] +st4q {Z10.Q, Z11.Q, Z12.Q, Z13.Q}, p2, [x3, x4, LSL #4] +st4q {Z10.Q - Z11.Q - Z12.Q - Z13.Q}, p2, [x3, x4, LSL #4] +st4q {Z10.Q - Z13.Q}, p2, [x3, x4, LSL #4] +st4q {Z10.Q, Z11.Q, Z12.Q, Z13.Q}, p2, [sp, x4, LSL #4] diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 3ea4ce25faa..c08a456172e 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -650,6 +650,7 @@ enum aarch64_opnd AARCH64_OPND_SVE_ADDR_RX_LSL1, /* SVE [, , LSL #1]. */ AARCH64_OPND_SVE_ADDR_RX_LSL2, /* SVE [, , LSL #2]. */ AARCH64_OPND_SVE_ADDR_RX_LSL3, /* SVE [, , LSL #3]. */ + AARCH64_OPND_SVE_ADDR_RX_LSL4, /* SVE [, , LSL #4]. */ AARCH64_OPND_SVE_ADDR_ZX, /* SVE [Zn.{, }]. */ AARCH64_OPND_SVE_ADDR_RZ, /* SVE [, Zm.D]. */ AARCH64_OPND_SVE_ADDR_RZ_LSL1, /* SVE [, Zm.D, LSL #1]. */ @@ -816,9 +817,6 @@ enum aarch64_opnd AARCH64_OPND_MOPS_WB_Rn, /* Rn!, in bits [5, 9]. */ AARCH64_OPND_CSSC_SIMM8, /* CSSC signed 8-bit immediate. */ AARCH64_OPND_CSSC_UIMM8, /* CSSC unsigned 8-bit immediate. */ - AARCH64_OPND_SME_Zt2, /* Qobule SVE vector register list. */ - AARCH64_OPND_SME_Zt3, /* Trible SVE vector register list. */ - AARCH64_OPND_SME_Zt4, /* Quad SVE vector register list. */ AARCH64_OPND_RCPC3_ADDR_OPT_POSTIND, /* []{, #}. */ AARCH64_OPND_RCPC3_ADDR_OPT_PREIND_WB, /* [] or [, #]!. */ AARCH64_OPND_RCPC3_ADDR_POSTIND, /* [], #. */ diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 64831e28631..e1e241cb6ab 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -1908,9 +1908,6 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, case AARCH64_OPND_SME_Zmx4: case AARCH64_OPND_SME_Znx2: case AARCH64_OPND_SME_Znx4: - case AARCH64_OPND_SME_Zt2: - case AARCH64_OPND_SME_Zt3: - case AARCH64_OPND_SME_Zt4: num = get_operand_specific_data (&aarch64_operands[type]); if (!check_reglist (opnd, mismatch_detail, idx, num, 1)) return 0; @@ -2453,6 +2450,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, case AARCH64_OPND_SVE_ADDR_RX_LSL1: case AARCH64_OPND_SVE_ADDR_RX_LSL2: case AARCH64_OPND_SVE_ADDR_RX_LSL3: + case AARCH64_OPND_SVE_ADDR_RX_LSL4: case AARCH64_OPND_SVE_ADDR_RZ: case AARCH64_OPND_SVE_ADDR_RZ_LSL1: case AARCH64_OPND_SVE_ADDR_RZ_LSL2: @@ -3730,10 +3728,7 @@ print_register_list (char *buf, size_t size, const aarch64_opnd_info *opnd, /* The hyphenated form is preferred for disassembly if there is more than one register in the list, and the register numbers are monotonically increasing in increments of one. */ - if (stride == 1 && num_regs > 1 - && ((opnd->type != AARCH64_OPND_SME_Zt2) - && (opnd->type != AARCH64_OPND_SME_Zt3) - && (opnd->type != AARCH64_OPND_SME_Zt4))) + if (stride == 1 && num_regs > 1) snprintf (buf, size, "{%s-%s}%s", style_reg (styler, "%s%d.%s", prefix, first_reg, qlf_name), style_reg (styler, "%s%d.%s", prefix, last_reg, qlf_name), tb); @@ -3834,36 +3829,51 @@ print_register_offset_address (char *buf, size_t size, bool print_amount_p = true; const char *shift_name = aarch64_operand_modifiers[opnd->shifter.kind].name; - if (!opnd->shifter.amount && (opnd->qualifier != AARCH64_OPND_QLF_S_B - || !opnd->shifter.amount_present)) + /* This is the case where offset is the optional argument and the optional + argument is ignored in the disassembly. */ + if (opnd->type == AARCH64_OPND_SVE_ADDR_ZX && offset != NULL + && strcmp (offset,"xzr") == 0) { - /* Not print the shift/extend amount when the amount is zero and - when it is not the special case of 8-bit load/store instruction. */ - print_amount_p = false; - /* Likewise, no need to print the shift operator LSL in such a - situation. */ - if (opnd->shifter.kind == AARCH64_MOD_LSL) - print_extend_p = false; - } - - /* Prepare for the extend/shift. */ - if (print_extend_p) - { - if (print_amount_p) - snprintf (tb, sizeof (tb), ", %s %s", - style_sub_mnem (styler, shift_name), - style_imm (styler, "#%" PRIi64, - /* PR 21096: The %100 is to silence a warning about possible truncation. */ - (opnd->shifter.amount % 100))); - else - snprintf (tb, sizeof (tb), ", %s", - style_sub_mnem (styler, shift_name)); + /* Example: [.S{, }]. + When the assembly is [Z0.S, XZR] or [Z0.S], Xm is XZR in both the cases + and the preferred disassembly is [Z0.S], ignoring the optional Xm. */ + snprintf (buf, size, "[%s]", style_reg (styler, base)); } else - tb[0] = '\0'; + { + if (!opnd->shifter.amount && (opnd->qualifier != AARCH64_OPND_QLF_S_B + || !opnd->shifter.amount_present)) + { + /* Not print the shift/extend amount when the amount is zero and + when it is not the special case of 8-bit load/store + instruction. */ + print_amount_p = false; + /* Likewise, no need to print the shift operator LSL in such a + situation. */ + if (opnd->shifter.kind == AARCH64_MOD_LSL) + print_extend_p = false; + } - snprintf (buf, size, "[%s, %s%s]", style_reg (styler, base), - style_reg (styler, offset), tb); + /* Prepare for the extend/shift. */ + if (print_extend_p) + { + if (print_amount_p) + snprintf (tb, sizeof (tb), ", %s %s", + style_sub_mnem (styler, shift_name), + style_imm (styler, "#%" PRIi64, + /* PR 21096: The %100 is to silence a warning about possible + truncation. */ + (opnd->shifter.amount % 100))); + else + snprintf (tb, sizeof (tb), ", %s", + style_sub_mnem (styler, shift_name)); + } + else + tb[0] = '\0'; + + snprintf (buf, size, "[%s, %s%s]", style_reg (styler, base), + style_reg (styler, offset), tb); + } } /* Print ZA tiles from imm8 in ZERO instruction. @@ -4201,9 +4211,6 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, case AARCH64_OPND_SME_Znx4: case AARCH64_OPND_SME_Ztx2_STRIDED: case AARCH64_OPND_SME_Ztx4_STRIDED: - case AARCH64_OPND_SME_Zt2: - case AARCH64_OPND_SME_Zt3: - case AARCH64_OPND_SME_Zt4: print_register_list (buf, size, opnd, "z", styler); break; @@ -4655,6 +4662,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, case AARCH64_OPND_SVE_ADDR_RX_LSL1: case AARCH64_OPND_SVE_ADDR_RX_LSL2: case AARCH64_OPND_SVE_ADDR_RX_LSL3: + case AARCH64_OPND_SVE_ADDR_RX_LSL4: print_register_offset_address (buf, size, opnd, get_64bit_int_reg_name (opnd->addr.base_regno, 1), get_offset_int_reg_name (opnd), styler); diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index bf7918e76b2..5f907a2a845 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -1825,11 +1825,11 @@ { \ QLF3(S_S,P_Z,S_S), \ } -#define OP_SVE_SZS_QD \ +#define OP_SVE_QZD \ { \ QLF3(S_Q,P_Z,S_D), \ } -#define OP_SVE_SUS_QD \ +#define OP_SVE_QUD \ { \ QLF3(S_Q,NIL,S_D), \ } @@ -6520,21 +6520,23 @@ const struct aarch64_opcode aarch64_opcode_table[] = SVE2p1_INSN("dupq",0x05202400, 0xffe0fc00, sve_index, 0, OP2 (SVE_Zd, SVE_Zn_5_INDEX), OP_SVE_VV_BHSD, 0, 0), SVE2p1_INSNC("extq",0x05602400, 0xfff0fc00, sve_misc, 0, OP4 (SVE_Zd, SVE_Zd, SVE_Zm_5, SVE_UIMM4), OP_SVE_BBBU, 0, C_SCAN_MOVPRFX, 1), - SVE2p1_INSNC("ld1q",0xc400a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_Zt, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_SZS_QD, 0, C_SCAN_MOVPRFX, 0), - SVE2p1_INSNC("ld2q",0xa490e000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt2, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0), - SVE2p1_INSNC("ld3q",0xa510e000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt3, SVE_Pg3, SVE_ADDR_RI_S4x3xVL), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0), - SVE2p1_INSNC("ld4q",0xa590e000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt4, SVE_Pg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0), - SVE2p1_INSNC("ld2q",0xa4a08000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt2, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0), - SVE2p1_INSNC("ld3q",0xa5208000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt3, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0), - SVE2p1_INSNC("ld4q",0xa5a08000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt4, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0), - SVE2p1_INSNC("st1q",0xe4202000, 0xffe0e000, sve_misc, 0, OP3 (SVE_Zt, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_SUS_QD, 0, C_SCAN_MOVPRFX, 0), - SVE2p1_INSNC("st2q",0xe4400000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt2, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0), - SVE2p1_INSNC("st3q",0xe4800000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt3, SVE_Pg3, SVE_ADDR_RI_S4x3xVL), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0), - SVE2p1_INSNC("st4q",0xe4c00000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt4, SVE_Pg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0), - SVE2p1_INSNC("st2q",0xe4600000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt2, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0), - SVE2p1_INSNC("st3q",0xe4a00000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt3, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0), - SVE2p1_INSNC("st4q",0xe4e00000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt4, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0), + SVE2p1_INSN("ld1q",0xc400a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_QZD, F_OD (1), 0), + SVE2p1_INSN("ld2q",0xa490e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QZU, F_OD (2), 0), + SVE2p1_INSN("ld3q",0xa510e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x3xVL), OP_SVE_QZU, F_OD (3), 0), + SVE2p1_INSN("ld4q",0xa590e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_QZU, F_OD (4), 0), + SVE2p1_INSN("ld2q",0xa4a08000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL4), OP_SVE_QZU, F_OD (2), 0), + SVE2p1_INSN("ld3q",0xa5208000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL4), OP_SVE_QZU, F_OD (3), 0), + SVE2p1_INSN("ld4q",0xa5a08000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL4), OP_SVE_QZU, F_OD (4), 0), + + SVE2p1_INSN("st1q",0xe4202000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_QUD, F_OD (1), 0), + SVE2p1_INSN("st2q",0xe4400000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QUU, F_OD (2), 0), + SVE2p1_INSN("st3q",0xe4800000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x3xVL), OP_SVE_QUU, F_OD (3), 0), + SVE2p1_INSN("st4q",0xe4c00000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_QUU, F_OD (4), 0), + SVE2p1_INSN("st2q",0xe4600000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL4), OP_SVE_QUU, F_OD (2), 0), + SVE2p1_INSN("st3q",0xe4a00000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL4), OP_SVE_QUU, F_OD (3), 0), + SVE2p1_INSN("st4q",0xe4e00000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL4), OP_SVE_QUU, F_OD (4), 0), + FP8_INSN("bf1cvtl", 0x2ea17800, 0xfffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2FP8B8H, 0), FP8_INSN("bf1cvtl2", 0x6ea17800, 0xfffffc00, asimdmisc, OP2 (Vd, Vn), QL_V28H16B, 0), FP8_INSN("bf2cvtl", 0x2ee17800, 0xfffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2FP8B8H, 0), @@ -6897,6 +6899,9 @@ const struct aarch64_opcode aarch64_opcode_table[] = Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RX_LSL3", \ (3 << OPD_F_OD_LSB) | OPD_F_NO_ZR, F(FLD_Rn,FLD_Rm), \ "an address with a scalar register offset") \ + Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RX_LSL4", \ + (4 << OPD_F_OD_LSB) | OPD_F_NO_ZR, F(FLD_Rn,FLD_Rm), \ + "an address with a scalar register offset") \ Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_ZX", \ 0 << OPD_F_OD_LSB , F(FLD_SVE_Zn,FLD_Rm), \ "vector of address with a scalar register offset") \ @@ -7259,15 +7264,6 @@ const struct aarch64_opcode aarch64_opcode_table[] = "an 8-bit signed immediate") \ Y(IMMEDIATE, imm, "CSSC_UIMM8", 0, F(FLD_CSSC_imm8), \ "an 8-bit unsigned immediate") \ - X(SVE_REGLIST, ins_sve_reglist, ext_sve_reglist_zt, "SME_Zt2", \ - 2 << OPD_F_OD_LSB, F(FLD_SVE_Zt), \ - "a list of 2 SVE vector registers") \ - X(SVE_REGLIST, ins_sve_reglist, ext_sve_reglist_zt, "SME_Zt3", \ - 3 << OPD_F_OD_LSB, F(FLD_SVE_Zt), \ - "a list of 3 SVE vector registers") \ - X(SVE_REGLIST, ins_sve_reglist, ext_sve_reglist_zt, "SME_Zt4", \ - 4 << OPD_F_OD_LSB, F(FLD_SVE_Zt), \ - "a list of 4 SVE vector registers") \ X(ADDRESS, ins_rcpc3_addr_opt_offset, ext_rcpc3_addr_opt_offset, \ "RCPC3_ADDR_OPT_POSTIND", 0, F(FLD_opc2), \ "an address with post-incrementing by ammount of loaded bytes") \