diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index 279dd56b2e9..ceb21df2a98 100644
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -668,15 +668,15 @@ aarch64_insert_operand (const aarch64_operand *self,
     case 193:
     case 194:
     case 195:
-    case 210:
     case 211:
     case 212:
     case 213:
-    case 222:
+    case 214:
     case 223:
     case 224:
     case 225:
     case 226:
+    case 227:
     case 237:
     case 241:
     case 245:
@@ -710,9 +710,9 @@ aarch64_insert_operand (const aarch64_operand *self,
     case 39:
     case 40:
     case 41:
-    case 227:
     case 228:
-    case 231:
+    case 229:
+    case 232:
     case 264:
     case 265:
     case 280:
@@ -776,6 +776,7 @@ aarch64_insert_operand (const aarch64_operand *self,
     case 207:
     case 208:
     case 209:
+    case 210:
     case 266:
     case 293:
     case 294:
@@ -932,19 +933,18 @@ aarch64_insert_operand (const aarch64_operand *self,
     case 201:
     case 279:
       return aarch64_ins_sve_shrimm (self, info, code, inst, errors);
-    case 214:
     case 215:
     case 216:
     case 217:
-      return aarch64_ins_sme_za_vrs1 (self, info, code, inst, errors);
     case 218:
+      return aarch64_ins_sme_za_vrs1 (self, info, code, inst, errors);
     case 219:
     case 220:
     case 221:
+    case 222:
       return aarch64_ins_sme_za_vrs2 (self, info, code, inst, errors);
-    case 229:
     case 230:
-    case 232:
+    case 231:
     case 233:
     case 234:
     case 235:
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index e320bb53cdb..6d381879066 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -33665,15 +33665,15 @@ aarch64_extract_operand (const aarch64_operand *self,
     case 193:
     case 194:
     case 195:
-    case 210:
     case 211:
     case 212:
     case 213:
-    case 222:
+    case 214:
     case 223:
     case 224:
     case 225:
     case 226:
+    case 227:
     case 237:
     case 241:
     case 245:
@@ -33712,9 +33712,9 @@ aarch64_extract_operand (const aarch64_operand *self,
     case 39:
     case 40:
     case 41:
-    case 227:
     case 228:
-    case 231:
+    case 229:
+    case 232:
     case 264:
     case 265:
     case 280:
@@ -33779,6 +33779,7 @@ aarch64_extract_operand (const aarch64_operand *self,
     case 207:
     case 208:
     case 209:
+    case 210:
     case 266:
     case 293:
     case 294:
@@ -33937,19 +33938,18 @@ aarch64_extract_operand (const aarch64_operand *self,
     case 201:
     case 279:
       return aarch64_ext_sve_shrimm (self, info, code, inst, errors);
-    case 214:
     case 215:
     case 216:
     case 217:
-      return aarch64_ext_sme_za_vrs1 (self, info, code, inst, errors);
     case 218:
+      return aarch64_ext_sme_za_vrs1 (self, info, code, inst, errors);
     case 219:
     case 220:
     case 221:
+    case 222:
       return aarch64_ext_sme_za_vrs2 (self, info, code, inst, errors);
-    case 229:
     case 230:
-    case 232:
+    case 231:
     case 233:
     case 234:
     case 235:
diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index 78d8234bee7..9f3853bd1ad 100644
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -234,6 +234,7 @@ const struct aarch64_operand aarch64_operands[] =
   {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM7", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm7}, "a 7-bit unsigned immediate"},
   {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM8", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm8}, "an 8-bit unsigned immediate"},
   {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM8_53", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm5,FLD_imm3_10}, "an 8-bit unsigned immediate"},
+  {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM4", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm4}, "a 4-bit unsigned immediate"},
   {AARCH64_OPND_CLASS_SIMD_REG, "SVE_VZn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "a SIMD register"},
   {AARCH64_OPND_CLASS_SIMD_REG, "SVE_Vd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Vd}, "a SIMD register"},
   {AARCH64_OPND_CLASS_SIMD_REG, "SVE_Vm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Vm}, "a SIMD register"},
@@ -259,7 +260,6 @@ const struct aarch64_operand aarch64_operands[] =
   {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_19_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm2_19, FLD_SVE_imm3}, "an indexed SVE vector register"},
   {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_22_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i3h, FLD_SVE_Zm_16}, "an indexed SVE vector register"},
   {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm4_11_INDEX", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i2h, FLD_SVE_i3l, FLD_SVE_imm4}, "an indexed SVE vector register"},
-  {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm_imm4", 5 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_5, FLD_SVE_imm4}, "an 4bit indexed SVE vector register"},
   {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm4_INDEX", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an indexed SVE vector register"},
   {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an SVE vector register"},
   {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_SVE_tszh, FLD_imm5}, "an indexed SVE vector register"},