<html><head><meta http-equiv="content-type" content="text/html; charset=utf-8"></head><body style="overflow-wrap: break-word; -webkit-nbsp-mode: space; line-break: after-white-space;">Oh sorry. I didn't know there is also a changelog for that.<div>Thanks!<br id="lineBreakAtBeginningOfMessage"><div>
<div dir="auto" style="caret-color: rgb(0, 0, 0); color: rgb(0, 0, 0); letter-spacing: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; -webkit-text-stroke-width: 0px; text-decoration: none; overflow-wrap: break-word; -webkit-nbsp-mode: space; line-break: after-white-space;"><div><br></div><div><br></div><div>Hau Hsu</div><div><br></div></div><br class="Apple-interchange-newline"><br class="Apple-interchange-newline">
</div>
<div><br><blockquote type="cite"><div>On Jun 18, 2024, at 3:27 PM, Nelson Chu <nelson@rivosinc.com> wrote:</div><br class="Apple-interchange-newline"><div><div dir="ltr"><div>Committed with minor updates, since you forgot to update the changelog for gas/doc/c-riscv-texi.</div><div><br></div><div>Thanks</div><div>Nelson</div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Tue, Jun 18, 2024 at 2:50 PM Hau Hsu <<a href="mailto:hau.hsu@sifive.com">hau.hsu@sifive.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">Add SiFive cease extension.<br>
This aligns LLVM:<br>
* <a href="https://llvm.org/docs/RISCVUsage.html" rel="noreferrer" target="_blank">https://llvm.org/docs/RISCVUsage.html</a><br>
* <a href="https://github.com/llvm/llvm-project/pull/83896" rel="noreferrer" target="_blank">https://github.com/llvm/llvm-project/pull/83896</a><br>
<br>
bfd/ChangeLog:<br>
<br>
* bfd/elfxx-riscv.c (riscv_supported_vendor_x_ext): Add support for 'xsfcease'.<br>
(riscv_multi_subset_supports): Handle INSN_CLASS_XSFCEASE.<br>
(riscv_multi_subset_supports_ext): Handle INSN_CLASS_XSFCEASE.<br>
<br>
gas/ChangeLog:<br>
<br>
* gas/testsuite/gas/riscv/march-help.l: Add 'xsfcease' to the list of supported -march extensions.<br>
* gas/testsuite/gas/riscv/sifive-insns.d: Add test case for 'sf.cease'.<br>
* gas/testsuite/gas/riscv/sifive-insns.s: Add assembly and disassembly test for 'sf.cease'.<br>
<br>
include/ChangeLog:<br>
<br>
* include/opcode/riscv-opc.h (MATCH_SF_CEASE, MASK_SF_CEASE): Define match and mask for 'sf.cease'.<br>
* include/opcode/riscv.h (INSN_CLASS_XSFCEASE): Add new instruction class for 'xsfcease'.<br>
<br>
opcodes/ChangeLog:<br>
<br>
* opcodes/riscv-opc.c (riscv_opcodes): Add opcode entry for 'sf.cease'.<br>
---<br>
bfd/elfxx-riscv.c | 5 +++++<br>
gas/doc/c-riscv.texi | 5 +++++<br>
gas/testsuite/gas/riscv/march-help.l | 1 +<br>
gas/testsuite/gas/riscv/sifive-insns.d | 1 +<br>
gas/testsuite/gas/riscv/sifive-insns.s | 6 ++++++<br>
include/opcode/riscv-opc.h | 3 +++<br>
include/opcode/riscv.h | 1 +<br>
opcodes/riscv-opc.c | 3 +++<br>
8 files changed, 25 insertions(+)<br>
<br>
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c<br>
index 297d565285c..4943ec79d92 100644<br>
--- a/bfd/elfxx-riscv.c<br>
+++ b/bfd/elfxx-riscv.c<br>
@@ -1484,6 +1484,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =<br>
{"xtheadzvamo", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },<br>
{"xventanacondops", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },<br>
{"xsfvcp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0},<br>
+ {"xsfcease", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },<br>
{NULL, 0, 0, 0, 0}<br>
};<br>
<br>
@@ -2732,6 +2733,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,<br>
return riscv_subset_supports (rps, "xventanacondops");<br>
case INSN_CLASS_XSFVCP:<br>
return riscv_subset_supports (rps, "xsfvcp");<br>
+ case INSN_CLASS_XSFCEASE:<br>
+ return riscv_subset_supports (rps, "xsfcease");<br>
default:<br>
rps->error_handler<br>
(_("internal: unreachable INSN_CLASS_*"));<br>
@@ -2998,6 +3001,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,<br>
return "xtheadvector";<br>
case INSN_CLASS_XTHEADZVAMO:<br>
return "xtheadzvamo";<br>
+ case INSN_CLASS_XSFCEASE:<br>
+ return "xsfcease";<br>
default:<br>
rps->error_handler<br>
(_("internal: unreachable INSN_CLASS_*"));<br>
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi<br>
index 61bb7bcdadc..e579eeb58c0 100644<br>
--- a/gas/doc/c-riscv.texi<br>
+++ b/gas/doc/c-riscv.texi<br>
@@ -850,4 +850,9 @@ VCIX as a low-latency, high-throughput interface to a coprocessor.<br>
<br>
It is documented in @url{<a href="https://sifive.cdn.prismic.io/sifive/c3829e36-8552-41f0-a841-79945784241b_vcix-spec-software.pdf" rel="noreferrer" target="_blank">https://sifive.cdn.prismic.io/sifive/c3829e36-8552-41f0-a841-79945784241b_vcix-spec-software.pdf</a>}.<br>
<br>
+@item XSfCease<br>
+XSfCease provides an instruction to instigates power-down sequence.<br>
+<br>
+It is documented in @url{<a href="https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf" rel="noreferrer" target="_blank">https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf</a>}.<br>
+<br>
@end table<br>
diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l<br>
index d2b98383e80..b7f5f763690 100644<br>
--- a/gas/testsuite/gas/riscv/march-help.l<br>
+++ b/gas/testsuite/gas/riscv/march-help.l<br>
@@ -129,3 +129,4 @@ All available -march extensions for RISC-V:<br>
xtheadzvamo 1.0<br>
xventanacondops 1.0<br>
xsfvcp 1.0<br>
+ xsfcease 1.0<br>
diff --git a/gas/testsuite/gas/riscv/sifive-insns.d b/gas/testsuite/gas/riscv/sifive-insns.d<br>
index f7d63d1bce0..610f62588b3 100644<br>
--- a/gas/testsuite/gas/riscv/sifive-insns.d<br>
+++ b/gas/testsuite/gas/riscv/sifive-insns.d<br>
@@ -35,3 +35,4 @@ Disassembly of section .text:<br>
[ ]+[0-9a-f]+:[ ]+fc25c05b[ ]+sf.vc.v.xvw[ ]+0x3,v0,v2,a1<br>
[ ]+[0-9a-f]+:[ ]+fc27b05b[ ]+sf.vc.v.ivw[ ]+0x3,v0,v2,15<br>
[ ]+[0-9a-f]+:[ ]+fc25d05b[ ]+sf.vc.v.fvw[ ]+0x1,v0,v2,fa1<br>
+[ ]+[0-9a-f]+:[ ]+30500073[ ]+sf.cease<br>
diff --git a/gas/testsuite/gas/riscv/sifive-insns.s b/gas/testsuite/gas/riscv/sifive-insns.s<br>
index d593692c5c0..cdf90c1b3ba 100644<br>
--- a/gas/testsuite/gas/riscv/sifive-insns.s<br>
+++ b/gas/testsuite/gas/riscv/sifive-insns.s<br>
@@ -31,3 +31,9 @@<br>
sf.vc.v.ivw 0x3, v0, v2, 15<br>
sf.vc.v.fvw 0x1, v0, v2, fa1<br>
.option pop<br>
+<br>
+ # xscease<br>
+ .option push<br>
+ .option arch, +xsfcease1p0<br>
+ sf.cease<br>
+ .option pop<br>
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h<br>
index 511895eca2b..04712cb6cf7 100644<br>
--- a/include/opcode/riscv-opc.h<br>
+++ b/include/opcode/riscv-opc.h<br>
@@ -3148,6 +3148,9 @@<br>
#define MASK_SF_VC_FVW 0xfa00707f<br>
#define MATCH_SF_VC_V_FVW 0xf800505b<br>
#define MASK_SF_VC_V_FVW 0xfa00707f<br>
+/* Vendor-specific (SiFive) cease instruction. */<br>
+#define MATCH_SF_CEASE 0x30500073<br>
+#define MASK_SF_CEASE 0xffffffff<br>
/* Unprivileged Counter/Timers CSR addresses. */<br>
#define CSR_CYCLE 0xc00<br>
#define CSR_TIME 0xc01<br>
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h<br>
index 33df56d13af..e3870473aaa 100644<br>
--- a/include/opcode/riscv.h<br>
+++ b/include/opcode/riscv.h<br>
@@ -514,6 +514,7 @@ enum riscv_insn_class<br>
INSN_CLASS_XTHEADZVAMO,<br>
INSN_CLASS_XVENTANACONDOPS,<br>
INSN_CLASS_XSFVCP,<br>
+ INSN_CLASS_XSFCEASE,<br>
};<br>
<br>
/* This structure holds information for a particular instruction. */<br>
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c<br>
index ff08bd595c0..96732148c33 100644<br>
--- a/opcodes/riscv-opc.c<br>
+++ b/opcodes/riscv-opc.c<br>
@@ -3087,6 +3087,9 @@ const struct riscv_opcode riscv_opcodes[] =<br>
{"sf.vc.fvw", 0, INSN_CLASS_XSFVCP, "XsO1,Vd,Vt,S", MATCH_SF_VC_FVW, MASK_SF_VC_FVW, match_opcode, 0 },<br>
{"sf.vc.v.fvw", 0, INSN_CLASS_XSFVCP, "XsO1,Vd,Vt,S", MATCH_SF_VC_V_FVW, MASK_SF_VC_V_FVW, match_opcode, 0 },<br>
<br>
+/* Vendor-specific (SiFive) cease instruction. */<br>
+{"sf.cease", 0, INSN_CLASS_XSFCEASE, "", MATCH_SF_CEASE, MASK_SF_CEASE, match_opcode, 0 },<br>
+<br>
/* Terminate the list. */<br>
{0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}<br>
};<br>
-- <br>
2.31.1<br>
<br>
</blockquote></div></div>
</div></blockquote></div><br></div></body></html>