<html><head><meta http-equiv="content-type" content="text/html; charset=utf-8"></head><body style="overflow-wrap: break-word; -webkit-nbsp-mode: space; line-break: after-white-space;">Ping ~<div><br><div><div dir="auto" style="caret-color: rgb(0, 0, 0); color: rgb(0, 0, 0); letter-spacing: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; -webkit-text-stroke-width: 0px; text-decoration: none; overflow-wrap: break-word; -webkit-nbsp-mode: space; line-break: after-white-space;"><div>Hau Hsu</div><div><br></div></div><br class="Apple-interchange-newline"><br class="Apple-interchange-newline">
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<div><br><blockquote type="cite"><div>On May 21, 2024, at 3:41 PM, Hau Hsu <hau.hsu@sifive.com> wrote:</div><br class="Apple-interchange-newline"><div><div>Add SiFive vender cease extension.<br>This aligns LLVM:<br>https://llvm.org/docs/RISCVUsage.html<br>---<br> bfd/elfxx-riscv.c | 5 +++++<br> gas/testsuite/gas/riscv/march-help.l | 1 +<br> gas/testsuite/gas/riscv/sifive-insns.d | 3 ++-<br> gas/testsuite/gas/riscv/sifive-insns.s | 6 ++++++<br> include/opcode/riscv-opc.h | 3 +++<br> include/opcode/riscv.h | 1 +<br> opcodes/riscv-opc.c | 3 +++<br> 7 files changed, 21 insertions(+), 1 deletion(-)<br><br>diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c<br>index dfacb87eda0..c69a000a46e 100644<br>--- a/bfd/elfxx-riscv.c<br>+++ b/bfd/elfxx-riscv.c<br>@@ -1470,6 +1470,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =<br> {"xtheadzvamo",<span class="Apple-tab-span" style="white-space:pre"> </span>ISA_SPEC_CLASS_DRAFT,<span class="Apple-tab-span" style="white-space:pre"> </span>1, 0, 0 },<br> {"xventanacondops",<span class="Apple-tab-span" style="white-space:pre"> </span>ISA_SPEC_CLASS_DRAFT,<span class="Apple-tab-span" style="white-space:pre"> </span>1, 0, 0 },<br> {"xsfvcp",<span class="Apple-tab-span" style="white-space:pre"> </span><span class="Apple-tab-span" style="white-space:pre"> </span>ISA_SPEC_CLASS_DRAFT,<span class="Apple-tab-span" style="white-space:pre"> </span>1, 0, 0},<br>+ {"xsfcease",<span class="Apple-tab-span" style="white-space:pre"> </span><span class="Apple-tab-span" style="white-space:pre"> </span>ISA_SPEC_CLASS_DRAFT,<span class="Apple-tab-span" style="white-space:pre"> </span>1, 0, 0 },<br> {NULL, 0, 0, 0, 0}<br> };<br><br>@@ -2706,6 +2707,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,<br> return riscv_subset_supports (rps, "xventanacondops");<br> case INSN_CLASS_XSFVCP:<br> return riscv_subset_supports (rps, "xsfvcp");<br>+ case INSN_CLASS_XSFCEASE:<br>+ return riscv_subset_supports (rps, "xsfcease");<br> default:<br> rps->error_handler<br> (_("internal: unreachable INSN_CLASS_*"));<br>@@ -2960,6 +2963,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,<br> return "xtheadvector";<br> case INSN_CLASS_XTHEADZVAMO:<br> return "xtheadzvamo";<br>+ case INSN_CLASS_XSFCEASE:<br>+ return _("xsfcease");<br> default:<br> rps->error_handler<br> (_("internal: unreachable INSN_CLASS_*"));<br>diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l<br>index c5754837e05..b30790bb980 100644<br>--- a/gas/testsuite/gas/riscv/march-help.l<br>+++ b/gas/testsuite/gas/riscv/march-help.l<br>@@ -121,3 +121,4 @@ All available -march extensions for RISC-V:<br> <span class="Apple-tab-span" style="white-space:pre"> </span>xtheadzvamo 1.0<br> <span class="Apple-tab-span" style="white-space:pre"> </span>xventanacondops 1.0<br> <span class="Apple-tab-span" style="white-space:pre"> </span>xsfvcp 1.0<br>+<span class="Apple-tab-span" style="white-space:pre"> </span>xsfcease 1.0<br>diff --git a/gas/testsuite/gas/riscv/sifive-insns.d b/gas/testsuite/gas/riscv/sifive-insns.d<br>index f7d63d1bce0..ad811c328cd 100644<br>--- a/gas/testsuite/gas/riscv/sifive-insns.d<br>+++ b/gas/testsuite/gas/riscv/sifive-insns.d<br>@@ -33,5 +33,6 @@ Disassembly of section .text:<br> [ <span class="Apple-tab-span" style="white-space:pre"> </span>]+[0-9a-f]+:[ <span class="Apple-tab-span" style="white-space:pre"> </span>]+ac25d05b[ <span class="Apple-tab-span" style="white-space:pre"> </span>]+sf.vc.v.fvv[ <span class="Apple-tab-span" style="white-space:pre"> </span>]+0x1,v0,v2,fa1<br> [ <span class="Apple-tab-span" style="white-space:pre"> </span>]+[0-9a-f]+:[ <span class="Apple-tab-span" style="white-space:pre"> </span>]+fc20805b[ <span class="Apple-tab-span" style="white-space:pre"> </span>]+sf.vc.v.vvw[ <span class="Apple-tab-span" style="white-space:pre"> </span>]+0x3,v0,v2,v1<br> [ <span class="Apple-tab-span" style="white-space:pre"> </span>]+[0-9a-f]+:[ <span class="Apple-tab-span" style="white-space:pre"> </span>]+fc25c05b[ <span class="Apple-tab-span" style="white-space:pre"> </span>]+sf.vc.v.xvw[ <span class="Apple-tab-span" style="white-space:pre"> </span>]+0x3,v0,v2,a1<br>-[ <span class="Apple-tab-span" style="white-space:pre"> </span>]+[0-9a-f]+:[ <span class="Apple-tab-span" style="white-space:pre"> </span>]+fc27b05b[ <span class="Apple-tab-span" style="white-space:pre"> </span>]+sf.vc.v.ivw[ <span class="Apple-tab-span" style="white-space:pre"> </span>]+0x3,v0,v2,15<br>+[ <span class="Apple-tab-span" style="white-space:pre"> </span>]+[0-9a-f]+:[ <span class="Apple-tab-span" style="white-space:pre"> </span>]+fc27b05b[ <span class="Apple-tab-span" style="white-space:pre"> </span>]+sf.vc.v.ivw[ <span class="Apple-tab-span" style="white-space:pre"> </span>]+0x3,v0,v2,15<br> [ <span class="Apple-tab-span" style="white-space:pre"> </span>]+[0-9a-f]+:[ <span class="Apple-tab-span" style="white-space:pre"> </span>]+fc25d05b[ <span class="Apple-tab-span" style="white-space:pre"> </span>]+sf.vc.v.fvw[ <span class="Apple-tab-span" style="white-space:pre"> </span>]+0x1,v0,v2,fa1<br>+[ <span class="Apple-tab-span" style="white-space:pre"> </span>]+[0-9a-f]+:[ <span class="Apple-tab-span" style="white-space:pre"> </span>]+30500073[ <span class="Apple-tab-span" style="white-space:pre"> </span>]+sf.cease<br>diff --git a/gas/testsuite/gas/riscv/sifive-insns.s b/gas/testsuite/gas/riscv/sifive-insns.s<br>index d593692c5c0..cdf90c1b3ba 100644<br>--- a/gas/testsuite/gas/riscv/sifive-insns.s<br>+++ b/gas/testsuite/gas/riscv/sifive-insns.s<br>@@ -31,3 +31,9 @@<br> <span class="Apple-tab-span" style="white-space:pre"> </span>sf.vc.v.ivw 0x3, v0, v2, 15<br> <span class="Apple-tab-span" style="white-space:pre"> </span>sf.vc.v.fvw 0x1, v0, v2, fa1<br> <span class="Apple-tab-span" style="white-space:pre"> </span>.option pop<br>+<br>+<span class="Apple-tab-span" style="white-space:pre"> </span># xscease<br>+<span class="Apple-tab-span" style="white-space:pre"> </span>.option push<br>+<span class="Apple-tab-span" style="white-space:pre"> </span>.option arch, +xsfcease1p0<br>+<span class="Apple-tab-span" style="white-space:pre"> </span>sf.cease<br>+<span class="Apple-tab-span" style="white-space:pre"> </span>.option pop<br>diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h<br>index ae14e14d427..d2d08c6526d 100644<br>--- a/include/opcode/riscv-opc.h<br>+++ b/include/opcode/riscv-opc.h<br>@@ -3076,6 +3076,9 @@<br> #define MASK_SF_VC_FVW 0xfa00707f<br> #define MATCH_SF_VC_V_FVW 0xf800505b<br> #define MASK_SF_VC_V_FVW 0xfa00707f<br>+/* Vendor-specific (SiFive) cease instruction. */<br>+#define MATCH_SF_CEASE 0x30500073<br>+#define MASK_SF_CEASE 0xffffffff<br> /* Unprivileged Counter/Timers CSR addresses. */<br> #define CSR_CYCLE 0xc00<br> #define CSR_TIME 0xc01<br>diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h<br>index 5f516a1026e..d6081caa0dd 100644<br>--- a/include/opcode/riscv.h<br>+++ b/include/opcode/riscv.h<br>@@ -505,6 +505,7 @@ enum riscv_insn_class<br> INSN_CLASS_XTHEADZVAMO,<br> INSN_CLASS_XVENTANACONDOPS,<br> INSN_CLASS_XSFVCP,<br>+ INSN_CLASS_XSFCEASE,<br> };<br><br> /* This structure holds information for a particular instruction. */<br>diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c<br>index 1ef4eaddf4d..01ced23d657 100644<br>--- a/opcodes/riscv-opc.c<br>+++ b/opcodes/riscv-opc.c<br>@@ -3041,6 +3041,9 @@ const struct riscv_opcode riscv_opcodes[] =<br> {"sf.vc.fvw", 0, INSN_CLASS_XSFVCP, "XsO1,Vd,Vt,S", MATCH_SF_VC_FVW, MASK_SF_VC_FVW, match_opcode, 0 },<br> {"sf.vc.v.fvw", 0, INSN_CLASS_XSFVCP, "XsO1,Vd,Vt,S", MATCH_SF_VC_V_FVW, MASK_SF_VC_V_FVW, match_opcode, 0 },<br><br>+/* Vendor-specific (SiFive) cease instruction. */<br>+{"sf.cease", 0, INSN_CLASS_XSFCEASE, "", MATCH_SF_CEASE, MASK_SF_CEASE, match_opcode, 0 },<br>+<br> /* Terminate the list. */<br> {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}<br> };<br>-- <br>2.31.1<br><br></div></div></blockquote></div><br></div></body></html>