<div dir="ltr"><div dir="ltr"><br></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Mon, Jan 8, 2024 at 9:41 PM Mary Bennett <<a href="mailto:mary.bennett@embecosm.com">mary.bennett@embecosm.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-style:solid;border-left-color:rgb(204,204,204);padding-left:1ex">Spec: <a href="https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html" rel="noreferrer" target="_blank">https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html</a><br>
<br>
Contributors:<br>
Mary Bennett <<a href="mailto:mary.bennett@embecosm.com" target="_blank">mary.bennett@embecosm.com</a>><br>
Nandni Jamnadas <<a href="mailto:nandni.jamnadas@embecosm.com" target="_blank">nandni.jamnadas@embecosm.com</a>><br>
Pietra Ferreira <<a href="mailto:pietra.ferreira@embecosm.com" target="_blank">pietra.ferreira@embecosm.com</a>><br>
Charlie Keaney<br>
Jessica Mills<br>
Craig Blackmore <<a href="mailto:craig.blackmore@embecosm.com" target="_blank">craig.blackmore@embecosm.com</a>><br>
Simon Cook <<a href="mailto:simon.cook@embecosm.com" target="_blank">simon.cook@embecosm.com</a>><br>
Jeremy Bennett <<a href="mailto:jeremy.bennett@embecosm.com" target="_blank">jeremy.bennett@embecosm.com</a>><br>
Helene Chelin <<a href="mailto:helene.chelin@embecosm.com" target="_blank">helene.chelin@embecosm.com</a>><br>
Nazareno Bruschi <<a href="mailto:nazareno.bruschi@embecosm.com" target="_blank">nazareno.bruschi@embecosm.com</a>><br>
Lin Sinan<br>
<br>
include/ChangeLog:<br>
* opcode/riscv-opc.h: Add corresponding MATCH and MASK<br>
macros for XCVbi.<br>
* opcode/riscv.h: Add corresponding EXTRACT and ENCODE macros<br>
for XCVbi.<br>
(enum riscv_insn_class): Add the XCVbi instruction class.<br>
<br>
gas/ChangeLog:<br>
* config/tc-riscv.c (validate_riscv_insn): Add the necessary<br>
operands for the extension.<br>
(riscv_ip): Likewise.<br>
* doc/c-riscv.texi: Note XCVbi as an additional ISA extension<br>
for CORE-V.<br>
* testsuite/gas/riscv/cv-bi-beqimm.d: New test.<br>
* testsuite/gas/riscv/cv-bi-beqimm.s: New test.<br>
* testsuite/gas/riscv/cv-bi-bneimm.d: New test.<br>
* testsuite/gas/riscv/cv-bi-bneimm.s: New test.<br>
* testsuite/gas/riscv/cv-bi-fail-march.d: New test.<br>
* testsuite/gas/riscv/cv-bi-fail-march.l: New test.<br>
* testsuite/gas/riscv/cv-bi-fail-march.s: New test.<br>
* testsuite/gas/riscv/cv-bi-fail-operand-01.d: New test.<br>
* testsuite/gas/riscv/cv-bi-fail-operand-01.l: New test.<br>
* testsuite/gas/riscv/cv-bi-fail-operand-01.s: New test.<br>
* testsuite/gas/riscv/cv-bi-fail-operand-02.d: New test.<br>
* testsuite/gas/riscv/cv-bi-fail-operand-02.l: New test.<br>
* testsuite/gas/riscv/cv-bi-fail-operand-02.s: New test.<br>
* testsuite/gas/riscv/cv-bi-fail-operand-03.d: New test.<br>
* testsuite/gas/riscv/cv-bi-fail-operand-03.l: New test.<br>
* testsuite/gas/riscv/cv-bi-fail-operand-03.s: New test.<br>
<br>
include/ChangeLog:<br>
* opcode/riscv-opc.h: Add corresponding MATCH and MASK<br>
macros for XCVbi.<br>
* opcode/riscv.h: Add corresponding EXTRACT and ENCODE macros<br>
for XCVbi.<br>
(enum riscv_insn_class): Add the XCVbi instruction class.<br>
<br>
ld/ChangeLog:<br>
* testsuite/ld-riscv-elf/cv-bi-beqimm.d: New test.<br>
* testsuite/ld-riscv-elf/cv-bi-beqimm.s: New test.<br>
* testsuite/ld-riscv-elf/cv-bi-bneimm.d: New test.<br>
* testsuite/ld-riscv-elf/cv-bi-bneimm.s: New test.<br>
* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Add new tests.<br></blockquote><div><br></div><div>Seems like this patch doesn't change ld code, so not sure if the ld test cases are needed or not?</div><div> </div><div>Nelson</div><div><br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-style:solid;border-left-color:rgb(204,204,204);padding-left:1ex">
opcodes/ChangeLog:<br>
* riscv-dis.c (print_insn_args): Add disassembly for new operand.<br>
* riscv-opc.c: Add XCVbi instructions.<br>
---<br>
bfd/elfxx-riscv.c | 5 +++++<br>
gas/config/tc-riscv.c | 12 ++++++++++-<br>
gas/doc/c-riscv.texi | 5 +++++<br>
gas/testsuite/gas/riscv/cv-bi-beqimm.d | 12 +++++++++++<br>
gas/testsuite/gas/riscv/cv-bi-beqimm.s | 4 ++++<br>
gas/testsuite/gas/riscv/cv-bi-bneimm.d | 12 +++++++++++<br>
gas/testsuite/gas/riscv/cv-bi-bneimm.s | 4 ++++<br>
gas/testsuite/gas/riscv/cv-bi-fail-march.d | 3 +++<br>
gas/testsuite/gas/riscv/cv-bi-fail-march.l | 3 +++<br>
gas/testsuite/gas/riscv/cv-bi-fail-march.s | 5 +++++<br>
.../gas/riscv/cv-bi-fail-operand-01.d | 3 +++<br>
.../gas/riscv/cv-bi-fail-operand-01.l | 3 +++<br>
.../gas/riscv/cv-bi-fail-operand-01.s | 4 ++++<br>
.../gas/riscv/cv-bi-fail-operand-02.d | 3 +++<br>
.../gas/riscv/cv-bi-fail-operand-02.l | 3 +++<br>
.../gas/riscv/cv-bi-fail-operand-02.s | 4 ++++<br>
.../gas/riscv/cv-bi-fail-operand-03.d | 3 +++<br>
.../gas/riscv/cv-bi-fail-operand-03.l | 9 ++++++++<br>
.../gas/riscv/cv-bi-fail-operand-03.s | 10 +++++++++<br>
include/opcode/riscv-opc.h | 5 +++++<br>
include/opcode/riscv.h | 4 ++++<br>
ld/testsuite/ld-riscv-elf/cv-bi-beqimm.d | 21 +++++++++++++++++++<br>
ld/testsuite/ld-riscv-elf/cv-bi-beqimm.s | 11 ++++++++++<br>
ld/testsuite/ld-riscv-elf/cv-bi-bneimm.d | 21 +++++++++++++++++++<br>
ld/testsuite/ld-riscv-elf/cv-bi-bneimm.s | 11 ++++++++++<br>
ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp | 2 ++<br>
opcodes/riscv-dis.c | 4 ++++<br>
opcodes/riscv-opc.c | 4 ++++<br>
28 files changed, 189 insertions(+), 1 deletion(-)<br>
create mode 100644 gas/testsuite/gas/riscv/cv-bi-beqimm.d<br>
create mode 100644 gas/testsuite/gas/riscv/cv-bi-beqimm.s<br>
create mode 100644 gas/testsuite/gas/riscv/cv-bi-bneimm.d<br>
create mode 100644 gas/testsuite/gas/riscv/cv-bi-bneimm.s<br>
create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-march.d<br>
create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-march.l<br>
create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-march.s<br>
create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-01.d<br>
create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-01.l<br>
create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-01.s<br>
create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-02.d<br>
create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-02.l<br>
create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-02.s<br>
create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-03.d<br>
create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-03.l<br>
create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-03.s<br>
create mode 100644 ld/testsuite/ld-riscv-elf/cv-bi-beqimm.d<br>
create mode 100644 ld/testsuite/ld-riscv-elf/cv-bi-beqimm.s<br>
create mode 100644 ld/testsuite/ld-riscv-elf/cv-bi-bneimm.d<br>
create mode 100644 ld/testsuite/ld-riscv-elf/cv-bi-bneimm.s<br>
<br>
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c<br>
index b8e64a17da0..646f1eddb70 100644<br>
--- a/bfd/elfxx-riscv.c<br>
+++ b/bfd/elfxx-riscv.c<br>
@@ -1370,6 +1370,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =<br>
{"xcvmac", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },<br>
{"xcvalu", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },<br>
{"xcvelw", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },<br>
+ {"xcvbi", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },<br>
{"xtheadba", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },<br>
{"xtheadbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },<br>
{"xtheadbs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },<br>
@@ -2579,6 +2580,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,<br>
return riscv_subset_supports (rps, "xcvalu");<br>
case INSN_CLASS_XCVELW:<br>
return riscv_subset_supports (rps, "xcvelw");<br>
+ case INSN_CLASS_XCVBI:<br>
+ return riscv_subset_supports (rps, "xcvbi");<br>
case INSN_CLASS_XTHEADBA:<br>
return riscv_subset_supports (rps, "xtheadba");<br>
case INSN_CLASS_XTHEADBB:<br>
@@ -2833,6 +2836,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,<br>
return "xcvalu";<br>
case INSN_CLASS_XCVELW:<br>
return "xcvelw";<br>
+ case INSN_CLASS_XCVBI:<br>
+ return "xcvbi";<br>
case INSN_CLASS_XTHEADBA:<br>
return "xtheadba";<br>
case INSN_CLASS_XTHEADBB:<br>
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c<br>
index a4161420128..77c42e5d8f4 100644<br>
--- a/gas/config/tc-riscv.c<br>
+++ b/gas/config/tc-riscv.c<br>
@@ -1501,7 +1501,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)<br>
switch (*++oparg)<br>
{<br>
case '2':<br>
- /* ls2[4:0] */<br>
+ case '4':<br>
used_bits |= ENCODE_CV_IS2_UIMM5 (-1U);<br>
break;<br>
case '3':<br>
@@ -3770,6 +3770,16 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,<br>
ip->insn_opcode<br>
|= ENCODE_CV_IS3_UIMM5 (imm_expr->X_add_number);<br>
continue;<br>
+ case '4':<br>
+ my_getExpression (imm_expr, asarg);<br>
+ check_absolute_expr (ip, imm_expr, FALSE);<br>
+ asarg = expr_parse_end;<br>
+ if (imm_expr->X_add_number < -16<br>
+ || imm_expr->X_add_number > 15)<br>
+ break;<br>
+ ip->insn_opcode<br>
+ |= ENCODE_CV_IS2_UIMM5 (imm_expr->X_add_number);<br>
+ continue;<br>
default:<br>
goto unknown_riscv_ip_operand;<br>
}<br>
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi<br>
index d1712b578a0..d983f9b7bba 100644<br>
--- a/gas/doc/c-riscv.texi<br>
+++ b/gas/doc/c-riscv.texi<br>
@@ -755,6 +755,11 @@ The Xcvelw extension provides instructions for event load word operations.<br>
<br>
It is documented in @url{<a href="https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html" rel="noreferrer" target="_blank">https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html</a>}<br>
<br>
+@item Xcvbi<br>
+The Xcvbi extension provides instructions for branch immediate operations.<br>
+<br>
+It is documented in @url{<a href="https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html" rel="noreferrer" target="_blank">https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html</a>}<br>
+<br>
@item XTheadBa<br>
The XTheadBa extension provides instructions for address calculations.<br>
<br>
diff --git a/gas/testsuite/gas/riscv/cv-bi-beqimm.d b/gas/testsuite/gas/riscv/cv-bi-beqimm.d<br>
new file mode 100644<br>
index 00000000000..97ef57d91cc<br>
--- /dev/null<br>
+++ b/gas/testsuite/gas/riscv/cv-bi-beqimm.d<br>
@@ -0,0 +1,12 @@<br>
+#as: -march=rv32i_xcvbi<br>
+#objdump: -d<br>
+<br>
+.*:[ ]+file format .*<br>
+<br>
+<br>
+Disassembly of section .text:<br>
+<br>
+0+000 <foo>:<br>
+[ ]+0:[ ]+0102e00b[ ]+cv.beqimm[ ]+t0,-16,0 +<foo><br>
+[ ]+4:[ ]+fe5eee8b[ ]+cv.beqimm[ ]+t4,5,0 +<foo><br>
+[ ]+8:[ ]+fef3ec8b[ ]+cv.beqimm[ ]+t2,15,0 +<foo><br>
diff --git a/gas/testsuite/gas/riscv/cv-bi-beqimm.s b/gas/testsuite/gas/riscv/cv-bi-beqimm.s<br>
new file mode 100644<br>
index 00000000000..7fbb8f27515<br>
--- /dev/null<br>
+++ b/gas/testsuite/gas/riscv/cv-bi-beqimm.s<br>
@@ -0,0 +1,4 @@<br>
+foo:<br>
+ cv.beqimm t0, -16, foo<br>
+ cv.beqimm t4, 5, foo<br>
+ cv.beqimm t2, 15, foo<br>
diff --git a/gas/testsuite/gas/riscv/cv-bi-bneimm.d b/gas/testsuite/gas/riscv/cv-bi-bneimm.d<br>
new file mode 100644<br>
index 00000000000..7dddf408107<br>
--- /dev/null<br>
+++ b/gas/testsuite/gas/riscv/cv-bi-bneimm.d<br>
@@ -0,0 +1,12 @@<br>
+#as: -march=rv32i_xcvbi<br>
+#objdump: -d<br>
+<br>
+.*:[ ]+file format .*<br>
+<br>
+<br>
+Disassembly of section .text:<br>
+<br>
+0+000 <foo>:<br>
+[ ]+0:[ ]+0102f00b[ ]+cv.bneimm[ ]+t0,-16,0 +<foo><br>
+[ ]+4:[ ]+fe5efe8b[ ]+cv.bneimm[ ]+t4,5,0 +<foo><br>
+[ ]+8:[ ]+fef3fc8b[ ]+cv.bneimm[ ]+t2,15,0 +<foo><br>
diff --git a/gas/testsuite/gas/riscv/cv-bi-bneimm.s b/gas/testsuite/gas/riscv/cv-bi-bneimm.s<br>
new file mode 100644<br>
index 00000000000..8014e6a8a4f<br>
--- /dev/null<br>
+++ b/gas/testsuite/gas/riscv/cv-bi-bneimm.s<br>
@@ -0,0 +1,4 @@<br>
+foo:<br>
+ cv.bneimm t0, -16, foo<br>
+ cv.bneimm t4, 5, foo<br>
+ cv.bneimm t2, 15, foo<br>
diff --git a/gas/testsuite/gas/riscv/cv-bi-fail-march.d b/gas/testsuite/gas/riscv/cv-bi-fail-march.d<br>
new file mode 100644<br>
index 00000000000..7a24146afe2<br>
--- /dev/null<br>
+++ b/gas/testsuite/gas/riscv/cv-bi-fail-march.d<br>
@@ -0,0 +1,3 @@<br>
+#as: -march=rv32i<br>
+#source: cv-bi-fail-march.s<br>
+#error_output: cv-bi-fail-march.l<br>
diff --git a/gas/testsuite/gas/riscv/cv-bi-fail-march.l b/gas/testsuite/gas/riscv/cv-bi-fail-march.l<br>
new file mode 100644<br>
index 00000000000..c351c64d414<br>
--- /dev/null<br>
+++ b/gas/testsuite/gas/riscv/cv-bi-fail-march.l<br>
@@ -0,0 +1,3 @@<br>
+.*: Assembler messages:<br>
+.*: Error: unrecognized opcode `cv.beqimm t2,1,foo', extension `xcvbi' required<br>
+.*: Error: unrecognized opcode `cv.bneimm t2,1,foo', extension `xcvbi' required<br>
diff --git a/gas/testsuite/gas/riscv/cv-bi-fail-march.s b/gas/testsuite/gas/riscv/cv-bi-fail-march.s<br>
new file mode 100644<br>
index 00000000000..b7fa16de240<br>
--- /dev/null<br>
+++ b/gas/testsuite/gas/riscv/cv-bi-fail-march.s<br>
@@ -0,0 +1,5 @@<br>
+# Absence of xcorev or xcorevbi march option disables all CORE-V<br>
+# immediate branching extensions.<br>
+foo:<br>
+ cv.beqimm t2, 1, foo<br>
+ cv.bneimm t2, 1, foo<br>
diff --git a/gas/testsuite/gas/riscv/cv-bi-fail-operand-01.d b/gas/testsuite/gas/riscv/cv-bi-fail-operand-01.d<br>
new file mode 100644<br>
index 00000000000..cc73fdd6492<br>
--- /dev/null<br>
+++ b/gas/testsuite/gas/riscv/cv-bi-fail-operand-01.d<br>
@@ -0,0 +1,3 @@<br>
+#as: -march=rv32i_xcvbi<br>
+#source: cv-bi-fail-operand-01.s<br>
+#error_output: cv-bi-fail-operand-01.l<br>
diff --git a/gas/testsuite/gas/riscv/cv-bi-fail-operand-01.l b/gas/testsuite/gas/riscv/cv-bi-fail-operand-01.l<br>
new file mode 100644<br>
index 00000000000..c76c5139429<br>
--- /dev/null<br>
+++ b/gas/testsuite/gas/riscv/cv-bi-fail-operand-01.l<br>
@@ -0,0 +1,3 @@<br>
+.*: Assembler messages:<br>
+.*: Error: illegal operands `cv.beqimm 20,10,foo'<br>
+.*: Error: illegal operands `cv.bneimm 8,-4,foo'<br>
diff --git a/gas/testsuite/gas/riscv/cv-bi-fail-operand-01.s b/gas/testsuite/gas/riscv/cv-bi-fail-operand-01.s<br>
new file mode 100644<br>
index 00000000000..7c529d4d045<br>
--- /dev/null<br>
+++ b/gas/testsuite/gas/riscv/cv-bi-fail-operand-01.s<br>
@@ -0,0 +1,4 @@<br>
+# Comparison target must be a register<br>
+foo:<br>
+ cv.beqimm 20, 10, foo<br>
+ cv.bneimm 8, -4, foo<br>
diff --git a/gas/testsuite/gas/riscv/cv-bi-fail-operand-02.d b/gas/testsuite/gas/riscv/cv-bi-fail-operand-02.d<br>
new file mode 100644<br>
index 00000000000..39741b9ed2b<br>
--- /dev/null<br>
+++ b/gas/testsuite/gas/riscv/cv-bi-fail-operand-02.d<br>
@@ -0,0 +1,3 @@<br>
+#as: -march=rv32i_xcvbi<br>
+#source: cv-bi-fail-operand-02.s<br>
+#error_output: cv-bi-fail-operand-02.l<br>
diff --git a/gas/testsuite/gas/riscv/cv-bi-fail-operand-02.l b/gas/testsuite/gas/riscv/cv-bi-fail-operand-02.l<br>
new file mode 100644<br>
index 00000000000..7c766fb072a<br>
--- /dev/null<br>
+++ b/gas/testsuite/gas/riscv/cv-bi-fail-operand-02.l<br>
@@ -0,0 +1,3 @@<br>
+.*: Assembler messages:<br>
+.*: Error: instruction cv.beqimm requires absolute expression<br>
+.*: Error: instruction cv.bneimm requires absolute expression<br>
diff --git a/gas/testsuite/gas/riscv/cv-bi-fail-operand-02.s b/gas/testsuite/gas/riscv/cv-bi-fail-operand-02.s<br>
new file mode 100644<br>
index 00000000000..5c8874cb9ac<br>
--- /dev/null<br>
+++ b/gas/testsuite/gas/riscv/cv-bi-fail-operand-02.s<br>
@@ -0,0 +1,4 @@<br>
+# Comparison value must be an immediate<br>
+foo:<br>
+ cv.beqimm t0, t1, foo<br>
+ cv.bneimm t3, t4, foo<br>
diff --git a/gas/testsuite/gas/riscv/cv-bi-fail-operand-03.d b/gas/testsuite/gas/riscv/cv-bi-fail-operand-03.d<br>
new file mode 100644<br>
index 00000000000..141efdeacc6<br>
--- /dev/null<br>
+++ b/gas/testsuite/gas/riscv/cv-bi-fail-operand-03.d<br>
@@ -0,0 +1,3 @@<br>
+#as: -march=rv32i_xcvbi<br>
+#source: cv-bi-fail-operand-03.s<br>
+#error_output: cv-bi-fail-operand-03.l<br>
diff --git a/gas/testsuite/gas/riscv/cv-bi-fail-operand-03.l b/gas/testsuite/gas/riscv/cv-bi-fail-operand-03.l<br>
new file mode 100644<br>
index 00000000000..af8ebce1284<br>
--- /dev/null<br>
+++ b/gas/testsuite/gas/riscv/cv-bi-fail-operand-03.l<br>
@@ -0,0 +1,9 @@<br>
+.*: Assembler messages:<br>
+.*: Error: illegal operands `cv.beqimm t0,-17,foo'<br>
+.*: Error: illegal operands `cv.beqimm t2,-32,foo'<br>
+.*: Error: illegal operands `cv.beqimm t4,16,foo'<br>
+.*: Error: illegal operands `cv.beqimm t3,44,foo'<br>
+.*: Error: illegal operands `cv.bneimm t0,-17,foo'<br>
+.*: Error: illegal operands `cv.bneimm t2,-32,foo'<br>
+.*: Error: illegal operands `cv.bneimm t4,16,foo'<br>
+.*: Error: illegal operands `cv.bneimm t3,44,foo'<br>
diff --git a/gas/testsuite/gas/riscv/cv-bi-fail-operand-03.s b/gas/testsuite/gas/riscv/cv-bi-fail-operand-03.s<br>
new file mode 100644<br>
index 00000000000..9c7f67b4aed<br>
--- /dev/null<br>
+++ b/gas/testsuite/gas/riscv/cv-bi-fail-operand-03.s<br>
@@ -0,0 +1,10 @@<br>
+# Comparison value must be an immediate in range [-16, +15]<br>
+foo:<br>
+ cv.beqimm t0, -17, foo<br>
+ cv.beqimm t2, -32, foo<br>
+ cv.beqimm t4, 16, foo<br>
+ cv.beqimm t3, 44, foo<br>
+ cv.bneimm t0, -17, foo<br>
+ cv.bneimm t2, -32, foo<br>
+ cv.bneimm t4, 16, foo<br>
+ cv.bneimm t3, 44, foo<br>
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h<br>
index 36eb3b5e723..596fad4000f 100644<br>
--- a/include/opcode/riscv-opc.h<br>
+++ b/include/opcode/riscv-opc.h<br>
@@ -2427,6 +2427,11 @@<br>
/* Vendor-specific (CORE-V) Xcvelw instructions. */<br>
#define MATCH_CV_ELW 0x600b<br>
#define MASK_CV_ELW 0x707f<br>
+/* Vendor-specific (CORE-V) Xcvbi instructions. */<br>
+#define MATCH_CV_BNEIMM 0x700b<br>
+#define MASK_CV_BNEIMM 0x707f<br>
+#define MATCH_CV_BEQIMM 0x600b<br>
+#define MASK_CV_BEQIMM 0x707f<br>
/* Vendor-specific (T-Head) XTheadBa instructions. */<br>
#define MATCH_TH_ADDSL 0x0000100b<br>
#define MASK_TH_ADDSL 0xf800707f<br>
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h<br>
index e385bf4ea7a..c15a90dd9b2 100644<br>
--- a/include/opcode/riscv.h<br>
+++ b/include/opcode/riscv.h<br>
@@ -55,6 +55,7 @@ static inline unsigned int riscv_insn_length (insn_t insn)<br>
#define RV_X(x, s, n) (((x) >> (s)) & ((1 << (n)) - 1))<br>
#define RV_IMM_SIGN(x) (-(((x) >> 31) & 1))<br>
#define RV_X_SIGNED(x, s, n) (RV_X(x, s, n) | ((-(RV_X(x, (s + n - 1), 1))) << (n)))<br>
+#define RV_IMM_SIGN_N(x, s, n) (-(((x) >> ((s) + (n) - 1)) & 1))<br>
<br>
#define EXTRACT_ITYPE_IMM(x) \<br>
(RV_X(x, 20, 12) | (RV_IMM_SIGN(x) << 12))<br>
@@ -117,6 +118,8 @@ static inline unsigned int riscv_insn_length (insn_t insn)<br>
(RV_X(x, 20, 5))<br>
#define EXTRACT_CV_IS3_UIMM5(x) \<br>
(RV_X(x, 25, 5))<br>
+#define EXTRACT_CV_BI_IMM5(x) \<br>
+ (RV_X(x, 20, 5) | (RV_IMM_SIGN_N(x, 20, 5) << 5))<br>
<br>
#define ENCODE_ITYPE_IMM(x) \<br>
(RV_X(x, 0, 12) << 20)<br>
@@ -472,6 +475,7 @@ enum riscv_insn_class<br>
INSN_CLASS_XCVMAC,<br>
INSN_CLASS_XCVALU,<br>
INSN_CLASS_XCVELW,<br>
+ INSN_CLASS_XCVBI,<br>
INSN_CLASS_XTHEADBA,<br>
INSN_CLASS_XTHEADBB,<br>
INSN_CLASS_XTHEADBS,<br>
diff --git a/ld/testsuite/ld-riscv-elf/cv-bi-beqimm.d b/ld/testsuite/ld-riscv-elf/cv-bi-beqimm.d<br>
new file mode 100644<br>
index 00000000000..b50d3846c1c<br>
--- /dev/null<br>
+++ b/ld/testsuite/ld-riscv-elf/cv-bi-beqimm.d<br>
@@ -0,0 +1,21 @@<br>
+#name: beqimm relocation<br>
+#source: cv-bi-beqimm.s<br>
+#as: -march=rv32i_xcvbi<br>
+#ld: -melf32lriscv<br>
+#objdump: -dr<br>
+<br>
+.*: file format .*<br>
+<br>
+<br>
+Disassembly of section \.text:<br>
+<br>
+.* <func>:<br>
+.*:[[:space:]]+00008067[[:space:]]+ret<br>
+<br>
+.* <_start>:<br>
+.*:[[:space:]]+0102e40b[[:space:]]+cv.beqimm[[:space:]]+t0,-16,.*[[:space:]]+<L2><br>
+.*:[[:space:]]+ff9ff0ef[[:space:]]+jal[[:space:]]+10074[[:space:]]+<func><br>
+<br>
+.* <L2>:<br>
+.*:[[:space:]]+00000013[[:space:]]+nop<br>
+#pass<br>
diff --git a/ld/testsuite/ld-riscv-elf/cv-bi-beqimm.s b/ld/testsuite/ld-riscv-elf/cv-bi-beqimm.s<br>
new file mode 100644<br>
index 00000000000..88a6b293e69<br>
--- /dev/null<br>
+++ b/ld/testsuite/ld-riscv-elf/cv-bi-beqimm.s<br>
@@ -0,0 +1,11 @@<br>
+ .option nopic<br>
+ .text<br>
+ .align 1<br>
+ .globl _start<br>
+ .type _start, @function<br>
+<br>
+func: ret<br>
+_start:<br>
+ cv.beqimm t0, -16, L2<br>
+ call func<br>
+L2: nop<br>
diff --git a/ld/testsuite/ld-riscv-elf/cv-bi-bneimm.d b/ld/testsuite/ld-riscv-elf/cv-bi-bneimm.d<br>
new file mode 100644<br>
index 00000000000..52231a14b71<br>
--- /dev/null<br>
+++ b/ld/testsuite/ld-riscv-elf/cv-bi-bneimm.d<br>
@@ -0,0 +1,21 @@<br>
+#name: bneimm relocation<br>
+#source: cv-bi-bneimm.s<br>
+#as: -march=rv32i_xcvbi<br>
+#ld: -melf32lriscv<br>
+#objdump: -dr<br>
+<br>
+.*: file format .*<br>
+<br>
+<br>
+Disassembly of section \.text:<br>
+<br>
+.* <func>:<br>
+.*:[[:space:]]+00008067[[:space:]]+ret<br>
+<br>
+.* <_start>:<br>
+.*:[[:space:]]+0102f40b[[:space:]]+cv.bneimm[[:space:]]+t0,-16,.*[[:space:]]+<L2><br>
+.*:[[:space:]]+ff9ff0ef[[:space:]]+jal[[:space:]]+10074[[:space:]]+<func><br>
+<br>
+.* <L2>:<br>
+.*:[[:space:]]+00000013[[:space:]]+nop<br>
+#pass<br>
diff --git a/ld/testsuite/ld-riscv-elf/cv-bi-bneimm.s b/ld/testsuite/ld-riscv-elf/cv-bi-bneimm.s<br>
new file mode 100644<br>
index 00000000000..0f514f02e1b<br>
--- /dev/null<br>
+++ b/ld/testsuite/ld-riscv-elf/cv-bi-bneimm.s<br>
@@ -0,0 +1,11 @@<br>
+ .option nopic<br>
+ .text<br>
+ .align 1<br>
+ .globl _start<br>
+ .type _start, @function<br>
+<br>
+func: ret<br>
+_start:<br>
+ cv.bneimm t0, -16, L2<br>
+ call func<br>
+L2: nop<br>
diff --git a/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp b/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp<br>
index 7e1281d826b..b9b415a1088 100644<br>
--- a/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp<br>
+++ b/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp<br>
@@ -173,6 +173,8 @@ if [istarget "riscv*-*-*"] {<br>
run_dump_test "attr-phdr"<br>
run_dump_test "relax-max-align-gp"<br>
run_dump_test "uleb128"<br>
+ run_dump_test "cv-bi-bneimm"<br>
+ run_dump_test "cv-bi-beqimm"<br>
run_dump_test "pr31179"<br>
run_dump_test "pr31179-r"<br>
run_ld_link_tests [list \<br>
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c<br>
index 3019b9a5130..57497c6f8dd 100644<br>
--- a/opcodes/riscv-dis.c<br>
+++ b/opcodes/riscv-dis.c<br>
@@ -720,6 +720,10 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info<br>
print (info->stream, dis_style_immediate, "%d",<br>
((int) EXTRACT_CV_IS3_UIMM5 (l)));<br>
break;<br>
+ case '4':<br>
+ print (info->stream, dis_style_immediate, "%d",<br>
+ ((int) EXTRACT_CV_BI_IMM5 (l)));<br>
+ break;<br>
default:<br>
goto undefined_modifier;<br>
}<br>
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c<br>
index 5941621f25d..301f9dad216 100644<br>
--- a/opcodes/riscv-opc.c<br>
+++ b/opcodes/riscv-opc.c<br>
@@ -2115,6 +2115,10 @@ const struct riscv_opcode riscv_opcodes[] =<br>
/* Vendor-specific (CORE-V) Xcvelw instructions. */<br>
{"cv.elw", 0, INSN_CLASS_XCVELW, "d,o(s)", MATCH_CV_ELW, MASK_CV_ELW, match_opcode, 0},<br>
<br>
+/* Vendor-specific (CORE-V) Xcvbi instructions. */<br>
+{"cv.beqimm", 0, INSN_CLASS_XCVBI, "s,Xc4,p", MATCH_CV_BEQIMM, MASK_CV_BEQIMM, match_opcode, 0},<br>
+{"cv.bneimm", 0, INSN_CLASS_XCVBI, "s,Xc4,p", MATCH_CV_BNEIMM, MASK_CV_BNEIMM, match_opcode, 0},<br>
+<br>
/* Vendor-specific (T-Head) XTheadBa instructions. */<br>
{"th.addsl", 0, INSN_CLASS_XTHEADBA, "d,s,t,Xtu2@25", MATCH_TH_ADDSL, MASK_TH_ADDSL, match_opcode, 0},<br>
<br>
-- <br>
2.34.1<br>
<br>
</blockquote></div></div>