diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 19a5d49d09067c85aed55739e219cd2259e31f5b..087f88ef173cd7a6167d5e5ce578036efe933c64 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -9144,6 +9144,7 @@ static const struct aarch64_arch_option_table aarch64_archs[] = {
   {"armv8.6-a", AARCH64_ARCH_V8_6},
   {"armv8.7-a", AARCH64_ARCH_V8_7},
   {"armv8-r",	AARCH64_ARCH_V8_R},
+  {"armv9-a",	AARCH64_ARCH_V9},
   {NULL, AARCH64_ARCH_NONE}
 };
 
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 79dce2f74074e7cd3502cb127d87f585b048dfaa..c49e0a4ee1cd736fd601e47d150b5cbb05b6f219 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -107,7 +107,8 @@ issue an error message if an attempt is made to assemble an
 instruction which will not execute on the target architecture.  The
 following architecture names are recognized: @code{armv8-a},
 @code{armv8.1-a}, @code{armv8.2-a}, @code{armv8.3-a}, @code{armv8.4-a}
-@code{armv8.5-a}, @code{armv8.6-a}, @code{armv8.7-a}, and @code{armv8-r}.
+@code{armv8.5-a}, @code{armv8.6-a}, @code{armv8.7-a}, @code{armv8-r}, and
+@code{armv9-a}.
 
 If both @option{-mcpu} and @option{-march} are specified, the
 assembler will use the setting for @option{-mcpu}.  If neither are
@@ -196,7 +197,7 @@ automatically cause those extensions to be disabled.
  @tab Enable ARMv8.1 Advanced SIMD extensions.  This implies @code{simd}.
 @item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
  @tab Enable Advanced SIMD extensions.  This implies @code{fp}.
-@item @code{sve} @tab ARMv8.2-A @tab No
+@item @code{sve} @tab ARMv8.2-A @tab Armv9-A or later
  @tab Enable the Scalable Vector Extensions.  This implies @code{fp16},
  @code{simd} and @code{compnum}.
 @item @code{dotprod} @tab ARMv8.2-A @tab ARMv8.4-A or later
@@ -216,7 +217,7 @@ automatically cause those extensions to be disabled.
  @tab Enable ARMv8.5-A Memory Tagging Extensions.
 @item @code{tme} @tab ARMv8-A @tab No
  @tab Enable Transactional Memory Extensions.
-@item @code{sve2} @tab ARMv8-A @tab No
+@item @code{sve2} @tab ARMv8-A @tab Armv9-A or later
  @tab Enable the SVE2 Extension.
 @item @code{sve2-bitperm} @tab ARMv8-A @tab No
  @tab Enable SVE2 BITPERM Extension.
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 2bbd593c36ec4f21cddb62b7d400ee87d2a797d3..420b211de6ea88dbab35b4f6f9dcab8f08bf946d 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -90,6 +90,7 @@ typedef uint32_t aarch64_insn;
 #define AARCH64_FEATURE_F32MM	     (1ULL << 53)
 #define AARCH64_FEATURE_F64MM	     (1ULL << 54)
 #define AARCH64_FEATURE_FLAGM	     (1ULL << 55) /* v8.4 Flag Manipulation.  */
+#define AARCH64_FEATURE_V9	     (1ULL << 56) /* Armv9.0-A processors.  */
 
 /* Crypto instructions are the combination of AES and SHA2.  */
 #define AARCH64_FEATURE_CRYPTO	(AARCH64_FEATURE_SHA2 | AARCH64_FEATURE_AES)
@@ -140,6 +141,10 @@ typedef uint32_t aarch64_insn;
 #define AARCH64_ARCH_V8_R	(AARCH64_FEATURE (AARCH64_ARCH_V8_4,	\
 						 AARCH64_FEATURE_V8_R)	\
 			      & ~(AARCH64_FEATURE_V8_A | AARCH64_FEATURE_LOR))
+#define AARCH64_ARCH_V9		AARCH64_FEATURE (AARCH64_ARCH_V8_5,	\
+						 AARCH64_FEATURE_SVE   \
+						 | AARCH64_FEATURE_SVE2 \
+						 | AARCH64_FEATURE_V9)
 
 #define AARCH64_ARCH_NONE	AARCH64_FEATURE (0, 0)
 #define AARCH64_ANY		AARCH64_FEATURE (-1, 0)	/* Any basic core.  */