diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 6f782d057f844a79aaca183e21f2fbd49b546019..e852e38dfb4ded14b0ce0f9f451e5c417b47121c 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -7020,18 +7020,49 @@ warn_unpredictable_ldst (aarch64_instruction *instr, char *str)
       break;
 
     case ldstexcl:
-      /* It is unpredictable if the destination and status registers are the
-	 same.  */
       if ((aarch64_get_operand_class (opnds[0].type)
 	   == AARCH64_OPND_CLASS_INT_REG)
 	  && (aarch64_get_operand_class (opnds[1].type)
-	      == AARCH64_OPND_CLASS_INT_REG)
-	  && (opnds[0].reg.regno == opnds[1].reg.regno
-	      || opnds[0].reg.regno == opnds[2].reg.regno))
-	as_warn (_("unpredictable: identical transfer and status registers"
-		   " --`%s'"),
-		 str);
+	      == AARCH64_OPND_CLASS_INT_REG))
+	{
+          if ((opcode->opcode & (1 << 22)))
+	    {
+	      /* It is unpredictable if load-exclusive pair with Rt == Rt2.  */
+	      if ((opcode->opcode & (1 << 21))
+		  && opnds[0].reg.regno == opnds[1].reg.regno)
+		as_warn (_("unpredictable load of register pair -- `%s'"), str);
+	    }
+	  else
+	    {
+	      /*  Store-Exclusive is unpredictable if Rt == Rs.  */
+	      if (opnds[0].reg.regno == opnds[1].reg.regno)
+		as_warn
+		  (_("unpredictable: identical transfer and status registers"
+		     " --`%s'"),str);
 
+	      if (opnds[0].reg.regno == opnds[2].reg.regno)
+		{
+		  if (!(opcode->opcode & (1 << 21)))
+	            /*  Store-Exclusive is unpredictable if Rn == Rs.  */
+		    as_warn
+		      (_("unpredictable: identical base and status registers"
+			 " --`%s'"),str);
+		  else
+	            /*  Store-Exclusive pair is unpredictable if Rt2 == Rs.  */
+		    as_warn
+		      (_("unpredictable: "
+			 "identical transfer and status registers"
+			 " --`%s'"),str);
+		}
+
+	      /* Store-Exclusive pair is unpredictable if Rn == Rs.  */
+	      if ((opcode->opcode & (1 << 21))
+		  && opnds[0].reg.regno == opnds[3].reg.regno
+		  && opnds[3].reg.regno != REG_SP)
+		as_warn (_("unpredictable: identical base and status registers"
+			   " --`%s'"),str);
+	    }
+	}
       break;
 
     default:
diff --git a/gas/testsuite/gas/aarch64/diagnostic.l b/gas/testsuite/gas/aarch64/diagnostic.l
index b5f304af70b35da0e488fe363eab9d040d5b95d5..5158d41cd43b3706c78be45ff958850dbafa02e8 100644
--- a/gas/testsuite/gas/aarch64/diagnostic.l
+++ b/gas/testsuite/gas/aarch64/diagnostic.l
@@ -175,11 +175,11 @@
 [^:]*:304: Warning: unpredictable: identical transfer and status registers --`stlxrb w26,w26,\[x0\]'
 [^:]*:305: Warning: unpredictable: identical transfer and status registers --`stlxrh w26,w26,\[x1\]'
 [^:]*:306: Warning: unpredictable: identical transfer and status registers --`stlxr w26,w26,\[x2\]'
-[^:]*:307: Warning: unpredictable: identical transfer and status registers --`stlxrb w26,w27,\[x26\]'
-[^:]*:308: Warning: unpredictable: identical transfer and status registers --`stlxrh w26,w27,\[x26\]'
-[^:]*:309: Warning: unpredictable: identical transfer and status registers --`stlxr w26,w27,\[x26\]'
-[^:]*:310: Warning: unpredictable: identical transfer and status registers --`stlxr w26,x27,\[x26\]'
+[^:]*:307: Warning: unpredictable: identical base and status registers --`stlxrb w26,w27,\[x26\]'
+[^:]*:308: Warning: unpredictable: identical base and status registers --`stlxrh w26,w27,\[x26\]'
+[^:]*:309: Warning: unpredictable: identical base and status registers --`stlxr w26,w27,\[x26\]'
+[^:]*:310: Warning: unpredictable: identical base and status registers --`stlxr w26,x27,\[x26\]'
 [^:]*:311: Warning: unpredictable: identical transfer and status registers --`stlxr w26,x26,\[x3\]'
-[^:]*:312: Warning: unpredictable: identical transfer and status registers --`ldxp x26,x26,\[x5\]'
-[^:]*:313: Warning: unpredictable: identical transfer and status registers --`ldxp x26,x1,\[x26\]'
+[^:]*:312: Warning: unpredictable load of register pair -- `ldxp x26,x26,\[x5\]'
 [^:]*:314: Error: expected element type rather than vector type at operand 1 -- `st4 {v0\.16b-v3\.16b}\[4\],\[x0\]'
+[^:]*:315: Warning: unpredictable: identical base and status registers --`stlxp w3,w26,w26,\[x3\]'
diff --git a/gas/testsuite/gas/aarch64/diagnostic.s b/gas/testsuite/gas/aarch64/diagnostic.s
index 21cbc53d8972bdf542a8c2088729af1591973cf1..0ebe85ac59d709e2f9253c0656cbd4cf3a6ea2d4 100644
--- a/gas/testsuite/gas/aarch64/diagnostic.s
+++ b/gas/testsuite/gas/aarch64/diagnostic.s
@@ -312,3 +312,4 @@
 	ldxp	x26, x26, [x5]
 	ldxp	x26, x1, [x26]
 	st4	{v0.16b-v3.16b}[4], [x0]
+	stlxp	w3, w26, w26, [x3]