From 004a2566602fd610e43032cc91f981b3c9467555 Mon Sep 17 00:00:00 2001 From: "Cui,Lili" Date: Thu, 15 Oct 2020 10:45:08 +0800 Subject: [PATCH] Enhancement for avx-vnni patch 1. Rename CpuVEX_PREFIX to PseudoVexPrefix and move it from cpu_flags to opcode_modifiers. 2. Delete {vex2} invalid test. 3. Use VexW0 and VexVVVV in the AVX-VNNI instructions. gas/ * config/tc-i386.c: Move Pseudo Prefix check to match_template. * testsuite/gas/i386/avx-vnni-inval.l: New file. * testsuite/gas/i386/avx-vnni-inval.s: Likewise. * testsuite/gas/i386/avx-vnni.d: Delete invalid {vex2} test. * testsuite/gas/i386/avx-vnni.s: Likewise. * testsuite/gas/i386/i386.exp: Add AVX VNNI invalid tests. * testsuite/gas/i386/x86-64-avx-vnni-inval.l: New file. * testsuite/gas/i386/x86-64-avx-vnni-inval.s: Likewise. * testsuite/gas/i386/x86-64-avx-vnni.d: Delete invalid {vex2} test. * testsuite/gas/i386/x86-64-avx-vnni.s: Likewise. opcodes/ * i386-opc.tbl: Rename CpuVEX_PREFIX to PseudoVexPrefix and move it from cpu_flags to opcode_modifiers. Use VexW0 and VexVVVV in the AVX-VNNI instructions. * i386-gen.c: Likewise. * i386-opc.h: Likewise. * i386-opc.h: Likewise. * i386-init.h: Regenerated. * i386-tbl.h: Likewise. --- gas/config/tc-i386.c | 16 ++++++++-------- gas/testsuite/gas/i386/avx-vnni-inval.l | 3 +++ gas/testsuite/gas/i386/avx-vnni-inval.s | 9 +++++++++ gas/testsuite/gas/i386/avx-vnni.d | 8 -------- gas/testsuite/gas/i386/avx-vnni.s | 2 -- gas/testsuite/gas/i386/i386.exp | 2 ++ gas/testsuite/gas/i386/x86-64-avx-vnni-inval.l | 5 +++++ gas/testsuite/gas/i386/x86-64-avx-vnni-inval.s | 11 +++++++++++ gas/testsuite/gas/i386/x86-64-avx-vnni.d | 8 -------- gas/testsuite/gas/i386/x86-64-avx-vnni.s | 2 -- opcodes/i386-gen.c | 4 ++-- opcodes/i386-opc.h | 6 +++--- opcodes/i386-opc.tbl | 8 ++++---- 13 files changed, 47 insertions(+), 37 deletions(-) create mode 100644 gas/testsuite/gas/i386/avx-vnni-inval.l create mode 100644 gas/testsuite/gas/i386/avx-vnni-inval.s create mode 100644 gas/testsuite/gas/i386/x86-64-avx-vnni-inval.l create mode 100644 gas/testsuite/gas/i386/x86-64-avx-vnni-inval.s diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index a081064aba..487454f24a 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -1973,14 +1973,7 @@ cpu_flags_match (const insn_template *t) cpu = cpu_flags_and (x, cpu); if (!cpu_flags_all_zero (&cpu)) { - if (x.bitfield.cpuvex_prefix) - { - /* We need to check a few extra flags with VEX_PREFIX. */ - if (i.vec_encoding == vex_encoding_vex - || i.vec_encoding == vex_encoding_vex3) - match |= CPU_FLAGS_ARCH_MATCH; - } - else if (x.bitfield.cpuavx) + if (x.bitfield.cpuavx) { /* We need to check a few extra flags with AVX. */ if (cpu.bitfield.cpuavx @@ -6265,6 +6258,13 @@ match_template (char mnem_suffix) if (cpu_flags_match (t) != CPU_FLAGS_PERFECT_MATCH) continue; + /* Check Pseudo Prefix. */ + i.error = unsupported; + if (t->opcode_modifier.pseudovexprefix + && !(i.vec_encoding == vex_encoding_vex + || i.vec_encoding == vex_encoding_vex3)) + continue; + /* Check AT&T mnemonic. */ i.error = unsupported_with_intel_mnemonic; if (intel_mnemonic && t->opcode_modifier.attmnemonic) diff --git a/gas/testsuite/gas/i386/avx-vnni-inval.l b/gas/testsuite/gas/i386/avx-vnni-inval.l new file mode 100644 index 0000000000..972f31f082 --- /dev/null +++ b/gas/testsuite/gas/i386/avx-vnni-inval.l @@ -0,0 +1,3 @@ +.* Assembler messages: +.*:6: Error: unsupported instruction `vpdpbusd' +.*:9: Error: unsupported instruction `vpdpbusd' diff --git a/gas/testsuite/gas/i386/avx-vnni-inval.s b/gas/testsuite/gas/i386/avx-vnni-inval.s new file mode 100644 index 0000000000..2b4cf0bf9b --- /dev/null +++ b/gas/testsuite/gas/i386/avx-vnni-inval.s @@ -0,0 +1,9 @@ +# Check illegal in AVXVNNI instructions + + .text + .arch .noavx512_vnni +_start: + vpdpbusd %xmm2,%xmm4,%xmm2 + + .intel_syntax noprefix + vpdpbusd %xmm2,%xmm4,%xmm2 diff --git a/gas/testsuite/gas/i386/avx-vnni.d b/gas/testsuite/gas/i386/avx-vnni.d index 6d6e779d6e..6e31528cf2 100644 --- a/gas/testsuite/gas/i386/avx-vnni.d +++ b/gas/testsuite/gas/i386/avx-vnni.d @@ -11,32 +11,24 @@ Disassembly of section .text: +[a-f0-9]+: 62 f2 5d 08 50 d2 vpdpbusd %xmm2,%xmm4,%xmm2 +[a-f0-9]+: c4 e2 59 50 d2 \{vex3\} vpdpbusd %xmm2,%xmm4,%xmm2 +[a-f0-9]+: c4 e2 59 50 d2 \{vex3\} vpdpbusd %xmm2,%xmm4,%xmm2 - +[a-f0-9]+: c4 e2 59 50 d2 \{vex3\} vpdpbusd %xmm2,%xmm4,%xmm2 - +[a-f0-9]+: c4 e2 59 50 11 \{vex3\} vpdpbusd \(%ecx\),%xmm4,%xmm2 +[a-f0-9]+: c4 e2 59 50 11 \{vex3\} vpdpbusd \(%ecx\),%xmm4,%xmm2 +[a-f0-9]+: c4 e2 59 50 11 \{vex3\} vpdpbusd \(%ecx\),%xmm4,%xmm2 +[a-f0-9]+: 62 f2 5d 08 52 d2 vpdpwssd %xmm2,%xmm4,%xmm2 +[a-f0-9]+: 62 f2 5d 08 52 d2 vpdpwssd %xmm2,%xmm4,%xmm2 +[a-f0-9]+: c4 e2 59 52 d2 \{vex3\} vpdpwssd %xmm2,%xmm4,%xmm2 +[a-f0-9]+: c4 e2 59 52 d2 \{vex3\} vpdpwssd %xmm2,%xmm4,%xmm2 - +[a-f0-9]+: c4 e2 59 52 d2 \{vex3\} vpdpwssd %xmm2,%xmm4,%xmm2 - +[a-f0-9]+: c4 e2 59 52 11 \{vex3\} vpdpwssd \(%ecx\),%xmm4,%xmm2 +[a-f0-9]+: c4 e2 59 52 11 \{vex3\} vpdpwssd \(%ecx\),%xmm4,%xmm2 +[a-f0-9]+: c4 e2 59 52 11 \{vex3\} vpdpwssd \(%ecx\),%xmm4,%xmm2 +[a-f0-9]+: 62 f2 5d 08 51 d2 vpdpbusds %xmm2,%xmm4,%xmm2 +[a-f0-9]+: 62 f2 5d 08 51 d2 vpdpbusds %xmm2,%xmm4,%xmm2 +[a-f0-9]+: c4 e2 59 51 d2 \{vex3\} vpdpbusds %xmm2,%xmm4,%xmm2 +[a-f0-9]+: c4 e2 59 51 d2 \{vex3\} vpdpbusds %xmm2,%xmm4,%xmm2 - +[a-f0-9]+: c4 e2 59 51 d2 \{vex3\} vpdpbusds %xmm2,%xmm4,%xmm2 - +[a-f0-9]+: c4 e2 59 51 11 \{vex3\} vpdpbusds \(%ecx\),%xmm4,%xmm2 +[a-f0-9]+: c4 e2 59 51 11 \{vex3\} vpdpbusds \(%ecx\),%xmm4,%xmm2 +[a-f0-9]+: c4 e2 59 51 11 \{vex3\} vpdpbusds \(%ecx\),%xmm4,%xmm2 +[a-f0-9]+: 62 f2 5d 08 53 d2 vpdpwssds %xmm2,%xmm4,%xmm2 +[a-f0-9]+: 62 f2 5d 08 53 d2 vpdpwssds %xmm2,%xmm4,%xmm2 +[a-f0-9]+: c4 e2 59 53 d2 \{vex3\} vpdpwssds %xmm2,%xmm4,%xmm2 +[a-f0-9]+: c4 e2 59 53 d2 \{vex3\} vpdpwssds %xmm2,%xmm4,%xmm2 - +[a-f0-9]+: c4 e2 59 53 d2 \{vex3\} vpdpwssds %xmm2,%xmm4,%xmm2 - +[a-f0-9]+: c4 e2 59 53 11 \{vex3\} vpdpwssds \(%ecx\),%xmm4,%xmm2 +[a-f0-9]+: c4 e2 59 53 11 \{vex3\} vpdpwssds \(%ecx\),%xmm4,%xmm2 +[a-f0-9]+: c4 e2 59 53 11 \{vex3\} vpdpwssds \(%ecx\),%xmm4,%xmm2 +[a-f0-9]+: 62 f2 5d 08 50 d2 vpdpbusd %xmm2,%xmm4,%xmm2 diff --git a/gas/testsuite/gas/i386/avx-vnni.s b/gas/testsuite/gas/i386/avx-vnni.s index 4ddc733040..b37bc85c3a 100644 --- a/gas/testsuite/gas/i386/avx-vnni.s +++ b/gas/testsuite/gas/i386/avx-vnni.s @@ -4,10 +4,8 @@ \mnemonic %xmm2, %xmm4, %xmm2 {evex} \mnemonic %xmm2, %xmm4, %xmm2 {vex} \mnemonic %xmm2, %xmm4, %xmm2 - {vex2} \mnemonic %xmm2, %xmm4, %xmm2 {vex3} \mnemonic %xmm2, %xmm4, %xmm2 {vex} \mnemonic (%ecx), %xmm4, %xmm2 - {vex2} \mnemonic (%ecx), %xmm4, %xmm2 {vex3} \mnemonic (%ecx), %xmm4, %xmm2 .endm diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index f5727678e2..068813d77f 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -459,6 +459,7 @@ if [gas_32_check] then { run_dump_test "avx512_bf16_vl" run_list_test "avx512_bf16_vl-inval" run_dump_test "avx-vnni" + run_list_test "avx-vnni-inval" run_list_test "sg" run_dump_test "clzero" run_dump_test "disassem" @@ -1077,6 +1078,7 @@ if [gas_64_check] then { run_dump_test "x86-64-avx512_bf16_vl" run_list_test "x86-64-avx512_bf16_vl-inval" run_dump_test "x86-64-avx-vnni" + run_list_test "x86-64-avx-vnni-inval" run_dump_test "x86-64-clzero" run_dump_test "x86-64-mwaitx-bdver4" run_list_test "x86-64-mwaitx-reg" diff --git a/gas/testsuite/gas/i386/x86-64-avx-vnni-inval.l b/gas/testsuite/gas/i386/x86-64-avx-vnni-inval.l new file mode 100644 index 0000000000..e05764d95f --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-avx-vnni-inval.l @@ -0,0 +1,5 @@ +.* Assembler messages: +.*:6: Error: unsupported instruction `vpdpbusds' +.*:7: Error: unsupported instruction `vpdpbusds' +.*:10: Error: unsupported instruction `vpdpbusds' +.*:11: Error: unsupported instruction `vpdpbusds' diff --git a/gas/testsuite/gas/i386/x86-64-avx-vnni-inval.s b/gas/testsuite/gas/i386/x86-64-avx-vnni-inval.s new file mode 100644 index 0000000000..8d165bc0f0 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-avx-vnni-inval.s @@ -0,0 +1,11 @@ +# Check illegal in AVXVNNI instructions + + .text + .arch .noavx512_vnni +_start: + vpdpbusds %xmm2, %xmm4, %xmm2 + vpdpbusds %xmm22, %xmm4, %xmm2 + + .intel_syntax noprefix + vpdpbusds xmm2, xmm4, xmm2 + vpdpbusds xmm2, xmm4, xmm22 diff --git a/gas/testsuite/gas/i386/x86-64-avx-vnni.d b/gas/testsuite/gas/i386/x86-64-avx-vnni.d index ebb0ebf02c..c4474739ed 100644 --- a/gas/testsuite/gas/i386/x86-64-avx-vnni.d +++ b/gas/testsuite/gas/i386/x86-64-avx-vnni.d @@ -11,8 +11,6 @@ Disassembly of section .text: +[a-f0-9]+: 62 d2 5d 08 50 d4 vpdpbusd %xmm12,%xmm4,%xmm2 +[a-f0-9]+: c4 c2 59 50 d4 \{vex3\} vpdpbusd %xmm12,%xmm4,%xmm2 +[a-f0-9]+: c4 c2 59 50 d4 \{vex3\} vpdpbusd %xmm12,%xmm4,%xmm2 - +[a-f0-9]+: c4 c2 59 50 d4 \{vex3\} vpdpbusd %xmm12,%xmm4,%xmm2 - +[a-f0-9]+: c4 e2 59 50 11 \{vex3\} vpdpbusd \(%rcx\),%xmm4,%xmm2 +[a-f0-9]+: c4 e2 59 50 11 \{vex3\} vpdpbusd \(%rcx\),%xmm4,%xmm2 +[a-f0-9]+: c4 e2 59 50 11 \{vex3\} vpdpbusd \(%rcx\),%xmm4,%xmm2 +[a-f0-9]+: 62 b2 5d 08 50 d6 vpdpbusd %xmm22,%xmm4,%xmm2 @@ -20,8 +18,6 @@ Disassembly of section .text: +[a-f0-9]+: 62 d2 5d 08 52 d4 vpdpwssd %xmm12,%xmm4,%xmm2 +[a-f0-9]+: c4 c2 59 52 d4 \{vex3\} vpdpwssd %xmm12,%xmm4,%xmm2 +[a-f0-9]+: c4 c2 59 52 d4 \{vex3\} vpdpwssd %xmm12,%xmm4,%xmm2 - +[a-f0-9]+: c4 c2 59 52 d4 \{vex3\} vpdpwssd %xmm12,%xmm4,%xmm2 - +[a-f0-9]+: c4 e2 59 52 11 \{vex3\} vpdpwssd \(%rcx\),%xmm4,%xmm2 +[a-f0-9]+: c4 e2 59 52 11 \{vex3\} vpdpwssd \(%rcx\),%xmm4,%xmm2 +[a-f0-9]+: c4 e2 59 52 11 \{vex3\} vpdpwssd \(%rcx\),%xmm4,%xmm2 +[a-f0-9]+: 62 b2 5d 08 52 d6 vpdpwssd %xmm22,%xmm4,%xmm2 @@ -29,8 +25,6 @@ Disassembly of section .text: +[a-f0-9]+: 62 d2 5d 08 51 d4 vpdpbusds %xmm12,%xmm4,%xmm2 +[a-f0-9]+: c4 c2 59 51 d4 \{vex3\} vpdpbusds %xmm12,%xmm4,%xmm2 +[a-f0-9]+: c4 c2 59 51 d4 \{vex3\} vpdpbusds %xmm12,%xmm4,%xmm2 - +[a-f0-9]+: c4 c2 59 51 d4 \{vex3\} vpdpbusds %xmm12,%xmm4,%xmm2 - +[a-f0-9]+: c4 e2 59 51 11 \{vex3\} vpdpbusds \(%rcx\),%xmm4,%xmm2 +[a-f0-9]+: c4 e2 59 51 11 \{vex3\} vpdpbusds \(%rcx\),%xmm4,%xmm2 +[a-f0-9]+: c4 e2 59 51 11 \{vex3\} vpdpbusds \(%rcx\),%xmm4,%xmm2 +[a-f0-9]+: 62 b2 5d 08 51 d6 vpdpbusds %xmm22,%xmm4,%xmm2 @@ -38,8 +32,6 @@ Disassembly of section .text: +[a-f0-9]+: 62 d2 5d 08 53 d4 vpdpwssds %xmm12,%xmm4,%xmm2 +[a-f0-9]+: c4 c2 59 53 d4 \{vex3\} vpdpwssds %xmm12,%xmm4,%xmm2 +[a-f0-9]+: c4 c2 59 53 d4 \{vex3\} vpdpwssds %xmm12,%xmm4,%xmm2 - +[a-f0-9]+: c4 c2 59 53 d4 \{vex3\} vpdpwssds %xmm12,%xmm4,%xmm2 - +[a-f0-9]+: c4 e2 59 53 11 \{vex3\} vpdpwssds \(%rcx\),%xmm4,%xmm2 +[a-f0-9]+: c4 e2 59 53 11 \{vex3\} vpdpwssds \(%rcx\),%xmm4,%xmm2 +[a-f0-9]+: c4 e2 59 53 11 \{vex3\} vpdpwssds \(%rcx\),%xmm4,%xmm2 +[a-f0-9]+: 62 b2 5d 08 53 d6 vpdpwssds %xmm22,%xmm4,%xmm2 diff --git a/gas/testsuite/gas/i386/x86-64-avx-vnni.s b/gas/testsuite/gas/i386/x86-64-avx-vnni.s index 7f47bf684b..95b6dc2ef3 100644 --- a/gas/testsuite/gas/i386/x86-64-avx-vnni.s +++ b/gas/testsuite/gas/i386/x86-64-avx-vnni.s @@ -4,10 +4,8 @@ \mnemonic %xmm12, %xmm4, %xmm2 {evex} \mnemonic %xmm12, %xmm4, %xmm2 {vex} \mnemonic %xmm12, %xmm4, %xmm2 - {vex2} \mnemonic %xmm12, %xmm4, %xmm2 {vex3} \mnemonic %xmm12, %xmm4, %xmm2 {vex} \mnemonic (%rcx), %xmm4, %xmm2 - {vex2} \mnemonic (%rcx), %xmm4, %xmm2 {vex3} \mnemonic (%rcx), %xmm4, %xmm2 \mnemonic %xmm22, %xmm4, %xmm2 .endm diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index fc42088638..c3f0181329 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -408,7 +408,7 @@ static initializer cpu_flag_init[] = { "CPU_ANY_AMX_TILE_FLAGS", "CpuAMX_TILE|CpuAMX_INT8|CpuAMX_BF16" }, { "CPU_ANY_AVX_VNNI_FLAGS", - "CpuAVX_VNNI|CpuVEX_PREFIX" }, + "CpuAVX_VNNI" }, { "CPU_ANY_MOVDIRI_FLAGS", "CpuMOVDIRI" }, { "CPU_ANY_UINTR_FLAGS", @@ -637,7 +637,6 @@ static bitfield cpu_flags[] = BITFIELD (CpuAVX512_VP2INTERSECT), BITFIELD (CpuTDX), BITFIELD (CpuAVX_VNNI), - BITFIELD (CpuVEX_PREFIX), BITFIELD (CpuMWAITX), BITFIELD (CpuCLZERO), BITFIELD (CpuOSPKE), @@ -708,6 +707,7 @@ static bitfield opcode_modifiers[] = BITFIELD (ImmExt), BITFIELD (NoRex64), BITFIELD (Ugh), + BITFIELD (PseudoVexPrefix), BITFIELD (Vex), BITFIELD (VexVVVV), BITFIELD (VexW), diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index 2e90c58421..ce2a1a5b47 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -214,8 +214,6 @@ enum CpuTDX, /* Intel AVX VNNI Instructions support required. */ CpuAVX_VNNI, - /* Intel AVX Instructions support via {vex} prefix required. */ - CpuVEX_PREFIX, /* mwaitx instruction required */ CpuMWAITX, /* Clzero instruction required */ @@ -387,7 +385,6 @@ typedef union i386_cpu_flags unsigned int cpuavx512_vp2intersect:1; unsigned int cputdx:1; unsigned int cpuavx_vnni:1; - unsigned int cpuvex_prefix:1; unsigned int cpumwaitx:1; unsigned int cpuclzero:1; unsigned int cpuospke:1; @@ -534,6 +531,8 @@ enum NoRex64, /* deprecated fp insn, gets a warning */ Ugh, + /* Intel AVX Instructions support via {vex} prefix */ + PseudoVexPrefix, /* insn has VEX prefix: 1: 128bit VEX prefix (or operand dependent). 2: 256bit VEX prefix. @@ -739,6 +738,7 @@ typedef struct i386_opcode_modifier unsigned int immext:1; unsigned int norex64:1; unsigned int ugh:1; + unsigned int pseudovexprefix:1; unsigned int vex:2; unsigned int vexvvvv:2; unsigned int vexw:2; diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 6745eff26c..56c2838991 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -3906,11 +3906,11 @@ vpshrdw, 4, 0x6672, None, 1, CpuAVX512_VBMI2, Modrm|Masking=3|OpcodePrefix=2|Vex // AVX_VNNI instructions -vpdpbusd, 3, 0x6650, None, 1, CpuAVX_VNNI|CpuVEX_PREFIX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpdpwssd, 3, 0x6652, None, 1, CpuAVX_VNNI|CpuVEX_PREFIX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpdpbusd, 3, 0x6650, None, 1, CpuAVX_VNNI, Modrm|Vex|PseudoVexPrefix|OpcodePrefix=1|VexVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpdpwssd, 3, 0x6652, None, 1, CpuAVX_VNNI, Modrm|Vex|PseudoVexPrefix|OpcodePrefix=1|VexVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpdpbusds, 3, 0x6651, None, 1, CpuAVX_VNNI|CpuVEX_PREFIX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpdpwssds, 3, 0x6653, None, 1, CpuAVX_VNNI|CpuVEX_PREFIX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpdpbusds, 3, 0x6651, None, 1, CpuAVX_VNNI, Modrm|Vex|PseudoVexPrefix|OpcodePrefix=1|VexVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpdpwssds, 3, 0x6653, None, 1, CpuAVX_VNNI, Modrm|Vex|PseudoVexPrefix|OpcodePrefix=1|VexVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } // AVX_VNNI instructions end -- 2.17.1