From 973aad74607092cbc78e473aa2222d26b92fba87 Mon Sep 17 00:00:00 2001 From: Ganesh Gopalasubramanian Date: Thu, 15 Oct 2020 01:06:21 +0530 Subject: [PATCH] Add AMD znver3 processor support --- gas/config/tc-i386.c | 2 ++ gas/doc/c-i386.texi | 11 ++++-- gas/testsuite/gas/i386/arch-14-znver3.d | 5 +++ gas/testsuite/gas/i386/arch-14.d | 17 ++++++++++ gas/testsuite/gas/i386/arch-14.s | 15 ++++++++ gas/testsuite/gas/i386/i386.exp | 7 ++++ gas/testsuite/gas/i386/invlpgb.d | 11 ++++++ gas/testsuite/gas/i386/invlpgb.s | 5 +++ gas/testsuite/gas/i386/snp.d | 14 ++++++++ gas/testsuite/gas/i386/snp.s | 8 +++++ gas/testsuite/gas/i386/tlbsync.d | 11 ++++++ gas/testsuite/gas/i386/tlbsync.s | 5 +++ gas/testsuite/gas/i386/x86-64-arch-4-znver3.d | 5 +++ gas/testsuite/gas/i386/x86-64-arch-4.d | 33 ++++++++++++++++++ gas/testsuite/gas/i386/x86-64-arch-4.s | 34 +++++++++++++++++++ opcodes/i386-dis.c | 20 +++++++++++ opcodes/i386-gen.c | 11 ++++++ opcodes/i386-opc.h | 9 +++++ opcodes/i386-opc.tbl | 21 ++++++++++++ 19 files changed, 241 insertions(+), 3 deletions(-) create mode 100644 gas/testsuite/gas/i386/arch-14-znver3.d create mode 100644 gas/testsuite/gas/i386/arch-14.d create mode 100644 gas/testsuite/gas/i386/arch-14.s create mode 100644 gas/testsuite/gas/i386/invlpgb.d create mode 100644 gas/testsuite/gas/i386/invlpgb.s create mode 100644 gas/testsuite/gas/i386/snp.d create mode 100644 gas/testsuite/gas/i386/snp.s create mode 100644 gas/testsuite/gas/i386/tlbsync.d create mode 100644 gas/testsuite/gas/i386/tlbsync.s create mode 100644 gas/testsuite/gas/i386/x86-64-arch-4-znver3.d create mode 100644 gas/testsuite/gas/i386/x86-64-arch-4.d create mode 100644 gas/testsuite/gas/i386/x86-64-arch-4.s diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index a081064aba..d46dc1f335 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -1014,6 +1014,8 @@ static const arch_entry cpu_arch[] = CPU_ZNVER1_FLAGS, 0 }, { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER, CPU_ZNVER2_FLAGS, 0 }, + { STRING_COMMA_LEN ("znver3"), PROCESSOR_ZNVER, + CPU_ZNVER3_FLAGS, 0 }, { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT, CPU_BTVER1_FLAGS, 0 }, { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT, diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index f9aae566bb..23eee3bc00 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -125,6 +125,7 @@ processor names are recognized: @code{bdver4}, @code{znver1}, @code{znver2}, +@code{znver3}, @code{btver1}, @code{btver2}, @code{generic32} and @@ -285,6 +286,9 @@ accept various extension mnemonics. For example, @code{3dnowa}, @code{sse4a}, @code{sse5}, +@code{snp}, +@code{invlpgb}, +@code{tlbsync}, @code{svme} and @code{padlock}. Note that rather than extending a basic instruction set, the extension @@ -1496,8 +1500,8 @@ supported on the CPU specified. The choices for @var{cpu_type} are: @item @samp{corei7} @tab @samp{l1om} @tab @samp{k1om} @tab @samp{iamcu} @item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8} @item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3} -@item @samp{bdver4} @tab @samp{znver1} @tab @samp{znver2} @tab @samp{btver1} -@item @samp{btver2} @tab @samp{generic32} @tab @samp{generic64} +@item @samp{bdver4} @tab @samp{znver1} @tab @samp{znver2} @tab @samp{znver3} +@item @samp{btver1} @tab @samp{btver2} @tab @samp{generic32} @tab @samp{generic64} @item @samp{.cmov} @tab @samp{.fxsr} @tab @samp{.mmx} @item @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3} @tab @samp{.sse4a} @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4} @@ -1526,7 +1530,8 @@ supported on the CPU specified. The choices for @var{cpu_type} are: @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16} @item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx} @tab @samp{.rdpru} -@item @samp{.mcommit} @tab @samp{.sev_es} +@item @samp{.mcommit} @tab @samp{.sev_es} @tab @samp{.snp} @tab @samp{.invlpgb} +@item @samp{.tlbsync} @end multitable Apart from the warning, there are only two other effects on diff --git a/gas/testsuite/gas/i386/arch-14-znver3.d b/gas/testsuite/gas/i386/arch-14-znver3.d new file mode 100644 index 0000000000..29686dfc27 --- /dev/null +++ b/gas/testsuite/gas/i386/arch-14-znver3.d @@ -0,0 +1,5 @@ +#source: arch-14.s +#as: -march=znver3 +#objdump: -dw +#name: i386 arch 14 (znver3) +#dump: arch-14.d diff --git a/gas/testsuite/gas/i386/arch-14.d b/gas/testsuite/gas/i386/arch-14.d new file mode 100644 index 0000000000..7875fea91f --- /dev/null +++ b/gas/testsuite/gas/i386/arch-14.d @@ -0,0 +1,17 @@ +#objdump: -dw +#name: i386 arch 14 + +.*: file format .* + +Disassembly of section .text: + +0+ <.text>: +[ ]*[0-9a-f]+:[ ]+0f 01 fe[ ]+invlpgb[ ^I]* +[ ]*[0-9a-f]+:[ ]+0f 01 ff[ ]+tlbsync[ ^I]* +[ ]*[a-f0-9]+:[ ]*f3 0f 01 ff[ ]+psmash[ ^I]* +[ ]*[a-f0-9]+:[ ]*f2 0f 01 ff[ ]+pvalidate[ ^I]* +[ ]*[a-f0-9]+:[ ]*f2 0f 01 fe[ ]+rmpupdate[ ^I]* +[ ]*[a-f0-9]+:[ ]*f3 0f 01 fe[ ]+rmpadjust[ ^I]* +[ ]*[a-f0-9]+:[ ]*0f 01 ee[ ]+rdpkru[ ^I]* +[ ]*[a-f0-9]+:[ ]*0f 01 ef[ ]+wrpkru[ ^I]* +#pass diff --git a/gas/testsuite/gas/i386/arch-14.s b/gas/testsuite/gas/i386/arch-14.s new file mode 100644 index 0000000000..b656aa15cf --- /dev/null +++ b/gas/testsuite/gas/i386/arch-14.s @@ -0,0 +1,15 @@ +# Test -march= + .text + +#INVLPGB + invlpgb +#TLBSYNC + tlbsync +#SNP - Secure Nested Paging support + psmash + pvalidate + rmpupdate + rmpadjust +#OSPKE + rdpkru + wrpkru diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index f5727678e2..88777b862e 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -183,6 +183,7 @@ if [gas_32_check] then { run_dump_test "arch-10-bdver4" run_dump_test "arch-13-znver1" run_dump_test "arch-13-znver2" + run_dump_test "arch-14-znver3" run_dump_test "arch-10-btver1" run_dump_test "arch-10-btver2" run_list_test "arch-10-1" "-march=generic32 -I${srcdir}/$subdir -al" @@ -192,6 +193,7 @@ if [gas_32_check] then { run_dump_test "arch-11" run_dump_test "arch-12" run_dump_test "arch-13" + run_dump_test "arch-14" run_dump_test "8087" run_dump_test "287" run_dump_test "387" @@ -461,6 +463,9 @@ if [gas_32_check] then { run_dump_test "avx-vnni" run_list_test "sg" run_dump_test "clzero" + run_dump_test "invlpgb" + run_dump_test "tlbsync" + run_dump_test "snp" run_dump_test "disassem" run_dump_test "mwaitx-bdver4" run_list_test "mwaitx-reg" @@ -838,6 +843,7 @@ if [gas_64_check] then { run_dump_test "x86-64-arch-1" run_dump_test "x86-64-arch-2" run_dump_test "x86-64-arch-3" + run_dump_test "x86-64-arch-4" run_dump_test "x86-64-arch-2-lzcnt" run_dump_test "x86-64-arch-2-prefetchw" run_dump_test "x86-64-arch-2-bdver1" @@ -846,6 +852,7 @@ if [gas_64_check] then { run_dump_test "x86-64-arch-2-bdver4" run_dump_test "x86-64-arch-3-znver1" run_dump_test "x86-64-arch-3-znver2" + run_dump_test "x86-64-arch-4-znver3" run_dump_test "x86-64-arch-2-btver1" run_dump_test "x86-64-arch-2-btver2" run_list_test "x86-64-arch-2-1" "-march=generic64 -I${srcdir}/$subdir -al" diff --git a/gas/testsuite/gas/i386/invlpgb.d b/gas/testsuite/gas/i386/invlpgb.d new file mode 100644 index 0000000000..6abb153b45 --- /dev/null +++ b/gas/testsuite/gas/i386/invlpgb.d @@ -0,0 +1,11 @@ +#objdump: -dw +#name: i386 INVLPGB insn + +.*: +file format .* + + +Disassembly of section \.text: + +00000000 <_start>: +[ ]*[a-f0-9]+: 0f 01 fe invlpgb[ ^I]* +#pass diff --git a/gas/testsuite/gas/i386/invlpgb.s b/gas/testsuite/gas/i386/invlpgb.s new file mode 100644 index 0000000000..5b4862b909 --- /dev/null +++ b/gas/testsuite/gas/i386/invlpgb.s @@ -0,0 +1,5 @@ +# Check INVLPGB instructions + + .text +_start: + invlpgb diff --git a/gas/testsuite/gas/i386/snp.d b/gas/testsuite/gas/i386/snp.d new file mode 100644 index 0000000000..d02d3dd53f --- /dev/null +++ b/gas/testsuite/gas/i386/snp.d @@ -0,0 +1,14 @@ +#objdump: -dw +#name: i386 SNP insn + +.*: +file format .* + + +Disassembly of section \.text: + +00000000 <_start>: +[ ]*[a-f0-9]+: f3 0f 01 ff psmash[ ^I]* +[ ]*[a-f0-9]+: f2 0f 01 ff pvalidate[ ^I]* +[ ]*[a-f0-9]+: f2 0f 01 fe rmpupdate[ ^I]* +[ ]*[a-f0-9]+: f3 0f 01 fe rmpadjust[ ^I]* +#pass diff --git a/gas/testsuite/gas/i386/snp.s b/gas/testsuite/gas/i386/snp.s new file mode 100644 index 0000000000..7debe94120 --- /dev/null +++ b/gas/testsuite/gas/i386/snp.s @@ -0,0 +1,8 @@ +# Check SNP instructions + + .text +_start: + psmash + pvalidate + rmpupdate + rmpadjust diff --git a/gas/testsuite/gas/i386/tlbsync.d b/gas/testsuite/gas/i386/tlbsync.d new file mode 100644 index 0000000000..0ea579036b --- /dev/null +++ b/gas/testsuite/gas/i386/tlbsync.d @@ -0,0 +1,11 @@ +#objdump: -dw +#name: i386 TLBSYNC insn + +.*: +file format .* + + +Disassembly of section \.text: + +00000000 <_start>: +[ ]*[a-f0-9]+: 0f 01 ff tlbsync[ ^I]* +#pass diff --git a/gas/testsuite/gas/i386/tlbsync.s b/gas/testsuite/gas/i386/tlbsync.s new file mode 100644 index 0000000000..fddd4ef5f3 --- /dev/null +++ b/gas/testsuite/gas/i386/tlbsync.s @@ -0,0 +1,5 @@ +# Check TLBSYNC instructions + + .text +_start: + tlbsync diff --git a/gas/testsuite/gas/i386/x86-64-arch-4-znver3.d b/gas/testsuite/gas/i386/x86-64-arch-4-znver3.d new file mode 100644 index 0000000000..0d3a865030 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-arch-4-znver3.d @@ -0,0 +1,5 @@ +#source: x86-64-arch-4.s +#as: -march=znver3 +#objdump: -dw +#name: x86-64 arch 4 (znver3) +#dump: x86-64-arch-4.d diff --git a/gas/testsuite/gas/i386/x86-64-arch-4.d b/gas/testsuite/gas/i386/x86-64-arch-4.d new file mode 100644 index 0000000000..f5373d51a1 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-arch-4.d @@ -0,0 +1,33 @@ +#objdump: -dw +#name: x86-64 arch 4 + +.*: file format .* + +Disassembly of section .text: + +0+ <.text>: +[ ]*[0-9a-f]+:[ ]+0f 01 fe[ ]+invlpgb[ ]* +[ ]*[0-9a-f]+:[ ]+0f 01 ff[ ]+tlbsync[ ]* +[ ]*[a-f0-9]+:[ ]*c4 43 35 44 d0 ab[ ]*vpclmulqdq \$0xab,%ymm8,%ymm9,%ymm10 +[ ]*[a-f0-9]+:[ ]*c4 23 35 44 94 f0 24 01 00 00 7b[ ]*vpclmulqdq \$0x7b,0x124\(%rax,%r14,8\),%ymm9,%ymm10 +[ ]*[a-f0-9]+:[ ]*c4 63 35 44 92 e0 0f 00 00 7b[ ]*vpclmulqdq \$0x7b,0xfe0\(%rdx\),%ymm9,%ymm10 +[ ]*[a-f0-9]+:[ ]*c4 43 25 44 e2 11[ ]*vpclmulhqhqdq %ymm10,%ymm11,%ymm12 +[ ]*[a-f0-9]+:[ ]*c4 43 1d 44 eb 01[ ]*vpclmulhqlqdq %ymm11,%ymm12,%ymm13 +[ ]*[a-f0-9]+:[ ]*c4 43 15 44 f4 10[ ]*vpclmullqhqdq %ymm12,%ymm13,%ymm14 +[ ]*[a-f0-9]+:[ ]*c4 43 0d 44 fd 00[ ]*vpclmullqlqdq %ymm13,%ymm14,%ymm15 +[ ]*[a-f0-9]+: c4 e2 4d dc d4[ ]+vaesenc %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e2 4d dc 39[ ]+vaesenc \(%rcx\),%ymm6,%ymm7 +[ ]*[a-f0-9]+: c4 e2 4d dd d4[ ]+vaesenclast %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e2 4d dd 39[ ]+vaesenclast \(%rcx\),%ymm6,%ymm7 +[ ]*[a-f0-9]+: c4 e2 4d de d4[ ]+vaesdec %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e2 4d de 39[ ]+vaesdec \(%rcx\),%ymm6,%ymm7 +[ ]*[a-f0-9]+: c4 e2 4d df d4[ ]+vaesdeclast %ymm4,%ymm6,%ymm2 +[ ]*[a-f0-9]+: c4 e2 4d df 39[ ]+vaesdeclast \(%rcx\),%ymm6,%ymm7 +[ ]*[a-f0-9]+: f3 0f 01 ff[ ]+psmash[ ]* +[ ]*[a-f0-9]+: f2 0f 01 ff[ ]+pvalidate[ ]* +[ ]*[a-f0-9]+: f2 0f 01 fe[ ]+rmpupdate[ ]* +[ ]*[a-f0-9]+: f3 0f 01 fe[ ]+rmpadjust[ ]* +[ ]*[a-f0-9]+: 66 0f 38 82 10[ ]+invpcid \(%rax\),%rdx +[ ]*[a-f0-9]+: 0f 01 ee[ ]+rdpkru[ ]* +[ ]*[a-f0-9]+: 0f 01 ef[ ]+wrpkru[ ]* +#pass diff --git a/gas/testsuite/gas/i386/x86-64-arch-4.s b/gas/testsuite/gas/i386/x86-64-arch-4.s new file mode 100644 index 0000000000..4b2dc814a2 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-arch-4.s @@ -0,0 +1,34 @@ +# Test -march= + .text +#INVLPGB + invlpgb +#TLBSYNC + tlbsync +#VPCLMUL 256 datapath + vpclmulqdq $0xab, %ymm8, %ymm9, %ymm10 + vpclmulqdq $123, 0x124(%rax,%r14,8), %ymm9, %ymm10 + vpclmulqdq $123, 4064(%rdx), %ymm9, %ymm10 + + vpclmulhqhqdq %ymm10, %ymm11, %ymm12 + vpclmulhqlqdq %ymm11, %ymm12, %ymm13 + vpclmullqhqdq %ymm12, %ymm13, %ymm14 + vpclmullqlqdq %ymm13, %ymm14, %ymm15 +#VAES + vaesenc %ymm4,%ymm6,%ymm2 + vaesenc (%rcx),%ymm6,%ymm7 + vaesenclast %ymm4,%ymm6,%ymm2 + vaesenclast (%rcx),%ymm6,%ymm7 + vaesdec %ymm4,%ymm6,%ymm2 + vaesdec (%rcx),%ymm6,%ymm7 + vaesdeclast %ymm4,%ymm6,%ymm2 + vaesdeclast (%rcx),%ymm6,%ymm7 +#SNP - Secure Nested Paging support + psmash + pvalidate + rmpupdate + rmpadjust +#INVPCID + invpcid (%rax), %rdx +#OSPKE + rdpkru + wrpkru diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index 7467ecdd4a..be4429f73f 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -969,6 +969,8 @@ enum PREFIX_0F01_REG_5_MOD_3_RM_6, PREFIX_0F01_REG_5_MOD_3_RM_7, PREFIX_0F01_REG_7_MOD_3_RM_2, + PREFIX_0F01_REG_7_MOD_3_RM_6, + PREFIX_0F01_REG_7_MOD_3_RM_7, PREFIX_0F09, PREFIX_0F10, PREFIX_0F11, @@ -3210,6 +3212,22 @@ static const struct dis386 prefix_table[][4] = { { "mcommit", { Skip_MODRM }, 0 }, }, + /* PREFIX_0F01_REG_7_MOD_3_RM_6 */ + { + { "invlpgb", { Skip_MODRM }, 0 }, + { "rmpadjust", { Skip_MODRM }, PREFIX_OPCODE }, + { Bad_Opcode }, + { "rmpupdate", { Skip_MODRM }, PREFIX_OPCODE }, + }, + + /* PREFIX_0F01_REG_7_MOD_3_RM_7 */ + { + { "tlbsync", { Skip_MODRM }, 0 }, + { "psmash", { Skip_MODRM }, PREFIX_OPCODE }, + { Bad_Opcode }, + { "pvalidate", { Skip_MODRM }, PREFIX_OPCODE }, + }, + /* PREFIX_0F09 */ { { "wbinvd", { XX }, 0 }, @@ -8990,6 +9008,8 @@ static const struct dis386 rm_table[][8] = { { "mwaitx", { { OP_Mwait, eBX_reg } }, PREFIX_OPCODE }, { "clzero", { Skip_MODRM }, 0 }, { "rdpru", { Skip_MODRM }, 0 }, + { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_6) }, + { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_7) }, }, { /* RM_0F1E_P_1_MOD_3_REG_7 */ diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index fc42088638..3f203a4f4f 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -103,6 +103,8 @@ static initializer cpu_flag_init[] = "CPU_GENERIC64_FLAGS|CpuFISTTP|CpuRdtscp|CpuCX16|CPU_AVX2_FLAGS|CpuSSE4A|CpuLZCNT|CpuPOPCNT|CpuSVME|CpuAES|CpuPCLMUL|CpuPRFCHW|CpuFMA|CpuBMI|CpuF16C|CpuXsaveopt|CpuFSGSBase|CpuMovbe|CpuBMI2|CpuRdRnd|CpuADX|CpuRdSeed|CpuSMAP|CpuSHA|CpuXSAVEC|CpuXSAVES|CpuClflushOpt|CpuCLZERO|CpuMWAITX" }, { "CPU_ZNVER2_FLAGS", "CPU_ZNVER1_FLAGS|CpuCLWB|CpuRDPID|CpuRDPRU|CpuMCOMMIT|CpuWBNOINVD" }, + { "CPU_ZNVER3_FLAGS", + "CPU_ZNVER2_FLAGS|CpuINVLPGB|CpuTLBSYNC|CpuVAES|CpuVPCLMULQDQ|CpuINVPCID|CpuSNP|CpuOSPKE" }, { "CPU_BTVER1_FLAGS", "CPU_GENERIC64_FLAGS|CpuFISTTP|CpuCX16|CpuRdtscp|CPU_SSSE3_FLAGS|CpuSSE4A|CpuLZCNT|CpuPOPCNT|CpuPRFCHW|CpuCX16|CpuClflush|CpuFISTTP|CpuSVME" }, { "CPU_BTVER2_FLAGS", @@ -333,6 +335,12 @@ static initializer cpu_flag_init[] = "CpuWideKL" }, { "CPU_HRESET_FLAGS", "CpuHRESET"}, + { "CPU_INVLPGB_FLAGS", + "CpuINVLPGB" }, + { "CPU_TLBSYNC_FLAGS", + "CpuTLBSYNC" }, + { "CPU_SNP_FLAGS", + "CpuSNP" }, { "CPU_ANY_X87_FLAGS", "CPU_ANY_287_FLAGS|Cpu8087" }, { "CPU_ANY_287_FLAGS", @@ -667,6 +675,9 @@ static bitfield cpu_flags[] = BITFIELD (CpuKL), BITFIELD (CpuWideKL), BITFIELD (CpuHRESET), + BITFIELD (CpuINVLPGB), + BITFIELD (CpuTLBSYNC), + BITFIELD (CpuSNP), #ifdef CpuUnused BITFIELD (CpuUnused), #endif diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index 2e90c58421..473e2ad3dc 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -273,6 +273,12 @@ enum CpuWideKL, /* HRESET instruction required */ CpuHRESET, + /* INVLPGB instructions required */ + CpuINVLPGB, + /* TLBSYNC instructions required */ + CpuTLBSYNC, + /* SNP instructions required */ + CpuSNP, /* 64bit support required */ Cpu64, /* Not supported in the 64bit mode */ @@ -417,6 +423,9 @@ typedef union i386_cpu_flags unsigned int cpukl:1; unsigned int cpuwidekl:1; unsigned int cpuhreset:1; + unsigned int cpuinvlpgb:1; + unsigned int cputlbsync:1; + unsigned int cpusnp:1; unsigned int cpu64:1; unsigned int cpuno64:1; #ifdef CpuUnused diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 6745eff26c..6ee00ecfb6 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -3960,6 +3960,18 @@ vpclmulhqhqdq, 3, 0x6644, 0x11, 1, CpuVPCLMULQDQ|CpuAVX512F, Modrm|OpcodePrefix= // AVX512 + VPCLMULQDQ instructions end +// INVLPGB instructions + +invlpgb, 0, 0xf01fe, None, 3, CpuINVLPGB, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } + +// INVLPGB instructions end + +// TLBSYNC instructions + +tlbsync, 0, 0xf01ff, None, 3, CpuTLBSYNC, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } + +// TLBSYNC instructions end + // CLZERO instructions clzero, 0, 0xf01fc, None, 3, CpuCLZERO, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } @@ -4092,6 +4104,15 @@ mcommit, 0, 0x0f01fa, None, 3, CpuMCOMMIT, Prefix_0XF3|No_bSuf|No_wSuf|No_lSuf|N // MCOMMIT instruction end +// SNP instructions + +psmash, 0, 0x0f01ff, None, 3, CpuSNP, Prefix_0XF3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +pvalidate, 0, 0x0f01ff, None, 3, CpuSNP, Prefix_0XF2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +rmpupdate, 0, 0x0f01fe, None, 3, CpuSNP, Prefix_0XF2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +rmpadjust, 0, 0x0f01fe, None, 3, CpuSNP, Prefix_0XF3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } + +// SNP instructions end + // RDPRU instruction rdpru, 0, 0x0f01fd, None, 3, CpuRDPRU, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } -- 2.25.1