diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index 0c1b9746b2ee8dfc278c1d3dcb9537ad335a436d..579275541c3cb6d25da85dcad6e39211b7670143 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -317,6 +317,8 @@ static const arm_feature_set fpu_neon_ext_dotprod = ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD); static const arm_feature_set sb_ext_armv8 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB); +static const arm_feature_set predres_ext_armv8 = + ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES); static int mfloat_abi_opt = -1; /* Architecture feature bits selected by the last -mcpu/-march or .cpu/.arch @@ -21525,6 +21527,14 @@ static const struct asm_opcode insns[] = #define THUMB_VARIANT & sb_ext_armv8 TUF("sb", 57ff070, f3bf8f70, 0, (), noargs, noargs), +#undef ARM_VARIANT +#define ARM_VARIANT & predres_ext_armv8 +#undef THUMB_VARIANT +#define THUMB_VARIANT & predres_ext_armv8 + CE("cfprctx", e070f93, 1, (RRnpc), rd), + CE("dvprctx", e070fb3, 1, (RRnpc), rd), + CE("cpprctx", e070ff3, 1, (RRnpc), rd), + /* ARMv8-M instructions. */ #undef ARM_VARIANT #define ARM_VARIANT NULL @@ -26421,6 +26431,9 @@ static const struct arm_option_extension_value_table arm_extensions[] = ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), ARM_FEATURE (ARM_EXT_V8, ARM_EXT2_PAN, 0), ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)), + ARM_EXT_OPT ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES), + ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES), + ARM_ARCH_V8A), ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS), ARM_FEATURE (ARM_EXT_V8, ARM_EXT2_RAS, 0), ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)), diff --git a/gas/doc/c-arm.texi b/gas/doc/c-arm.texi index 18008c48666ccdea96f166612ab0868dbe4c8bf8..835777a3abb89eba97b11bd9972adf9a0826bd26 100644 --- a/gas/doc/c-arm.texi +++ b/gas/doc/c-arm.texi @@ -189,6 +189,8 @@ The following extensions are currently supported: @code{mp} (Multiprocessing Extensions for v7-A and v7-R architectures), @code{os} (Operating System for v6M architecture), +@code{predres} (Execution and Data Prediction Restriction Instruction for +v8-A architectures, added by default from v8.5-A), @code{sb} (Speculation Barrier Instruction for v8-A architectures, added by default from v8.5-A), @code{sec} (Security Extensions for v6K and v7-A architectures), diff --git a/gas/testsuite/gas/arm/predres-bad.d b/gas/testsuite/gas/arm/predres-bad.d new file mode 100644 index 0000000000000000000000000000000000000000..7fc8ca077799da0a8ddd3ab21f87ac2a4eee9eb3 --- /dev/null +++ b/gas/testsuite/gas/arm/predres-bad.d @@ -0,0 +1,4 @@ +#name: Error for Prediction Restriction instructions without +predres +#source: predres.s +#as: -march=armv8-a +#error-output: predres-bad.l diff --git a/gas/testsuite/gas/arm/predres-bad.l b/gas/testsuite/gas/arm/predres-bad.l new file mode 100644 index 0000000000000000000000000000000000000000..3f7efc62b069d678dcfeb48f6e93be7c328c16de --- /dev/null +++ b/gas/testsuite/gas/arm/predres-bad.l @@ -0,0 +1,4 @@ +[^:]*: Assembler messages: +[^:]*:4: Error: selected processor does not support `cfprctx r1' in ARM mode +[^:]*:5: Error: selected processor does not support `dvprctx r2' in ARM mode +[^:]*:6: Error: selected processor does not support `cpprctx r3' in ARM mode diff --git a/gas/testsuite/gas/arm/predres.s b/gas/testsuite/gas/arm/predres.s new file mode 100644 index 0000000000000000000000000000000000000000..6cfb1f166fe1d3744a9f081758bf25b090e3fa1a --- /dev/null +++ b/gas/testsuite/gas/arm/predres.s @@ -0,0 +1,6 @@ +@ Test case to validate Prediction Restriction Instructions +.section .text +.syntax unified + cfprctx r1 + dvprctx r2 + cpprctx r3 diff --git a/gas/testsuite/gas/arm/predres1.d b/gas/testsuite/gas/arm/predres1.d new file mode 100644 index 0000000000000000000000000000000000000000..b3a900a3d4756da529e2b765b20be4831b1cf3df --- /dev/null +++ b/gas/testsuite/gas/arm/predres1.d @@ -0,0 +1,11 @@ +#name: Execution and Data Prediction Restriction instructions +#source: predres.s +#as: -march=armv8.5-a +#objdump: -dr --prefix-addresses --show-raw-insn + +.*: *file format .*arm.* + +Disassembly of section .text: +.*> ee071f93 mcr 15, 0, r1, cr7, cr3, \{4\} +.*> ee072fb3 mcr 15, 0, r2, cr7, cr3, \{5\} +.*> ee073ff3 mcr 15, 0, r3, cr7, cr3, \{7\} diff --git a/gas/testsuite/gas/arm/predres2.d b/gas/testsuite/gas/arm/predres2.d new file mode 100644 index 0000000000000000000000000000000000000000..d17cf06eb0ea36977aa13853d4872daded805bc5 --- /dev/null +++ b/gas/testsuite/gas/arm/predres2.d @@ -0,0 +1,11 @@ +#name: Execution and Data Prediction Restriction instructions with +predres +#source: predres.s +#as: -march=armv8-a+predres +#objdump: -dr --prefix-addresses --show-raw-insn + +.*: *file format .*arm.* + +Disassembly of section .text: +.*> ee071f93 mcr 15, 0, r1, cr7, cr3, \{4\} +.*> ee072fb3 mcr 15, 0, r2, cr7, cr3, \{5\} +.*> ee073ff3 mcr 15, 0, r3, cr7, cr3, \{7\} diff --git a/include/opcode/arm.h b/include/opcode/arm.h index c595799920e369b859f851d184639f9489554da4..71c430638b1af3785721f789a2fc7a476370da6d 100644 --- a/include/opcode/arm.h +++ b/include/opcode/arm.h @@ -70,6 +70,7 @@ #define ARM_EXT2_FP16_FML 0x00000800 /* ARM V8.2A FP16-FML instructions. */ #define ARM_EXT2_V8_5A 0x00001000 /* ARM V8.5A. */ #define ARM_EXT2_SB 0x00002000 /* Speculation Barrier instruction. */ +#define ARM_EXT2_PREDRES 0x00004000 /* Prediction Restriction insns. */ /* Co-processor space extensions. */ #define ARM_CEXT_XSCALE 0x00000001 /* Allow MIA etc. */ @@ -297,7 +298,8 @@ CRC_EXT_ARMV8 | FPU_NEON_EXT_RDMA \ | FPU_NEON_EXT_DOTPROD) #define ARM_ARCH_V8_5A ARM_FEATURE (ARM_AEXT_V8A, \ - ARM_AEXT2_V8_5A | ARM_EXT2_SB, \ + ARM_AEXT2_V8_5A | ARM_EXT2_SB \ + | ARM_EXT2_PREDRES, \ CRC_EXT_ARMV8 | FPU_NEON_EXT_RDMA \ | FPU_NEON_EXT_DOTPROD) #define ARM_ARCH_V8M_BASE ARM_FEATURE_CORE (ARM_AEXT_V8M_BASE, ARM_AEXT2_V8M)