From 51c7623fde1b30b1f57c7c5443c8db3751e5c151 Mon Sep 17 00:00:00 2001 From: Jia Liu Date: Thu, 2 Feb 2012 13:43:07 +0800 Subject: [PATCH] add MIPS64DSPR2 support Content-Type: text/plain; charset="utf-8" --- gas/config/tc-mips.c | 19 ++++++++++++++++ gas/testsuite/gas/mips/mips64-dspr2.d | 38 +++++++++++++++++++++++++++++++++ gas/testsuite/gas/mips/mips64-dspr2.s | 38 +++++++++++++++++++++++++++++++++ include/opcode/mips.h | 10 ++++++-- opcodes/mips-dis.c | 7 +++++- opcodes/mips-opc.c | 28 ++++++++++++++++++++++++ 6 files changed, 136 insertions(+), 4 deletions(-) create mode 100644 gas/testsuite/gas/mips/mips64-dspr2.d create mode 100644 gas/testsuite/gas/mips/mips64-dspr2.s diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c index f23835a..d3681c9 100644 --- a/gas/config/tc-mips.c +++ b/gas/config/tc-mips.c @@ -362,6 +362,8 @@ static int file_ase_dspr2; #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \ || mips_opts.isa == ISA_MIPS64R2) +#define ISA_SUPPORTS_DSP64R2_ASE (mips_opts.isa == ISA_MIPS64R2) + /* True if -mmt was passed or implied by arguments passed on the command line (e.g., by -march). */ static int file_ase_mt; @@ -2210,6 +2212,8 @@ is_opcode_valid (const struct mips_opcode *mo) isa |= INSN_DSP64; if (mips_opts.ase_dspr2) isa |= INSN_DSPR2; + if (mips_opts.ase_dspr2 && ISA_SUPPORTS_DSP64R2_ASE) + isa |= INSN_DSP64R2; if (mips_opts.ase_mt) isa |= INSN_MT; if (mips_opts.ase_mips3d) @@ -10327,6 +10331,7 @@ validate_mips_insn (const struct mips_opcode *opc) case ']': break; case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break; + case '^': USE_BITS (OP_MASK_BP3, OP_SH_BP3); break; case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break; case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break; case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break; @@ -10788,6 +10793,20 @@ mips_ip (char *str, struct mips_cl_insn *ip) s = expr_end; continue; + case '^': /* DSP 3-bit unsigned immediate in bit 11. */ + gas_assert (!mips_opts.micromips); + my_getExpression (&imm_expr, s); + check_absolute_expr (ip, &imm_expr); + if (imm_expr.X_add_number & ~OP_MASK_BP3) + { + as_bad (_("DBALIGN immediate not in rage 0..%d (%lu)"), + OP_MASK_BP3, (unsigned long) imm_expr.X_add_number); + } + INSERT_OPERAND (0, BP3, *ip, imm_expr.X_add_number); + imm_expr.X_op = O_absent; + s = expr_end; + continue; + case '3': /* DSP 3-bit unsigned immediate in bit 21. */ gas_assert (!mips_opts.micromips); my_getExpression (&imm_expr, s); diff --git a/gas/testsuite/gas/mips/mips64-dspr2.d b/gas/testsuite/gas/mips/mips64-dspr2.d new file mode 100644 index 0000000..e1fb0e2 --- /dev/null +++ b/gas/testsuite/gas/mips/mips64-dspr2.d @@ -0,0 +1,38 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: MIPS DSP ASE Rev2 for MIPS64 +#as: -mdspr2 -mips64r2 -32 + +# Check MIPS DSP ASE Rev2 for MIPS64 Instruction Assembly + +.*: +file format .*mips.* + + +Disassembly of section .text: +0+0000: 7c010056 absq_s.ob zero,at +0+0004: 7c430a14 addu.qh at,v0,v1 +0+0008: 7c641314 addu_s.qh v0,v1,a0 +0+000c: 7c851e14 adduh.ob v1,a0,a1 +0+0010: 7ca62694 adduh_r.ob a0,a1,a2 +0+0014: 7ce83615 cmpgdu.eq.ob a2,a3,a4 +0+0018: 7d093e55 cmpgdu.lt.ob a3,a4,a5 +0+001c: 7d2a4695 cmpgdu.le.ob a4,a5,a6 +0+0020: 7cc50035 dappend a1,a2,0x0 +0+0024: 7ce60c35 dbalign a2,a3,0x1 +0+0028: 7d2a0034 dpa.w.qh $ac0,a5,a6 +0+002c: 7d4b0874 dps.w.qh $ac1,a6,a7 +0+0030: 7f19bb55 precr.ob.qh s7,t8,t9 +0+0034: 7f380795 precr_sra.qh.pw t8,t9,0x0 +0+0038: 7f5907d5 precr_sra_r.qh.pw t9,k0,0x0 +0+003c: 7f7a00f5 prependd k0,k1,0x0 +0+0040: 7f7af875 prependw k0,k1,0x1f +0+0044: 7c1cd917 shra.ob k1,gp,0x0 +0+0048: 7c1de157 shra_r.ob gp,sp,0x0 +0+004c: 7ffee997 shrav.ob sp,s8,ra +0+0050: 7c1ff1d7 shrav_r.ob s8,ra,zero +0+0054: 7c00fe57 shrl.qh ra,zero,0x0 +0+0058: 7c4106d7 shrlv.qh zero,at,v0 +0+005c: 7c430a54 subu.qh at,v0,v1 +0+0060: 7c641354 subu_s.qh v0,v1,a0 +0+0064: 7c851e54 subuh.ob v1,a0,a1 +0+0068: 7ca626d4 subuh_r.ob a0,a1,a2 + \.\.\. diff --git a/gas/testsuite/gas/mips/mips64-dspr2.s b/gas/testsuite/gas/mips/mips64-dspr2.s new file mode 100644 index 0000000..a6f80ba --- /dev/null +++ b/gas/testsuite/gas/mips/mips64-dspr2.s @@ -0,0 +1,38 @@ +# source file to test assembly of MIPS DSP ASE Rev2 for MIPS32 instructions + + .set noreorder + .set noat + + .text +text_label: + + absq_s.ob $0,$1 + addu.qh $1,$2,$3 + addu_s.qh $2,$3,$4 + adduh.ob $3,$4,$5 + adduh_r.ob $4,$5,$6 + cmpgdu.eq.ob $6,$7,$8 + cmpgdu.lt.ob $7,$8,$9 + cmpgdu.le.ob $8,$9,$10 + dappend $5,$6,0 + dbalign $6,$7,1 + dpa.w.qh $ac0,$9,$10 + dps.w.qh $ac1,$10,$11 + precr.ob.qh $23,$24,$25 + precr_sra.qh.pw $24,$25,0 + precr_sra_r.qh.pw $25,$26,0 + prependd $26,$27,0 + prependw $26,$27,31 + shra.ob $27,$28,0 + shra_r.ob $28,$29,0 + shrav.ob $29,$30,$31 + shrav_r.ob $30,$31,$0 + shrl.qh $31,$0,0 + shrlv.qh $0,$1,$2 + subu.qh $1,$2,$3 + subu_s.qh $2,$3,$4 + subuh.ob $3,$4,$5 + subuh_r.ob $4,$5,$6 + +# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ... + .space 8 diff --git a/include/opcode/mips.h b/include/opcode/mips.h index fb9094c..9a1132d 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -176,6 +176,8 @@ #define OP_MASK_RDDSP 0x3f #define OP_SH_BP 11 #define OP_MASK_BP 0x3 +#define OP_SH_BP3 11 +#define OP_MASK_BP3 0x7 /* MIPS MT ASE */ #define OP_SH_MT_U 5 @@ -456,6 +458,7 @@ struct mips_opcode DSP ASE usage: "2" 2 bit unsigned immediate for byte align (OP_*_BP) + "^" 3 bit unsigned immediate for byte align (OP_*_BP3) "3" 3 bit unsigned immediate (OP_*_SA3) "4" 4 bit unsigned immediate (OP_*_SA4) "5" 8 bit unsigned immediate (OP_*_IMM8) @@ -516,7 +519,7 @@ struct mips_opcode Characters used so far, for quick reference when adding more: "1234567890" - "%[]<>(),+:'@!$*&\~" + "%[]<>(),+:'@!$*&\~^" "ABCDEFGHIJKLMNOPQRSTUVWXYZ" "abcdefghijklopqrstuvwxz" @@ -726,8 +729,7 @@ static const unsigned int mips_isa_table[] = /* DSP ASE */ #define INSN_DSP 0x00001000 #define INSN_DSP64 0x00002000 - -/* 0x00004000 is unused. */ +#define INSN_DSP64R2 0x00004000 /* MIPS-3D ASE */ #define INSN_MIPS3D 0x00008000 @@ -1530,6 +1532,8 @@ extern const int bfd_mips16_num_opcodes; #define MICROMIPSOP_SH_RDDSP 0 #define MICROMIPSOP_MASK_BP 0 #define MICROMIPSOP_SH_BP 0 +#define MICROMIPSOP_MASK_BP3 0 +#define MICROMIPSOP_SH_BP3 0 #define MICROMIPSOP_MASK_MT_U 0 #define MICROMIPSOP_SH_MT_U 0 #define MICROMIPSOP_MASK_MT_H 0 diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c index 0d1de30..859029d 100644 --- a/opcodes/mips-dis.c +++ b/opcodes/mips-dis.c @@ -578,7 +578,7 @@ const struct mips_arch_choice mips_arch_choices[] = { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2, (ISA_MIPS64R2 | INSN_MIPS3D | INSN_DSP | INSN_DSPR2 - | INSN_DSP64 | INSN_MT | INSN_MDMX | INSN_MCU), + | INSN_DSP64 | INSN_DSP64R2 | INSN_MT | INSN_MDMX | INSN_MCU), mips_cp0_names_mips3264r2, mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), mips_hwr_names_mips3264r2 }, @@ -1129,6 +1129,11 @@ print_insn_args (const char *d, (l >> OP_SH_BP) & OP_MASK_BP); break; + case '^': + (*info->fprintf_func) (info->stream, "0x%lx", + (l >> OP_SH_BP3) & OP_MASK_BP3); + break; + case '3': (*info->fprintf_func) (info->stream, "0x%lx", (l >> OP_SH_SA3) & OP_MASK_SA3); diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index 4083c1a..368640d 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -164,6 +164,7 @@ #define D32 INSN_DSP #define D33 INSN_DSPR2 #define D64 INSN_DSP64 +#define D65 INSN_DSP64R2 /* MIPS MT ASE support. */ #define MT32 INSN_MT @@ -1897,18 +1898,30 @@ const struct mips_opcode mips_builtin_opcodes[] = {"wrdsp", "s,8", 0x7c0004f8, 0xfc1e07ff, RD_s|DSP_VOLA, 0, D32 }, /* MIPS DSP ASE Rev2 */ {"absq_s.qb", "d,t", 0x7c000052, 0xffe007ff, WR_d|RD_t, 0, D33 }, +{"absq_s.ob", "d,t", 0x7c000056, 0xffe007ff, WR_d|RD_t, 0, D65 }, {"addu.ph", "d,s,t", 0x7c000210, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"addu.qh", "d,s,t", 0x7c000214, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D65 }, {"addu_s.ph", "d,s,t", 0x7c000310, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"addu_s.qh", "d,s,t", 0x7c000314, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D65 }, {"adduh.qb", "d,s,t", 0x7c000018, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"adduh.ob", "d,s,t", 0x7c000614, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D65 }, {"adduh_r.qb", "d,s,t", 0x7c000098, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"adduh_r.ob", "d,s,t", 0x7c000694, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D65 }, {"append", "t,s,h", 0x7c000031, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 }, {"balign", "t,s,I", 0, (int) M_BALIGN, INSN_MACRO, 0, D33 }, {"balign", "t,s,2", 0x7c000431, 0xfc00e7ff, WR_t|RD_t|RD_s, 0, D33 }, {"cmpgdu.eq.qb", "d,s,t", 0x7c000611, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"cmpgdu.eq.ob", "d,s,t", 0x7c000615, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D65 }, {"cmpgdu.lt.qb", "d,s,t", 0x7c000651, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"cmpgdu.lt.ob", "d,s,t", 0x7c000655, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D65 }, {"cmpgdu.le.qb", "d,s,t", 0x7c000691, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"cmpgdu.le.ob", "d,s,t", 0x7c000695, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D65 }, +{"dappend", "t,s,h", 0x7c000035, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D65 }, +{"dbalign", "t,s,^", 0x7c000435, 0xfc00c7ff, WR_t|RD_t|RD_s, 0, D65 }, {"dpa.w.ph", "7,s,t", 0x7c000030, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, +{"dpa.w.qh", "7,s,t", 0x7c000034, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D65 }, {"dps.w.ph", "7,s,t", 0x7c000070, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, +{"dps.w.qh", "7,s,t", 0x7c000074, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D65 }, {"mul.ph", "d,s,t", 0x7c000318, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, {"mul_s.ph", "d,s,t", 0x7c000398, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, {"mulq_rs.w", "d,s,t", 0x7c0005d8, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, @@ -1916,19 +1929,34 @@ const struct mips_opcode mips_builtin_opcodes[] = {"mulq_s.w", "d,s,t", 0x7c000598, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, {"mulsa.w.ph", "7,s,t", 0x7c0000b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, {"precr.qb.ph", "d,s,t", 0x7c000351, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"precr.ob.qh", "d,s,t", 0x7c000355, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D65 }, {"precr_sra.ph.w", "t,s,h", 0x7c000791, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 }, +{"precr_sra.qh.pw", "t,s,h", 0x7c000795, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D65 }, {"precr_sra_r.ph.w", "t,s,h", 0x7c0007d1, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 }, +{"precr_sra_r.qh.pw", "t,s,h", 0x7c0007d5, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D65 }, {"prepend", "t,s,h", 0x7c000071, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 }, +{"prependw", "t,s,h", 0x7c000075, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D65 }, +{"prependd", "t,s,h", 0x7c0000f5, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D65 }, {"shra.qb", "d,t,3", 0x7c000113, 0xff0007ff, WR_d|RD_t, 0, D33 }, +{"shra.ob", "d,t,3", 0x7c000117, 0xff0007ff, WR_d|RD_t, 0, D65 }, {"shra_r.qb", "d,t,3", 0x7c000153, 0xff0007ff, WR_d|RD_t, 0, D33 }, +{"shra_r.ob", "d,t,3", 0x7c000157, 0xff0007ff, WR_d|RD_t, 0, D65 }, {"shrav.qb", "d,t,s", 0x7c000193, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"shrav.ob", "d,t,s", 0x7c000197, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D65 }, {"shrav_r.qb", "d,t,s", 0x7c0001d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"shrav_r.ob", "d,t,s", 0x7c0001d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D65 }, {"shrl.ph", "d,t,4", 0x7c000653, 0xfe0007ff, WR_d|RD_t, 0, D33 }, +{"shrl.qh", "d,t,4", 0x7c000657, 0xfe0007ff, WR_d|RD_t, 0, D65 }, {"shrlv.ph", "d,t,s", 0x7c0006d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"shrlv.qh", "d,t,s", 0x7c0006d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D65 }, {"subu.ph", "d,s,t", 0x7c000250, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"subu.qh", "d,s,t", 0x7c000254, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D65 }, {"subu_s.ph", "d,s,t", 0x7c000350, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"subu_s.qh", "d,s,t", 0x7c000354, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D65 }, {"subuh.qb", "d,s,t", 0x7c000058, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"subuh.ob", "d,s,t", 0x7c000654, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D65 }, {"subuh_r.qb", "d,s,t", 0x7c0000d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"subuh_r.ob", "d,s,t", 0x7c0006d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D65 }, {"addqh.ph", "d,s,t", 0x7c000218, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, {"addqh_r.ph", "d,s,t", 0x7c000298, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, {"addqh.w", "d,s,t", 0x7c000418, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, -- 1.7.5.4