2010-10-06  Nathan Sidwell  <nathan@codesourcery.com>

	bfd/
	* elf32-arm.c (elf32_arm_stub_long_branch_any_arm_pic, 
	elf32_arm_stub_long_branch_any_arm_pic): Use a consistent name for
	ip/r12.
	(arm_type_of_stub): Remove superfluous braces.

	gas/
	* config/tc-arm.c (encode_branch): Remove superfluous braces.
	(do_t_branch): Move reloc setting to end of routine.

Index: bfd/elf32-arm.c
===================================================================
RCS file: /cvs/src/src/bfd/elf32-arm.c,v
retrieving revision 1.243
diff -c -3 -p -r1.243 elf32-arm.c
*** bfd/elf32-arm.c	1 Oct 2010 11:22:40 -0000	1.243
--- bfd/elf32-arm.c	6 Oct 2010 08:12:47 -0000
*************** static const insn_sequence elf32_arm_stu
*** 2106,2112 ****
     blx to reach the stub if necessary.  */
  static const insn_sequence elf32_arm_stub_long_branch_any_arm_pic[] =
    {
!     ARM_INSN(0xe59fc000),             /* ldr   r12, [pc] */
      ARM_INSN(0xe08ff00c),             /* add   pc, pc, ip */
      DATA_WORD(0, R_ARM_REL32, -4),    /* dcd   R_ARM_REL32(X-4) */
    };
--- 2106,2112 ----
     blx to reach the stub if necessary.  */
  static const insn_sequence elf32_arm_stub_long_branch_any_arm_pic[] =
    {
!     ARM_INSN(0xe59fc000),             /* ldr   ip, [pc] */
      ARM_INSN(0xe08ff00c),             /* add   pc, pc, ip */
      DATA_WORD(0, R_ARM_REL32, -4),    /* dcd   R_ARM_REL32(X-4) */
    };
*************** static const insn_sequence elf32_arm_stu
*** 2117,2123 ****
     ARMv7).  */
  static const insn_sequence elf32_arm_stub_long_branch_any_thumb_pic[] =
    {
!     ARM_INSN(0xe59fc004),             /* ldr   r12, [pc, #4] */
      ARM_INSN(0xe08fc00c),             /* add   ip, pc, ip */
      ARM_INSN(0xe12fff1c),             /* bx    ip */
      DATA_WORD(0, R_ARM_REL32, 0),     /* dcd   R_ARM_REL32(X) */
--- 2117,2123 ----
     ARMv7).  */
  static const insn_sequence elf32_arm_stub_long_branch_any_thumb_pic[] =
    {
!     ARM_INSN(0xe59fc004),             /* ldr   ip, [pc, #4] */
      ARM_INSN(0xe08fc00c),             /* add   ip, pc, ip */
      ARM_INSN(0xe12fff1c),             /* bx    ip */
      DATA_WORD(0, R_ARM_REL32, 0),     /* dcd   R_ARM_REL32(X) */
*************** arm_type_of_stub (struct bfd_link_info *
*** 3269,3277 ****
  
    /* If a stub is needed, record the actual destination type.  */
    if (stub_type != arm_stub_none)
!     {
!       *actual_st_type = st_type;
!     }
  
    return stub_type;
  }
--- 3269,3275 ----
  
    /* If a stub is needed, record the actual destination type.  */
    if (stub_type != arm_stub_none)
!     *actual_st_type = st_type;
  
    return stub_type;
  }
Index: gas/config/tc-arm.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-arm.c,v
retrieving revision 1.469
diff -c -3 -p -r1.469 tc-arm.c
*** gas/config/tc-arm.c	27 Sep 2010 09:47:05 -0000	1.469
--- gas/config/tc-arm.c	6 Oct 2010 08:12:55 -0000
*************** encode_branch (int default_reloc)
*** 7285,7293 ****
        inst.reloc.type  = BFD_RELOC_ARM_PLT32;
      }
    else
!     {
!       inst.reloc.type = (bfd_reloc_code_real_type) default_reloc;
!     }
    inst.reloc.pc_rel = 1;
  }
  
--- 7285,7291 ----
        inst.reloc.type  = BFD_RELOC_ARM_PLT32;
      }
    else
!     inst.reloc.type = (bfd_reloc_code_real_type) default_reloc;
    inst.reloc.pc_rel = 1;
  }
  
*************** do_t_branch (void)
*** 9666,9671 ****
--- 9664,9670 ----
  {
    int opcode;
    int cond;
+   int reloc;
  
    cond = inst.cond;
    set_it_insn_type (IF_INSIDE_IT_LAST_INSN);
*************** do_t_branch (void)
*** 9688,9716 ****
      {
        inst.instruction = THUMB_OP32(opcode);
        if (cond == COND_ALWAYS)
! 	inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH25;
        else
  	{
  	  gas_assert (cond != 0xF);
  	  inst.instruction |= cond << 22;
! 	  inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH20;
  	}
      }
    else
      {
        inst.instruction = THUMB_OP16(opcode);
        if (cond == COND_ALWAYS)
! 	inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12;
        else
  	{
  	  inst.instruction |= cond << 8;
! 	  inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9;
  	}
        /* Allow section relaxation.  */
        if (unified_syntax && inst.size_req != 2)
  	inst.relax = opcode;
      }
! 
    inst.reloc.pc_rel = 1;
  }
  
--- 9687,9715 ----
      {
        inst.instruction = THUMB_OP32(opcode);
        if (cond == COND_ALWAYS)
! 	reloc = BFD_RELOC_THUMB_PCREL_BRANCH25;
        else
  	{
  	  gas_assert (cond != 0xF);
  	  inst.instruction |= cond << 22;
! 	  reloc = BFD_RELOC_THUMB_PCREL_BRANCH20;
  	}
      }
    else
      {
        inst.instruction = THUMB_OP16(opcode);
        if (cond == COND_ALWAYS)
! 	reloc = BFD_RELOC_THUMB_PCREL_BRANCH12;
        else
  	{
  	  inst.instruction |= cond << 8;
! 	  reloc = BFD_RELOC_THUMB_PCREL_BRANCH9;
  	}
        /* Allow section relaxation.  */
        if (unified_syntax && inst.size_req != 2)
  	inst.relax = opcode;
      }
!   inst.reloc.type = reloc;
    inst.reloc.pc_rel = 1;
  }