diff -purNw --exclude=i386-tbl.h src/gas/testsuite/gas/i386/x86-64-sse5.d src-patch/gas/testsuite/gas/i386/x86-64-sse5.d
--- src/gas/testsuite/gas/i386/x86-64-sse5.d	2007-09-14 13:21:08.000000000 -0500
+++ src-patch/gas/testsuite/gas/i386/x86-64-sse5.d	2008-04-14 14:50:18.043145000 -0500
@@ -2838,4 +2838,7 @@ Disassembly of section .text:
 [ 	]+48c8:[ 	]+41 0f 7a 30 8f 00 00 10 00[ 	]+cvtph2ps 0x100000\(%r15\),%xmm1
 [ 	]+48d1:[ 	]+0f 7a 31 d1[ 	]+cvtps2ph %xmm2,%xmm1
 [ 	]+48d5:[ 	]+41 0f 7a 31 8f 00 00 10 00[ 	]+cvtps2ph %xmm1,0x100000\(%r15\)
-[ 	]+48de:[ 	]+c3[ 	]+retq[ 	]*
+[ 	]+48de:[ 	]+0f 7b 40 41 04 04[ 	]+protb[ 	]+\$0x4,0x4\(%rcx\),%xmm0
+[ 	]+48e4:[ 	]+41 0f 7b 41 42 08 01[ 	]+protw[ 	]+\$0x1,0x8\(%r10\),%xmm0
+[ 	]+48eb:[ 	]+41 0f 7b 43 41 04 03[ 	]+protq[ 	]+\$0x3,0x4\(%r9\),%xmm0
+[ 	]+48f2:[ 	]+c3[ 	]+retq[ 	]*
diff -purNw --exclude=i386-tbl.h src/gas/testsuite/gas/i386/x86-64-sse5.s src-patch/gas/testsuite/gas/i386/x86-64-sse5.s
--- src/gas/testsuite/gas/i386/x86-64-sse5.s	2007-09-14 13:21:08.000000000 -0500
+++ src-patch/gas/testsuite/gas/i386/x86-64-sse5.s	2008-04-14 14:46:30.172195000 -0500
@@ -2966,5 +2966,9 @@ foo:
 	cvtps2ph        %xmm2, %xmm1
 	cvtps2ph        %xmm1, 0x100000(%r15)
 
+	protb           $0x4, 0x4(%rdx), %xmm1
+	protw		$0x1, 0x8(%r14), %xmm2
+	protq		$0x3, 0x4(%r15), %xmm1
+	
 	ret
 	.size	foo, .-foo
diff -purNw --exclude=i386-tbl.h src/opcodes/i386-opc.tbl src-patch/opcodes/i386-opc.tbl
--- src/opcodes/i386-opc.tbl	2008-04-07 12:35:12.000000000 -0500
+++ src-patch/opcodes/i386-opc.tbl	2008-04-14 13:04:52.167357000 -0500
@@ -2523,13 +2523,13 @@ pperm, 4, 0x0f2423, None, 3, CpuSSE5, No
 permps, 4, 0x0f2420, None, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
 permpd, 4, 0x0f2421, None, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
 protb, 3, 0x0f2440, None, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
-protb, 3, 0x0f7b40, 0x0, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm,            { Imm8,            RegXMM,          RegXMM }
+protb, 3, 0x0f7b40, 0x0, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm, { Imm8, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
 protw, 3, 0x0f2441, None, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
-protw, 3, 0x0f7b41, 0x0, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm,            { Imm8,            RegXMM,          RegXMM }
+protw, 3, 0x0f7b41, 0x0, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm, { Imm8, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
 protd, 3, 0x0f2442, None, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
-protd, 3, 0x0f7b42, 0x0, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm,            { Imm8,            RegXMM,          RegXMM }
+protd, 3, 0x0f7b42, 0x0, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm, { Imm8,  RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
 protq, 3, 0x0f2443, None, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
-protq, 3, 0x0f7b43, 0x0, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm,            { Imm8,            RegXMM,          RegXMM }
+protq, 3, 0x0f7b43, 0x0, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm, { Imm8, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
 pshlb, 3, 0x0f2444, None, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
 pshlw, 3, 0x0f2445, None, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
 pshld, 3, 0x0f2446, None, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }