Index: gas/testsuite/gas/mips/mips.exp
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips.exp,v
retrieving revision 1.129
diff -u -p -r1.129 mips.exp
--- gas/testsuite/gas/mips/mips.exp	24 Sep 2007 22:08:21 -0000	1.129
+++ gas/testsuite/gas/mips/mips.exp	4 Oct 2007 07:31:31 -0000
@@ -775,4 +775,5 @@ if { [istarget mips*-*-vxworks*] } {
 
     run_dump_test "noreorder"
     run_dump_test "align"
+    run_dump_test "odd-float"
 }
Index: gas/testsuite/gas/mips/odd-float.d
===================================================================
RCS file: gas/testsuite/gas/mips/odd-float.d
diff -N gas/testsuite/gas/mips/odd-float.d
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/mips/odd-float.d	4 Oct 2007 07:31:31 -0000
@@ -0,0 +1,10 @@
+#objdump: -dr --prefix-addresses
+#name: MIPS odd float
+#as: -32 -march=sb1 -EL --fatal-warnings
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+00 <[^>]*> lwxc1	\$f1,a0\(a1\)
+0+04 <[^>]*> swxc1	\$f3,a0\(a1\)
+	...
Index: gas/testsuite/gas/mips/odd-float.s
===================================================================
RCS file: gas/testsuite/gas/mips/odd-float.s
diff -N gas/testsuite/gas/mips/odd-float.s
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/mips/odd-float.s	4 Oct 2007 07:31:31 -0000
@@ -0,0 +1,6 @@
+# Source file used to test operations on odd numbered floating point
+# registers.
+
+text_label:
+	lwxc1	$f1,$4($5)
+	swxc1	$f3,$4($5)
Index: opcodes/mips-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-opc.c,v
retrieving revision 1.61
diff -u -p -r1.61 mips-opc.c
--- opcodes/mips-opc.c	5 Jul 2007 09:49:02 -0000	1.61
+++ opcodes/mips-opc.c	4 Oct 2007 07:31:37 -0000
@@ -744,7 +744,7 @@ const struct mips_opcode mips_builtin_op
 {"fork",    "d,s,t",	0x7c000008, 0xfc0007ff, TRAP|WR_d|RD_s|RD_t,	0,		MT32	},
 {"lwu",     "t,o(b)",	0x9c000000, 0xfc000000,	LDD|RD_b|WR_t,		0,		I3	},
 {"lwu",     "t,A(b)",	0,    (int) M_LWU_AB,	INSN_MACRO,		0,		I3	},
-{"lwxc1",   "D,t(b)",	0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0,		I4|I33	},
+{"lwxc1",   "D,t(b)",	0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_S, 0,		I4|I33	},
 {"lwxs",    "d,t(b)",	0x70000088, 0xfc0007ff,	LDD|RD_b|RD_t|WR_d,	0,		SMT	},
 {"macc",    "d,s,t",	0x00000028, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,		N412    },
 {"macc",    "d,s,t",	0x00000158, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d,	0,		N5      },