diff -upNr binutils-old/gas/testsuite/gas/ppc/cell.d binutils/gas/testsuite/gas/ppc/cell.d --- binutils-old/gas/testsuite/gas/ppc/cell.d 1969-12-31 16:00:00.000000000 -0800 +++ binutils/gas/testsuite/gas/ppc/cell.d 2006-10-20 18:05:06.000000000 -0700 @@ -0,0 +1,31 @@ +#as: -mcell +#objdump: -dr -Mcell +#name: Cell tests + + +.*: +file format elf(32)?(64)?-powerpc.* + + +Disassembly of section \.text: + +0000000000000000 <.text>: + 0: 7c 01 14 0e lvlx v0,r1,r2 + 4: 7c 00 14 0e lvlx v0,0,r2 + 8: 7c 01 16 0e lvlxl v0,r1,r2 + c: 7c 00 16 0e lvlxl v0,0,r2 + 10: 7c 01 14 4e lvrx v0,r1,r2 + 14: 7c 00 14 4e lvrx v0,0,r2 + 18: 7c 01 16 4e lvrxl v0,r1,r2 + 1c: 7c 00 16 4e lvrxl v0,0,r2 + 20: 7c 01 15 0e stvlx v0,r1,r2 + 24: 7c 00 15 0e stvlx v0,0,r2 + 28: 7c 01 17 0e stvlxl v0,r1,r2 + 2c: 7c 00 17 0e stvlxl v0,0,r2 + 30: 7c 01 15 4e stvrx v0,r1,r2 + 34: 7c 00 15 4e stvrx v0,0,r2 + 38: 7c 01 17 4e stvrxl v0,r1,r2 + 3c: 7c 00 17 4e stvrxl v0,0,r2 + 40: 7c 00 0c 28 ldbrx r0,0,r1 + 44: 7c 01 14 28 ldbrx r0,r1,r2 + 48: 7c 00 0d 28 stdbrx r0,0,r1 + 4c: 7c 01 15 28 stdbrx r0,r1,r2 diff -upNr binutils-old/gas/testsuite/gas/ppc/cell.s binutils/gas/testsuite/gas/ppc/cell.s --- binutils-old/gas/testsuite/gas/ppc/cell.s 1969-12-31 16:00:00.000000000 -0800 +++ binutils/gas/testsuite/gas/ppc/cell.s 2006-10-20 18:05:06.000000000 -0700 @@ -0,0 +1,24 @@ + .section ".text" + lvlx %r0, %r1, %r2 + lvlx %r0, 0, %r2 + lvlxl %r0, %r1, %r2 + lvlxl %r0, 0, %r2 + lvrx %r0, %r1, %r2 + lvrx %r0, 0, %r2 + lvrxl %r0, %r1, %r2 + lvrxl %r0, 0, %r2 + + stvlx %r0, %r1, %r2 + stvlx %r0, 0, %r2 + stvlxl %r0, %r1, %r2 + stvlxl %r0, 0, %r2 + stvrx %r0, %r1, %r2 + stvrx %r0, 0, %r2 + stvrxl %r0, %r1, %r2 + stvrxl %r0, 0, %r2 + + ldbrx %r0, 0, %r1 + ldbrx %r0, %r1, %r2 + + stdbrx %r0, 0, %r1 + stdbrx %r0, %r1, %r2 Index: gas/config/tc-ppc.c =================================================================== RCS file: /cvs/src/src/gas/config/tc-ppc.c,v retrieving revision 1.114 diff -u -p -r1.114 tc-ppc.c --- gas/config/tc-ppc.c 22 Sep 2006 13:54:06 -0000 1.114 +++ gas/config/tc-ppc.c 23 Oct 2006 23:23:59 -0000 @@ -920,6 +920,12 @@ parse_cpu (const char *arg) | PPC_OPCODE_64 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6); } + else if (strcmp (arg, "cell") == 0) + { + ppc_cpu = (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC + | PPC_OPCODE_64 | PPC_OPCODE_POWER4 + | PPC_OPCODE_CELL); + } /* -mcom means assemble for the common intersection between Power and PowerPC. At present, we just allow the union, rather than the intersection. */ @@ -1116,6 +1122,7 @@ PowerPC options:\n\ -mpower4 generate code for Power4 architecture\n\ -mpower5 generate code for Power5 architecture\n\ -mpower6 generate code for Power6 architecture\n\ +-mcell generate code for Cell Broadband Engine architecture\n\ -mcom generate code Power/PowerPC common instructions\n\ -many generate code for any architecture (PWR/PWRX/PPC)\n")); fprintf (stream, _("\ Index: gas/doc/c-ppc.texi =================================================================== RCS file: /cvs/src/src/gas/doc/c-ppc.texi,v retrieving revision 1.9 diff -u -p -r1.9 c-ppc.texi --- gas/doc/c-ppc.texi 24 Jul 2006 13:49:49 -0000 1.9 +++ gas/doc/c-ppc.texi 23 Oct 2006 23:23:59 -0000 @@ -82,6 +82,9 @@ Generate code for Power5 architecture. @item -mpower6 Generate code for Power6 architecture. +@item -mcell +Generate code for Cell Broadband Engine architecture. + @item -mcom Generate code Power/PowerPC common instructions. Index: gas/testsuite/gas/ppc/ppc.exp =================================================================== RCS file: /cvs/src/src/gas/testsuite/gas/ppc/ppc.exp,v retrieving revision 1.11 diff -u -p -r1.11 ppc.exp --- gas/testsuite/gas/ppc/ppc.exp 21 Nov 2003 15:05:55 -0000 1.11 +++ gas/testsuite/gas/ppc/ppc.exp 23 Oct 2006 23:24:00 -0000 @@ -11,6 +11,7 @@ if { [istarget powerpc64*-*-*] || [istar run_dump_test "astest2_64" run_dump_test "test1elf64" run_dump_test "power4" + run_dump_test "cell" } elseif { [istarget powerpc*-*aix*] } then { run_dump_test "test1xcoff32" } elseif { [istarget powerpc*-*-*bsd*] \ Index: include/opcode/ppc.h =================================================================== RCS file: /cvs/src/src/include/opcode/ppc.h,v retrieving revision 1.22 diff -u -p -r1.22 ppc.h --- include/opcode/ppc.h 7 Jun 2006 05:23:59 -0000 1.22 +++ include/opcode/ppc.h 23 Oct 2006 23:24:02 -0000 @@ -143,6 +143,8 @@ extern const int powerpc_num_opcodes; /* Opcode is only supported by Power6 architecture. */ #define PPC_OPCODE_POWER6 0x4000000 +/* Opcode is only supported by PowerPC Cell family. */ +#define PPC_OPCODE_CELL 0x8000000 /* A macro to extract the major opcode from an instruction. */ #define PPC_OP(i) (((i) >> 26) & 0x3f) Index: opcodes/ppc-dis.c =================================================================== RCS file: /cvs/src/src/opcodes/ppc-dis.c,v retrieving revision 1.23 diff -u -p -r1.23 ppc-dis.c --- opcodes/ppc-dis.c 7 Jun 2006 05:23:59 -0000 1.23 +++ opcodes/ppc-dis.c 23 Oct 2006 23:24:02 -0000 @@ -74,6 +74,10 @@ powerpc_dialect (struct disassemble_info dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5; if (info->disassembler_options + && strstr (info->disassembler_options, "cell") != NULL) + dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC; + + if (info->disassembler_options && strstr (info->disassembler_options, "power6") != NULL) dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC; Index: opcodes/ppc-opc.c =================================================================== RCS file: /cvs/src/src/opcodes/ppc-opc.c,v retrieving revision 1.85 diff -u -p -r1.85 ppc-opc.c --- opcodes/ppc-opc.c 15 Nov 2005 21:33:04 -0000 1.85 +++ opcodes/ppc-opc.c 23 Oct 2006 23:24:03 -0000 @@ -1823,6 +1823,7 @@ extract_tbr (unsigned long insn, #define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM #define POWER4 PPC_OPCODE_POWER4 #define POWER5 PPC_OPCODE_POWER5 +#define CELL PPC_OPCODE_CELL #define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC #define PPC403 PPC_OPCODE_403 @@ -3014,7 +3015,7 @@ const struct powerpc_opcode powerpc_opco { "crand", XL(19,257), XL_MASK, COM, { BT, BA, BB } }, -{ "hrfid", XL(19,274), 0xffffffff, POWER5, { 0 } }, +{ "hrfid", XL(19,274), 0xffffffff, POWER5 | CELL, { 0 } }, { "crset", XL(19,289), XL_MASK, PPCCOM, { BT, BAT, BBA } }, { "creqv", XL(19,289), XL_MASK, COM, { BT, BA, BB } }, @@ -4206,6 +4207,8 @@ const struct powerpc_opcode powerpc_opco { "clcs", X(31,531), XRB_MASK, M601, { RT, RA } }, +{ "ldbrx", X(31,532), X_MASK, CELL, { RT, RA0, RB } }, + { "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA0, RB } }, { "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB } }, @@ -4265,6 +4268,8 @@ const struct powerpc_opcode powerpc_opco { "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } }, +{ "stdbrx", X(31,660), X_MASK, CELL, { RS, RA0, RB } }, + { "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA0, RB } }, { "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA0, RB } }, @@ -4423,6 +4428,16 @@ const struct powerpc_opcode powerpc_opco { "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } }, { "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } }, +/* New load/store left/right index vector instructions that are in the Cell only. */ +{ "lvlx", X(31, 519), X_MASK, CELL, { VD, RA0, RB } }, +{ "lvlxl", X(31, 775), X_MASK, CELL, { VD, RA0, RB } }, +{ "lvrx", X(31, 551), X_MASK, CELL, { VD, RA0, RB } }, +{ "lvrxl", X(31, 807), X_MASK, CELL, { VD, RA0, RB } }, +{ "stvlx", X(31, 647), X_MASK, CELL, { VS, RA0, RB } }, +{ "stvlxl", X(31, 903), X_MASK, CELL, { VS, RA0, RB } }, +{ "stvrx", X(31, 679), X_MASK, CELL, { VS, RA0, RB } }, +{ "stvrxl", X(31, 935), X_MASK, CELL, { VS, RA0, RB } }, + { "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA0 } }, { "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA0 } },