Index: bfd/bfd-in2.h
===================================================================
RCS file: /var/cvsroot/src-cvs/src/bfd/bfd-in2.h,v
retrieving revision 1.353
diff -u -p -r1.353 bfd-in2.h
--- bfd/bfd-in2.h	18 Jul 2005 14:13:34 -0000	1.353
+++ bfd/bfd-in2.h	21 Jul 2005 22:18:56 -0000
@@ -2837,7 +2837,8 @@ pc-relative or some form of GOT-indirect
   BFD_RELOC_ARM_IMMEDIATE,
   BFD_RELOC_ARM_ADRL_IMMEDIATE,
   BFD_RELOC_ARM_T32_IMMEDIATE,
   BFD_RELOC_ARM_T32_IMM12,
+  BFD_RELOC_ARM_T32_ADD_PC12,
   BFD_RELOC_ARM_SHIFT_IMM,
   BFD_RELOC_ARM_SMI,
   BFD_RELOC_ARM_SWI,
Index: bfd/libbfd.h
===================================================================
RCS file: /var/cvsroot/src-cvs/src/bfd/libbfd.h,v
retrieving revision 1.151
diff -u -p -r1.151 libbfd.h
--- bfd/libbfd.h	18 Jul 2005 14:13:35 -0000	1.151
+++ bfd/libbfd.h	21 Jul 2005 22:18:56 -0000
@@ -1211,7 +1211,8 @@ static const char *const bfd_reloc_code_
   "BFD_RELOC_ARM_IMMEDIATE",
   "BFD_RELOC_ARM_ADRL_IMMEDIATE",
   "BFD_RELOC_ARM_T32_IMMEDIATE",
   "BFD_RELOC_ARM_T32_IMM12",
+  "BFD_RELOC_ARM_T32_ADD_PC12",
   "BFD_RELOC_ARM_SHIFT_IMM",
   "BFD_RELOC_ARM_SMI",
   "BFD_RELOC_ARM_SWI",
Index: bfd/reloc.c
===================================================================
RCS file: /var/cvsroot/src-cvs/src/bfd/reloc.c,v
retrieving revision 1.132
diff -u -p -r1.132 reloc.c
--- bfd/reloc.c	18 Jul 2005 14:13:36 -0000	1.132
+++ bfd/reloc.c	21 Jul 2005 22:18:43 -0000
@@ -2736,8 +2736,10 @@ ENUMX
 ENUMX
   BFD_RELOC_ARM_T32_IMMEDIATE
 ENUMX
   BFD_RELOC_ARM_T32_IMM12
 ENUMX
+  BFD_RELOC_ARM_T32_ADD_PC12
+ENUMX
   BFD_RELOC_ARM_SHIFT_IMM
 ENUMX
   BFD_RELOC_ARM_SMI
Index: gas/config/tc-arm.c
===================================================================
RCS file: /var/cvsroot/src-cvs/src/gas/config/tc-arm.c,v
retrieving revision 1.213
diff -u -p -r1.213 tc-arm.c
--- gas/config/tc-arm.c	21 Jul 2005 13:11:24 -0000	1.213
+++ gas/config/tc-arm.c	22 Jul 2005 14:05:18 -0000
@@ -5694,6 +5748,7 @@ encode_thumb32_addr_mode (int i, bfd_boo
   X(adcs,  4140, eb500000),			\
   X(add,   1c00, eb000000),			\
   X(adds,  1c00, eb100000),			\
+  X(adr,   000f, f20f0000),			\
   X(and,   4000, ea000000),			\
   X(ands,  4000, ea100000),			\
   X(asr,   1000, fa40f000),			\
@@ -5727,8 +5782,8 @@ encode_thumb32_addr_mode (int i, bfd_boo
   X(negs,  4240, f1d00000), /* rsbs #0 */	\
   X(orr,   4300, ea400000),			\
   X(orrs,  4300, ea500000),			\
-  X(pop,   bc00, e8ad0000), /* ldmia sp!,... */	\
-  X(push,  b400, e8bd0000), /* stmia sp!,... */	\
+  X(pop,   bc00, e8bd0000), /* ldmia sp!,... */	\
+  X(push,  b400, e92d0000), /* stmdb sp!,... */	\
   X(rev,   ba00, fa90f080),			\
   X(rev16, ba40, fa90f090),			\
   X(revsh, bac0, fa90f0b0),			\
@@ -5895,11 +5964,24 @@ do_t_add_sub (void)
 static void
 do_t_adr (void)
 {
-  inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
-  inst.reloc.exp.X_add_number -= 4; /* PC relative adjust.  */
-  inst.reloc.pc_rel = 1;
+  if (unified_syntax && inst.size_req != 2)
+    {
+      /* Always generate a 32-bit opcode;
+	 section relaxation will shrink it later if possible.  */
+      inst.instruction = THUMB_OP32 (inst.instruction);
+      inst.instruction |= inst.operands[0].reg << 8;
+      inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12;
+      inst.reloc.pc_rel = 1;
+    }
+  else
+    {
+      inst.instruction = THUMB_OP16 (inst.instruction);
+      inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
+      inst.reloc.exp.X_add_number -= 4; /* PC relative adjust.  */
+      inst.reloc.pc_rel = 1;
 
-  inst.instruction |= inst.operands[0].reg << 4;
+      inst.instruction |= inst.operands[0].reg << 4;
+    }
 }
 
 /* Arithmetic instructions for which there is just one 16-bit
@@ -6880,39 +6962,52 @@ do_t_pld (void)
 static void
 do_t_push_pop (void)
 {
+  unsigned mask;
+  
   constraint (inst.operands[0].writeback,
 	      _("push/pop do not support {reglist}^"));
   constraint (inst.reloc.type != BFD_RELOC_UNUSED,
 	      _("expression too complex"));
 
-  if ((inst.operands[0].imm & ~0xff) == 0)
+  mask = inst.operands[0].imm;
+  if ((mask & ~0xff) == 0)
     inst.instruction = THUMB_OP16 (inst.instruction);
   else if ((inst.instruction == T_MNEM_push
-	    && (inst.operands[0].imm & ~0xff) == 1 << REG_LR)
+	    && (mask & ~0xff) == 1 << REG_LR)
 	   || (inst.instruction == T_MNEM_pop
-	       && (inst.operands[0].imm & ~0xff) == 1 << REG_PC))
+	       && (mask & ~0xff) == 1 << REG_PC))
     {
       inst.instruction = THUMB_OP16 (inst.instruction);
       inst.instruction |= THUMB_PP_PC_LR;
-      inst.operands[0].imm &= 0xff;
+      mask &= 0xff;
     }
   else if (unified_syntax)
     {
-      if (inst.operands[1].imm & (1 << 13))
-	as_warn (_("SP should not be in register list"));
+      if (mask & (1 << 13))
+	inst.error =  _("SP not allowed in register list");
       if (inst.instruction == T_MNEM_push)
 	{
-	  if (inst.operands[1].imm & (1 << 15))
-	    as_warn (_("PC should not be in register list"));
+	  if (mask & (1 << 15))
+	    inst.error = _("PC not allowed in register list");
 	}
       else
 	{
-	  if (inst.operands[1].imm & (1 << 14)
-	      && inst.operands[1].imm & (1 << 15))
-	    as_warn (_("LR and PC should not both be in register list"));
+	  if (mask & (1 << 14)
+	      && mask & (1 << 15))
+	    inst.error = _("LR and PC should not both be in register list");
+	}
+      if ((mask & (mask - 1)) == 0)
+	{
+	  /* Single register push/pop implemented as str/ldr.  */
+	  if (inst.instruction == T_MNEM_push)
+	    inst.instruction = 0xf84d0d04; /* str reg, [sp, #-4]! */
+	  else
+	    inst.instruction = 0xf85d0b04; /* ldr reg, [sp], #4 */
+	  mask = ffs(mask) - 1;
+	  mask <<= 12;
 	}
-
-      inst.instruction = THUMB_OP32 (inst.instruction);
+      else
+	inst.instruction = THUMB_OP32 (inst.instruction);
     }
   else
     {
@@ -6920,7 +7015,7 @@ do_t_push_pop (void)
       return;
     }
 
-  inst.instruction |= inst.operands[0].imm;
+  inst.instruction |= mask;
 }
 
 static void
@@ -8122,7 +8232,7 @@ static const struct asm_opcode insns[] =
  TCE(bl,	b000000, f000f800, 1, (EXPr),	     branch, t_branch23),
 
   /* Pseudo ops.  */
- TCE(adr,	28f0000, 000f,	   2, (RR, EXP),     adr,  t_adr),
+ tCE(adr,	28f0000, adr,	   2, (RR, EXP),     adr,  t_adr),
   C3(adrl,	28f0000,           2, (RR, EXP),     adrl),
  tCE(nop,	1a00000, nop,	   1, (oI255c),	     nop,  t_nop),
 
@@ -9918,6 +10037,7 @@ md_pcrel_from_section (fixS * fixP, segT
 
     case BFD_RELOC_ARM_THUMB_OFFSET:
     case BFD_RELOC_ARM_T32_OFFSET_IMM:
+    case BFD_RELOC_ARM_T32_ADD_PC12:
       return (base + 4) & ~3;
 
       /* Thumb branches are simply offset by +4.  */
@@ -10439,7 +10559,8 @@ md_apply_fix (fixS *	fixP,
       break;
 
     case BFD_RELOC_ARM_T32_IMMEDIATE:
     case BFD_RELOC_ARM_T32_IMM12:
+    case BFD_RELOC_ARM_T32_ADD_PC12:
       /* We claim that this fixup has been processed here,
 	 even if in fact we generate an error because we do
 	 not have a reloc for it, so tc_gen_reloc will reject it.  */
@@ -10457,17 +10579,23 @@ md_apply_fix (fixS *	fixP,
       newval <<= 16;
       newval |= md_chars_to_number (buf+2, THUMB_SIZE);
 
-      if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMM12)
-	{
-	  if (value > 0xfff)
-	    newimm = (unsigned int) FAIL;
-	  else
-	    newimm = value;
-	}
-      else
-	newimm = encode_thumb32_immediate (value);
-
       /* FUTURE: Implement analogue of negate_data_op for T32.  */
+      if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE)
+	newimm = encode_thumb32_immediate (value);
+      else
+	{
+	  /* 12 bit immediate for addw/subw.  */
+	  if (value < 0)
+	    {
+	      value = -value;
+	      newval ^= 0x00a00000;
+	    }
+	  if (value > 0xfff)
+	    newimm = (unsigned int) FAIL;
+	  else
+	    newimm = value;
+	}
+
       if (newimm == (unsigned int)FAIL)
 	{
 	  as_bad_where (fixP->fx_file, fixP->fx_line,
Index: gas/testsuite/gas/arm/thumb32.d
===================================================================
RCS file: /var/cvsroot/src-cvs/src/gas/testsuite/gas/arm/thumb32.d,v
retrieving revision 1.7
diff -u -p -r1.7 thumb32.d
--- gas/testsuite/gas/arm/thumb32.d	21 Jul 2005 13:11:28 -0000	1.7
+++ gas/testsuite/gas/arm/thumb32.d	22 Jul 2005 14:06:22 -0000
@@ -500,10 +500,10 @@ Disassembly of section .text:
 0+59a <[^>]+> f895 1000 	ldrb\.w	r1, \[r5\]
 0+59e <[^>]+> f895 1330 	ldrb\.w	r1, \[r5, #816\]
 0+5a2 <[^>]+> f815 1c30 	ldrb\.w	r1, \[r5, #-48\]
-0+5a6 <[^>]+> f815 1b30 	ldrb\.w	r1, \[r5, #48\]!
-0+5aa <[^>]+> f815 1930 	ldrb\.w	r1, \[r5, #-48\]!
-0+5ae <[^>]+> f815 1f30 	ldrb\.w	r1, \[r5\], #48
-0+5b2 <[^>]+> f815 1d30 	ldrb\.w	r1, \[r5\], #-48
+0+5a6 <[^>]+> f815 1b30 	ldrb\.w	r1, \[r5\], #48
+0+5aa <[^>]+> f815 1930 	ldrb\.w	r1, \[r5\], #-48
+0+5ae <[^>]+> f815 1f30 	ldrb\.w	r1, \[r5, #48\]!
+0+5b2 <[^>]+> f815 1d30 	ldrb\.w	r1, \[r5, #-48\]!
 0+5b6 <[^>]+> 5d29      	ldrb	r1, \[r5, r4\]
 0+5b8 <[^>]+> f819 100c 	ldrb\.w	r1, \[r9, ip\]
 0+5bc <[^>]+> f89f 10ac 	ldrb\.w	r1, \[pc, #172\]	; 0+66c <[^>]+>
@@ -511,10 +511,10 @@ Disassembly of section .text:
 0+5c4 <[^>]+> f995 1000 	ldrsb\.w	r1, \[r5\]
 0+5c8 <[^>]+> f995 1330 	ldrsb\.w	r1, \[r5, #816\]
 0+5cc <[^>]+> f915 1c30 	ldrsb\.w	r1, \[r5, #-48\]
-0+5d0 <[^>]+> f915 1b30 	ldrsb\.w	r1, \[r5, #48\]!
-0+5d4 <[^>]+> f915 1930 	ldrsb\.w	r1, \[r5, #-48\]!
-0+5d8 <[^>]+> f915 1f30 	ldrsb\.w	r1, \[r5\], #48
-0+5dc <[^>]+> f915 1d30 	ldrsb\.w	r1, \[r5\], #-48
+0+5d0 <[^>]+> f915 1b30 	ldrsb\.w	r1, \[r5\], #48
+0+5d4 <[^>]+> f915 1930 	ldrsb\.w	r1, \[r5\], #-48
+0+5d8 <[^>]+> f915 1f30 	ldrsb\.w	r1, \[r5, #48\]!
+0+5dc <[^>]+> f915 1d30 	ldrsb\.w	r1, \[r5, #-48\]!
 0+5e0 <[^>]+> 5729      	ldrsb	r1, \[r5, r4\]
 0+5e2 <[^>]+> f919 100c 	ldrsb\.w	r1, \[r9, ip\]
 0+5e6 <[^>]+> f99f 1084 	ldrsb\.w	r1, \[pc, #132\]	; 0+66c <[^>]+>
@@ -522,10 +522,10 @@ Disassembly of section .text:
 0+5ee <[^>]+> f8b5 1000 	ldrh\.w	r1, \[r5\]
 0+5f2 <[^>]+> f8b5 1330 	ldrh\.w	r1, \[r5, #816\]
 0+5f6 <[^>]+> f835 1c30 	ldrh\.w	r1, \[r5, #-48\]
-0+5fa <[^>]+> f835 1b30 	ldrh\.w	r1, \[r5, #48\]!
-0+5fe <[^>]+> f835 1930 	ldrh\.w	r1, \[r5, #-48\]!
-0+602 <[^>]+> f835 1f30 	ldrh\.w	r1, \[r5\], #48
-0+606 <[^>]+> f835 1d30 	ldrh\.w	r1, \[r5\], #-48
+0+5fa <[^>]+> f835 1b30 	ldrh\.w	r1, \[r5\], #48
+0+5fe <[^>]+> f835 1930 	ldrh\.w	r1, \[r5\], #-48
+0+602 <[^>]+> f835 1f30 	ldrh\.w	r1, \[r5, #48\]!
+0+606 <[^>]+> f835 1d30 	ldrh\.w	r1, \[r5, #-48\]!
 0+60a <[^>]+> 5b29      	ldrh	r1, \[r5, r4\]
 0+60c <[^>]+> f839 100c 	ldrh\.w	r1, \[r9, ip\]
 0+610 <[^>]+> f8bf 1058 	ldrh\.w	r1, \[pc, #88\]	; 0+66c <[^>]+>
@@ -533,10 +533,10 @@ Disassembly of section .text:
 0+618 <[^>]+> f9b5 1000 	ldrsh\.w	r1, \[r5\]
 0+61c <[^>]+> f9b5 1330 	ldrsh\.w	r1, \[r5, #816\]
 0+620 <[^>]+> f935 1c30 	ldrsh\.w	r1, \[r5, #-48\]
-0+624 <[^>]+> f935 1b30 	ldrsh\.w	r1, \[r5, #48\]!
-0+628 <[^>]+> f935 1930 	ldrsh\.w	r1, \[r5, #-48\]!
-0+62c <[^>]+> f935 1f30 	ldrsh\.w	r1, \[r5\], #48
-0+630 <[^>]+> f935 1d30 	ldrsh\.w	r1, \[r5\], #-48
+0+624 <[^>]+> f935 1b30 	ldrsh\.w	r1, \[r5\], #48
+0+628 <[^>]+> f935 1930 	ldrsh\.w	r1, \[r5\], #-48
+0+62c <[^>]+> f935 1f30 	ldrsh\.w	r1, \[r5, #48\]!
+0+630 <[^>]+> f935 1d30 	ldrsh\.w	r1, \[r5, #-48\]!
 0+634 <[^>]+> 5f29      	ldrsh	r1, \[r5, r4\]
 0+636 <[^>]+> f939 100c 	ldrsh\.w	r1, \[r9, ip\]
 0+63a <[^>]+> f9bf 1030 	ldrsh\.w	r1, \[pc, #48\]	; 0+66c <[^>]+>
@@ -544,10 +544,10 @@ Disassembly of section .text:
 0+642 <[^>]+> f8d5 1000 	ldr\.w	r1, \[r5\]
 0+646 <[^>]+> f8d5 1330 	ldr\.w	r1, \[r5, #816\]
 0+64a <[^>]+> f855 1c30 	ldr\.w	r1, \[r5, #-48\]
-0+64e <[^>]+> f855 1b30 	ldr\.w	r1, \[r5, #48\]!
-0+652 <[^>]+> f855 1930 	ldr\.w	r1, \[r5, #-48\]!
-0+656 <[^>]+> f855 1f30 	ldr\.w	r1, \[r5\], #48
-0+65a <[^>]+> f855 1d30 	ldr\.w	r1, \[r5\], #-48
+0+64e <[^>]+> f855 1b30 	ldr\.w	r1, \[r5\], #48
+0+652 <[^>]+> f855 1930 	ldr\.w	r1, \[r5\], #-48
+0+656 <[^>]+> f855 1f30 	ldr\.w	r1, \[r5, #48\]!
+0+65a <[^>]+> f855 1d30 	ldr\.w	r1, \[r5, #-48\]!
 0+65e <[^>]+> 5929      	ldr	r1, \[r5, r4\]
 0+660 <[^>]+> f859 100c 	ldr\.w	r1, \[r9, ip\]
 0+664 <[^>]+> f8df 1004 	ldr\.w	r1, \[pc, #4\]	; 0+66c <[^>]+>
@@ -555,10 +555,10 @@ Disassembly of section .text:
 0+66c <[^>]+> f885 1000 	strb\.w	r1, \[r5\]
 0+670 <[^>]+> f885 1330 	strb\.w	r1, \[r5, #816\]
 0+674 <[^>]+> f805 1c30 	strb\.w	r1, \[r5, #-48\]
-0+678 <[^>]+> f805 1b30 	strb\.w	r1, \[r5, #48\]!
-0+67c <[^>]+> f805 1930 	strb\.w	r1, \[r5, #-48\]!
-0+680 <[^>]+> f805 1f30 	strb\.w	r1, \[r5\], #48
-0+684 <[^>]+> f805 1d30 	strb\.w	r1, \[r5\], #-48
+0+678 <[^>]+> f805 1b30 	strb\.w	r1, \[r5\], #48
+0+67c <[^>]+> f805 1930 	strb\.w	r1, \[r5\], #-48
+0+680 <[^>]+> f805 1f30 	strb\.w	r1, \[r5, #48\]!
+0+684 <[^>]+> f805 1d30 	strb\.w	r1, \[r5, #-48\]!
 0+688 <[^>]+> 5529      	strb	r1, \[r5, r4\]
 0+68a <[^>]+> f809 100c 	strb\.w	r1, \[r9, ip\]
 0+68e <[^>]+> f88f 1086 	strb\.w	r1, \[pc, #134\]	; 0+716 <[^>]+>
@@ -566,10 +566,10 @@ Disassembly of section .text:
 0+696 <[^>]+> f8a5 1000 	strh\.w	r1, \[r5\]
 0+69a <[^>]+> f8a5 1330 	strh\.w	r1, \[r5, #816\]
 0+69e <[^>]+> f825 1c30 	strh\.w	r1, \[r5, #-48\]
-0+6a2 <[^>]+> f825 1b30 	strh\.w	r1, \[r5, #48\]!
-0+6a6 <[^>]+> f825 1930 	strh\.w	r1, \[r5, #-48\]!
-0+6aa <[^>]+> f825 1f30 	strh\.w	r1, \[r5\], #48
-0+6ae <[^>]+> f825 1d30 	strh\.w	r1, \[r5\], #-48
+0+6a2 <[^>]+> f825 1b30 	strh\.w	r1, \[r5\], #48
+0+6a6 <[^>]+> f825 1930 	strh\.w	r1, \[r5\], #-48
+0+6aa <[^>]+> f825 1f30 	strh\.w	r1, \[r5, #48\]!
+0+6ae <[^>]+> f825 1d30 	strh\.w	r1, \[r5, #-48\]!
 0+6b2 <[^>]+> 5329      	strh	r1, \[r5, r4\]
 0+6b4 <[^>]+> f829 100c 	strh\.w	r1, \[r9, ip\]
 0+6b8 <[^>]+> f8af 105a 	strh\.w	r1, \[pc, #90\]	; 0+716 <[^>]+>
@@ -577,10 +577,10 @@ Disassembly of section .text:
 0+6c0 <[^>]+> f8c5 1000 	str\.w	r1, \[r5\]
 0+6c4 <[^>]+> f8c5 1330 	str\.w	r1, \[r5, #816\]
 0+6c8 <[^>]+> f845 1c30 	str\.w	r1, \[r5, #-48\]
-0+6cc <[^>]+> f845 1b30 	str\.w	r1, \[r5, #48\]!
-0+6d0 <[^>]+> f845 1930 	str\.w	r1, \[r5, #-48\]!
-0+6d4 <[^>]+> f845 1f30 	str\.w	r1, \[r5\], #48
-0+6d8 <[^>]+> f845 1d30 	str\.w	r1, \[r5\], #-48
+0+6cc <[^>]+> f845 1b30 	str\.w	r1, \[r5\], #48
+0+6d0 <[^>]+> f845 1930 	str\.w	r1, \[r5\], #-48
+0+6d4 <[^>]+> f845 1f30 	str\.w	r1, \[r5, #48\]!
+0+6d8 <[^>]+> f845 1d30 	str\.w	r1, \[r5, #-48\]!
 0+6dc <[^>]+> 5129      	str	r1, \[r5, r4\]
 0+6de <[^>]+> f849 100c 	str\.w	r1, \[r9, ip\]
 0+6e2 <[^>]+> f8cf 1032 	str\.w	r1, \[pc, #50\]	; 0+716 <[^>]+>
@@ -588,10 +588,10 @@ Disassembly of section .text:
 0+6ea <[^>]+> f895 f000 	pld	\[r5\]
 0+6ee <[^>]+> f895 f330 	pld	\[r5, #816\]
 0+6f2 <[^>]+> f815 fc30 	pld	\[r5, #-48\]
-0+6f6 <[^>]+> f815 fb30 	pld	\[r5, #48\]!
-0+6fa <[^>]+> f815 f930 	pld	\[r5, #-48\]!
-0+6fe <[^>]+> f815 ff30 	pld	\[r5\], #48
-0+702 <[^>]+> f815 fd30 	pld	\[r5\], #-48
+0+6f6 <[^>]+> f815 fb30 	pld	\[r5\], #48
+0+6fa <[^>]+> f815 f930 	pld	\[r5\], #-48
+0+6fe <[^>]+> f815 ff30 	pld	\[r5, #48\]!
+0+702 <[^>]+> f815 fd30 	pld	\[r5, #-48\]!
 0+706 <[^>]+> f815 f000 	pld	\[r5, r0\]
 0+70a <[^>]+> f819 f000 	pld	\[r9, r0\]
 0+70e <[^>]+> f89f f006 	pld	\[pc, #6\]	; 0+716 <[^>]+>
@@ -758,8 +758,8 @@ Disassembly of section .text:
 0+956 <[^>]+> bc01      	pop	\{r0\}
 0+958 <[^>]+> b502      	push	\{r1, lr\}
 0+95a <[^>]+> bd02      	pop	\{r1, pc\}
-0+95c <[^>]+> e8bd 1f00 	ldmia\.w	sp!, \{r8, r9, sl, fp, ip\}
-0+960 <[^>]+> e8ad 1f00 	stmia\.w	sp!, \{r8, r9, sl, fp, ip\}
+0+95c <[^>]+> e92d 1f00 	stmdb	sp!, \{r8, r9, sl, fp, ip\}
+0+960 <[^>]+> e8bd 1f00 	ldmia\.w	sp!, \{r8, r9, sl, fp, ip\}
 0+964 <[^>]+> fa92 f113 	qadd16	r1, r2, r3
 0+968 <[^>]+> fa82 f113 	qadd8	r1, r2, r3
 0+96c <[^>]+> faa2 f113 	qaddsubx	r1, r2, r3
@@ -1011,11 +1011,13 @@ Disassembly of section .text:
 0+cf4 <[^>]+> f8df 1155 	ldr\.w	r1, \[pc, #341\]	; 0+e4d <[^>]+>
 0+cf8 <[^>]+> f85f 12aa 	ldr\.w	r1, \[pc, #-682\]	; 0+a52 <[^>]+>
 0+cfc <[^>]+> f85f 1155 	ldr\.w	r1, \[pc, #-341\]	; 0+bab <[^>]+>
 0+d00 <[^>]+> f200 0900 	addw	r9, r0, #0	; 0x0
 0+d04 <[^>]+> f60f 76ff 	addw	r6, pc, #4095	; 0xfff
 0+d08 <[^>]+> f6a9 2685 	subw	r6, r9, #2693	; 0xa85
 0+d0c <[^>]+> f2a9 567a 	subw	r6, r9, #1402	; 0x57a
 0+d10 <[^>]+> e8df f006 	tbb	\[pc, r6\]
 0+d14 <[^>]+> e8d0 f009 	tbb	\[r0, r9\]
 0+d18 <[^>]+> e8df f017 	tbh	\[pc, r7, lsl #1\]
 0+d1c <[^>]+> e8d0 f018 	tbh	\[r0, r8, lsl #1\]
+0+d20 <[^>]+> f84d 8d04 	str.w	r8, \[sp, #-4\]!
+0+d24 <[^>]+> f85d 8b04 	ldr.w	r8, \[sp\], #4
Index: gas/testsuite/gas/arm/thumb32.s
===================================================================
RCS file: /var/cvsroot/src-cvs/src/gas/testsuite/gas/arm/thumb32.s,v
retrieving revision 1.3
diff -u -p -r1.3 thumb32.s
--- gas/testsuite/gas/arm/thumb32.s	21 Jul 2005 13:11:28 -0000	1.3
+++ gas/testsuite/gas/arm/thumb32.s	22 Jul 2005 12:59:37 -0000
@@ -745,11 +745,14 @@ xta:	
 	ldpcimm	ldrh
 	ldpcimm	ldrsh
 	ldpcimm	ldr
 	addw r9, r0, #0
 	addw r6, pc, #0xfff
 	subw r6, r9, #0xa85
 	subw r6, r9, #0x57a
 	tbb [pc, r6]
 	tbb [r0, r9]
 	tbh [pc, r7, lsl #1]
 	tbh [r0, r8, lsl #1]
+
+	push	{r8}
+	pop	{r8}
Index: opcodes/arm-dis.c
===================================================================
RCS file: /var/cvsroot/src-cvs/src/opcodes/arm-dis.c,v
retrieving revision 1.50
diff -u -p -r1.50 arm-dis.c
--- opcodes/arm-dis.c	7 Jul 2005 19:27:48 -0000	1.50
+++ opcodes/arm-dis.c	22 Jul 2005 13:57:58 -0000
@@ -2253,22 +2253,22 @@ print_insn_thumb32 (bfd_vma pc, struct d
 		      offset = -i8;
 		      break;
 
-		    case 0xB:  /* 8-bit + preindex with wb */
+		    case 0xF:  /* 8-bit + preindex with wb */
 		      offset = i8;
 		      writeback = TRUE;
 		      break;
 
-		    case 0x9:  /* 8-bit - preindex with wb */
+		    case 0xD:  /* 8-bit - preindex with wb */
 		      offset = -i8;
 		      writeback = TRUE;
 		      break;
 
-		    case 0xF:  /* 8-bit + postindex */
+		    case 0xB:  /* 8-bit + postindex */
 		      offset = i8;
 		      postind = TRUE;
 		      break;
 
-		    case 0xD:  /* 8-bit - postindex */
+		    case 0x9:  /* 8-bit - postindex */
 		      offset = -i8;
 		      postind = TRUE;
 		      break;