? gas/doc/as.info
? gas/testsuite/gas/maxq10
? gas/testsuite/gas/maxq20
? ld/testsuite/ld-maxq
Index: config.sub
===================================================================
RCS file: /cvs/src/src/config.sub,v
retrieving revision 1.44.12.1
diff -c -3 -p -r1.44.12.1 config.sub
*** config.sub	9 Apr 2004 18:27:57 -0000	1.44.12.1
--- config.sub	2 Nov 2004 13:51:28 -0000
*************** case $basic_machine in
*** 237,244 ****
  	| h8300 | h8500 | hppa | hppa1.[01] | hppa2.0 | hppa2.0[nw] | hppa64 \
  	| i370 | i860 | i960 | ia64 \
  	| ip2k | iq2000 \
! 	| m32r | m68000 | m68k | m88k | mcore \
! 	| mips | mipsbe | mipseb | mipsel | mipsle \
  	| mips16 \
  	| mips64 | mips64el \
  	| mips64vr | mips64vrel \
--- 237,244 ----
  	| h8300 | h8500 | hppa | hppa1.[01] | hppa2.0 | hppa2.0[nw] | hppa64 \
  	| i370 | i860 | i960 | ia64 \
  	| ip2k | iq2000 \
! 	| m32r | m68000 | m68k | m88k | maxq |mcore \
! 	| mips | mipsbe | mipseb | mipsel | mi:/psle \
  	| mips16 \
  	| mips64 | mips64el \
  	| mips64vr | mips64vrel \
*************** case $basic_machine in
*** 311,317 ****
  	| m32r-* \
  	| m68000-* | m680[012346]0-* | m68360-* | m683?2-* | m68k-* \
  	| m88110-* | m88k-* | mcore-* \
! 	| mips-* | mipsbe-* | mipseb-* | mipsel-* | mipsle-* \
  	| mips16-* \
  	| mips64-* | mips64el-* \
  	| mips64vr-* | mips64vrel-* \
--- 311,317 ----
  	| m32r-* \
  	| m68000-* | m680[012346]0-* | m68360-* | m683?2-* | m68k-* \
  	| m88110-* | m88k-* | mcore-* \
! 	| maxq-* | mips-* | mipsbe-* | mipseb-* | mipsel-* | mipsle-* \
  	| mips16-* \
  	| mips64-* | mips64el-* \
  	| mips64vr-* | mips64vrel-* \
*************** case $basic_machine in
*** 630,635 ****
--- 630,639 ----
  	m88k-omron*)
  		basic_machine=m88k-omron
  		;;
+ 
+ 	maxq)	
+ 		basic_machine=maxq
+ 		;;
  	magnum | m3230)
  		basic_machine=mips-mips
  		os=-sysv
Index: bfd/archures.c
===================================================================
RCS file: /cvs/src/src/bfd/archures.c,v
retrieving revision 1.88
diff -c -3 -p -r1.88 archures.c
*** bfd/archures.c	3 Dec 2003 17:38:48 -0000	1.88
--- bfd/archures.c	2 Nov 2004 13:51:31 -0000
*************** extern const bfd_arch_info_type bfd_m68h
*** 394,399 ****
--- 394,400 ----
  extern const bfd_arch_info_type bfd_m68hc12_arch;
  extern const bfd_arch_info_type bfd_m68k_arch;
  extern const bfd_arch_info_type bfd_m88k_arch;
+ extern const bfd_arch_info_type bfd_maxq_arch;
  extern const bfd_arch_info_type bfd_mcore_arch;
  extern const bfd_arch_info_type bfd_mips_arch;
  extern const bfd_arch_info_type bfd_mmix_arch;
*************** static const bfd_arch_info_type * const 
*** 454,459 ****
--- 455,461 ----
      &bfd_m68hc12_arch,
      &bfd_m68k_arch,
      &bfd_m88k_arch,
+     &bfd_maxq_arch,
      &bfd_mcore_arch,
      &bfd_mips_arch,
      &bfd_mmix_arch,
Index: bfd/bfd-in2.h
===================================================================
RCS file: /cvs/src/src/bfd/bfd-in2.h,v
retrieving revision 1.257.2.3
diff -c -3 -p -r1.257.2.3 bfd-in2.h
*** bfd/bfd-in2.h	8 Apr 2004 13:07:53 -0000	1.257.2.3
--- bfd/bfd-in2.h	2 Nov 2004 13:51:32 -0000
*************** enum bfd_architecture
*** 1728,1733 ****
--- 1728,1734 ----
  #define bfd_mach_msp44          44
    bfd_arch_xtensa,    /* Tensilica's Xtensa cores.  */
  #define bfd_mach_xtensa        1
+   bfd_arch_maxq,     /* Dallas MAXQ 10/20 */
    bfd_arch_last
    };
  
Index: bfd/coff-maxq.c
===================================================================
RCS file: bfd/coff-maxq.c
diff -N bfd/coff-maxq.c
*** /dev/null	1 Jan 1970 00:00:00 -0000
--- bfd/coff-maxq.c	2 Nov 2004 13:51:32 -0000
***************
*** 0 ****
--- 1,509 ----
+ /* BFD back-end for MAXQ COFF binaries. Copyright 2003, 2004
+ 
+    Contributed by Vineet Sharma (vineets@noida.hcltech.com) Inderpreet S.
+    (inderpreetb@noida.hcltech.com)
+ 
+    HCL Technologies Ltd.
+ 
+    This file is part of BFD, the Binary File Descriptor library.
+ 
+    This program is free software; you can redistribute it and/or modify it
+    under the terms of the GNU General Public License as published by the Free 
+    Software Foundation; either version 2 of the License, or (at your option)
+    any later version.
+ 
+    This program is distributed in the hope that it will be useful, but
+    WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 
+    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+    for more details.
+ 
+    You should have received a copy of the GNU General Public License along
+    with this program; if not, write to the Free Software Foundation, Inc., 59 
+    Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+ 
+ #include "bfd.h"
+ #include "sysdep.h"
+ #include "libbfd.h"
+ #include "coff/maxq.h"
+ #include "coff/internal.h"
+ #include "libcoff.h"
+ 
+ #ifndef MAXQ20
+ #define MAXQ20 1
+ #endif
+ 
+ /* Forward declarations.  */
+ static reloc_howto_type *maxq_reloc_type_lookup
+ PARAMS ((bfd * abfd, bfd_reloc_code_real_type code));
+ 
+ static long get_symbol_value PARAMS ((asymbol *));
+ 
+ static bfd_reloc_status_type coff_maxq20_reloc
+ PARAMS ((bfd *, arelent *, asymbol *, PTR, asection *, bfd *, char **));
+ 
+ #define RTYPE2HOWTO(cache_ptr, dst)                                     \
+   ((cache_ptr)->howto =                                                 \
+    ((dst)->r_type < 48 							\
+     ? howto_table + (((dst)->r_type==47) ? 6: ((dst)->r_type))		\
+     : NULL))
+ 
+ #define COFF_DEFAULT_SECTION_ALIGNMENT_POWER (2)
+ 
+ /* Code to swap in the reloc offset */
+ #define SWAP_IN_RELOC_OFFSET  H_GET_16
+ #define SWAP_OUT_RELOC_OFFSET H_PUT_16
+ 
+ #define SHORT_JUMP 	BFD_RELOC_16_PCREL_S2
+ #define LONG_JUMP 	BFD_RELOC_14
+ #define ABSOLUTE_ADDR_FOR_DATA BFD_RELOC_24
+ 
+ /* checks the range of short jump -127 to 128 */
+ #define IS_SJUMP_RANGE(x)((x>-128)&&(x<129))
+ #define HIGH_WORD_MASK 0xff00
+ #define LOW_WORD_MASK  0x00ff
+ 
+ #define true (1==1)
+ #define false !(true)
+ 
+ static long
+ get_symbol_value (symbol)
+      asymbol *symbol;
+ {
+   long relocation = 0;
+ 
+   if (bfd_is_com_section (symbol->section))
+     relocation = 0;
+   else
+     relocation = symbol->value +
+       symbol->section->output_section->vma + symbol->section->output_offset;
+ 
+   return relocation;
+ }
+ 
+ /* coff_maxq20_reloc This function performs all the maxq relocations. FIXME:
+    The handling of the addend in the 'BFD_*' relocations types */
+ static bfd_reloc_status_type
+ coff_maxq20_reloc (abfd, reloc_entry, symbol_in, data, input_section,
+ 		   output_bfd, error_message)
+      bfd *abfd;
+      arelent *reloc_entry;
+      asymbol *symbol_in;
+      PTR data;
+      asection *input_section ATTRIBUTE_UNUSED;
+      bfd *output_bfd ATTRIBUTE_UNUSED;
+      char **error_message ATTRIBUTE_UNUSED;
+ {
+   unsigned char *addr = NULL;
+   long diff = 0;
+   reloc_howto_type *howto = NULL;
+   unsigned long x = 0;
+   long call_addr = 0;
+   short addend = 0;
+ 
+   /* If this is an undefined symbol, return error.  */
+   if (symbol_in->section == &bfd_und_section
+       && (symbol_in->flags & BSF_WEAK) == 0)
+     return bfd_reloc_continue;
+ 
+   if (data && reloc_entry)
+     {
+       howto = reloc_entry->howto;
+       addr = (unsigned char *) data + reloc_entry->address;
+       call_addr = call_addr - call_addr;
+       call_addr = get_symbol_value (symbol_in);
+ 
+       /* Over here the value val stores the 8 bit/16 bit value. We will put a 
+          check if we are moving a 16 bit immediate value into an 8 bit
+          register. In that case we will generate a Upper bytes into PFX[0]
+          and move the lower 8 bits as SRC */
+ 
+       switch (reloc_entry->howto->type)
+ 	{
+ 	  /* BFD_RELOC_16_PCREL_S2 47 Handles all the relative jumps and
+ 	     calls Note: Every relative jump or call is in words. */
+ 	case SHORT_JUMP:
+ 	  {
+ 	    /* Handle any addend */
+ 	    addend = reloc_entry->addend;
+ 
+ 	    if (addend > call_addr || addend > 0)
+ 	      call_addr = symbol_in->section->output_section->vma + addend;
+ 	    else if (addend < call_addr && addend > 0)
+ 	      call_addr = call_addr + addend;
+ 	    else if (addend < 0)
+ 	      call_addr = call_addr + addend;
+ 
+ 	    diff = ((call_addr << 1) - (reloc_entry->address << 1));
+ 
+ 	    if (!IS_SJUMP_RANGE (diff))
+ 	      {
+ 		bfd_perror ("Can't Make it a Short Jump");
+ 		return bfd_reloc_outofrange;
+ 	      }
+ 
+ 	    else
+ 	      {
+ 		x = bfd_get_16 (abfd, addr);
+ 
+ 		x = x & LOW_WORD_MASK;
+ 		x = x | (diff << 8);
+ 		bfd_put_16 (abfd, (bfd_vma) x, addr);
+ 
+ 		return bfd_reloc_ok;
+ 	      }
+ 	  }			/* case */
+ 
+ 	case ABSOLUTE_ADDR_FOR_DATA:
+ 	case LONG_JUMP:
+ 	  /* BFD_RELOC_14 Handles intersegment or long jumps which might be
+ 	     from code to code or code to data segment jumps. Note: When this 
+ 	     fucntion is called by gas the section flags somehow do not
+ 	     contain the info about the section type(CODE or DATA). Thus the
+ 	     user needs to evoke the linker after assembling the files
+ 	     because the Code-Code relocs are word aligned but code-data are
+ 	     byte aligned.  */
+ 
+ 	  addend = (reloc_entry->addend - reloc_entry->addend);
+ 
+ 	  /* Handle any addend */
+ 	  addend = reloc_entry->addend;
+ 
+ 	  /* for relocation involving multiple file added becomes zero thus
+ 	     this fails - check for zero added. In another case when we try
+ 	     to add a stub to a file the addend shows the offset from the
+ 	     start od this file.  */
+ 
+ 	  addend = 0;
+ 	  if (!bfd_is_com_section (symbol_in->section) &&
+ 	      ((symbol_in->flags & BSF_OLD_COMMON) == 0))
+ 	    {
+ 	      if (reloc_entry->addend > symbol_in->value)
+ 		addend = reloc_entry->addend - symbol_in->value;
+ 
+ 	      if ((reloc_entry->addend < symbol_in->value)
+ 		  && (reloc_entry->addend != 0))
+ 		addend = reloc_entry->addend - symbol_in->value;
+ 
+ 	      if (reloc_entry->addend == symbol_in->value)
+ 		addend = 0;
+ 	    }
+ 
+ 	  if (bfd_is_com_section (symbol_in->section) ||
+ 	      ((symbol_in->flags & BSF_OLD_COMMON) != 0))
+ 	    addend = reloc_entry->addend;
+ 
+ 	  if (addend < 0)
+ 	    {
+ 	      if (call_addr < (long) (addend * (-1)))
+ 		addend = 0;
+ 	    }
+ 
+ 	  call_addr += addend;
+ 
+ 	  /* FIXME: This check doesnot work well with the Assembler, linker
+ 	     needs to be run always. */
+ 	  if ((symbol_in->section->flags & SEC_CODE) == SEC_CODE)
+ 	    {
+ 	      call_addr = call_addr >> 1;	/* to convert it into words */
+ 	      if (call_addr > 0xFFFF)	/* Intersegment Jump */
+ 		{
+ 		  bfd_perror ("Exceeds Long Jump Range");
+ 		  return bfd_reloc_outofrange;
+ 		}
+ 	      else
+ 		{
+ 		  x = bfd_get_32 (abfd, addr);
+ 
+ 		  x = (x & 0xFF00FF00);
+ 		  x = (x | ((call_addr & HIGH_WORD_MASK) >> 8));
+ 		  x = (x | (call_addr & LOW_WORD_MASK) << 16);
+ 
+ 		  bfd_put_32 (abfd, (bfd_vma) x, addr);
+ 		  return bfd_reloc_ok;
+ 		}
+ 	    }
+ 
+ 	  /* case ABSOLUTE_ADDR_FOR_DATA : Resolves any code-data segemnt
+ 	     relocs. These are NOT word aligned.  */
+ 	  else
+ 	    {
+ 	      if (call_addr > 0xFFFF)	/* Intersegment Jump */
+ 		{
+ 		  bfd_perror ("Absolute address Exceeds 16 bit Range");
+ 		  return bfd_reloc_outofrange;
+ 		}
+ 
+ 	      else
+ 		{
+ 		  x = bfd_get_32 (abfd, addr);
+ 		  x = (x & 0xFF00FF00);
+ 		  x = (x | ((call_addr & HIGH_WORD_MASK) >> 8));
+ 		  x = (x | (call_addr & LOW_WORD_MASK) << 16);
+ 
+ 		  bfd_put_32 (abfd, (bfd_vma) x, addr);
+ 		  return bfd_reloc_ok;
+ 
+ 		}
+ 
+ 	    }
+ 
+ 	case BFD_RELOC_8:
+ 	  {
+ 	    addend = (reloc_entry->addend - reloc_entry->addend);
+ 
+ 	    if (!bfd_is_com_section (symbol_in->section) &&
+ 		((symbol_in->flags & BSF_OLD_COMMON) == 0))
+ 	      {
+ 		if (reloc_entry->addend > symbol_in->value)
+ 		  addend = reloc_entry->addend - symbol_in->value;
+ 		if (reloc_entry->addend < symbol_in->value)
+ 		  addend = reloc_entry->addend - symbol_in->value;
+ 		if (reloc_entry->addend == symbol_in->value)
+ 		  addend = 0;
+ 	      }
+ 
+ 	    if (bfd_is_com_section (symbol_in->section) ||
+ 		((symbol_in->flags & BSF_OLD_COMMON) != 0))
+ 	      addend = reloc_entry->addend;
+ 
+ 	    if (addend < 0)
+ 	      {
+ 		if (call_addr < (long) (addend * (-1)))
+ 		  addend = 0;
+ 	      }
+ 
+ 	    if (call_addr + addend > 0xFF)
+ 	      {
+ 		bfd_perror ("Absolute address Exceeds 8 bit Range");
+ 		return bfd_reloc_outofrange;
+ 	      }
+ 	    else
+ 	      {
+ 		x = bfd_get_8 (abfd, addr);
+ 		x = x & 0x00;
+ 		x = x | (call_addr + addend);
+ 	      }
+ 
+ 	    bfd_put_8 (abfd, (bfd_vma) x, addr);
+ 	    return bfd_reloc_ok;
+ 	  }
+ 
+ 	case BFD_RELOC_16:
+ 	  {
+ 
+ 	    addend = (reloc_entry->addend - reloc_entry->addend);
+ 	    if (!bfd_is_com_section (symbol_in->section) &&
+ 		((symbol_in->flags & BSF_OLD_COMMON) == 0))
+ 	      {
+ 		if (reloc_entry->addend > symbol_in->value)
+ 		  addend = reloc_entry->addend - symbol_in->value;
+ 
+ 		if (reloc_entry->addend < symbol_in->value)
+ 		  addend = reloc_entry->addend - symbol_in->value;
+ 
+ 		if (reloc_entry->addend == symbol_in->value)
+ 		  addend = 0;
+ 	      }
+ 
+ 	    if (bfd_is_com_section (symbol_in->section) ||
+ 		((symbol_in->flags & BSF_OLD_COMMON) != 0))
+ 	      addend = reloc_entry->addend;
+ 
+ 	    if (addend < 0)
+ 	      {
+ 		if (call_addr < (long) (addend * (-1)))
+ 		  addend = 0;
+ 	      }
+ 
+ 	    if ((call_addr + addend) > 0xFFFF)
+ 	      {
+ 		bfd_perror ("Absolute address Exceeds 16 bit Range");
+ 		return bfd_reloc_outofrange;
+ 	      }
+ 	    else
+ 	      {
+ 		unsigned short val = (call_addr + addend);
+ 		x = bfd_get_16 (abfd, addr);
+ 
+ 		/* LE */
+ 		x = (x & 0x0000);	/* Flush garbage value */
+ 		x = val;
+ 		if ((symbol_in->section->flags & SEC_CODE) == SEC_CODE)
+ 		  x = x >> 1;	/* convert it into words */
+ 	      }
+ 
+ 	    bfd_put_16 (abfd, (bfd_vma) x, addr);
+ 	    return bfd_reloc_ok;
+ 	  }
+ 
+ 	case BFD_RELOC_32:
+ 	  {
+ 
+ 	    addend = (reloc_entry->addend - reloc_entry->addend);
+ 
+ 	    if (!bfd_is_com_section (symbol_in->section) &&
+ 		((symbol_in->flags & BSF_OLD_COMMON) == 0))
+ 	      {
+ 		if (reloc_entry->addend > symbol_in->value)
+ 		  addend = reloc_entry->addend - symbol_in->value;
+ 		if (reloc_entry->addend < symbol_in->value)
+ 		  addend = reloc_entry->addend - symbol_in->value;
+ 		if (reloc_entry->addend == symbol_in->value)
+ 		  addend = 0;
+ 	      }
+ 
+ 	    if (bfd_is_com_section (symbol_in->section) ||
+ 		((symbol_in->flags & BSF_OLD_COMMON) != 0))
+ 	      addend = reloc_entry->addend;
+ 
+ 	    if (addend < 0)
+ 	      {
+ 		if (call_addr < (long) (addend * (-1)))
+ 		  addend = 0;
+ 	      }
+ 
+ 	    if ((call_addr + addend) > 0xFFFFFFFF)
+ 	      {
+ 		bfd_perror ("Absolute address Exceeds 32 bit Range");
+ 		return bfd_reloc_outofrange;
+ 	      }
+ 	    else
+ 	      {
+ 		x = bfd_get_32 (abfd, addr);
+ 		x = (x & 0x0000);	/* Flush garbage value */
+ 		x = call_addr + addend;
+ 		if ((symbol_in->section->flags & SEC_CODE) == SEC_CODE)
+ 		  x = x >> 1;	/* convert it into words */
+ 	      }
+ 	    bfd_put_32 (abfd, (bfd_vma) x, addr);
+ 	    return bfd_reloc_ok;
+ 	  }
+ 
+ 	default:
+ 	  bfd_perror ("Unrecognized Reloc Type");
+ 	  return bfd_reloc_notsupported;
+ 
+ 	}
+ 
+     }
+   return bfd_reloc_notsupported;
+ }
+ 
+ static reloc_howto_type howto_table[] = {
+   EMPTY_HOWTO (0),
+   EMPTY_HOWTO (1),
+ 
+   {
+    BFD_RELOC_32, 0, 1, 8, false, 0, complain_overflow_bitfield,
+    coff_maxq20_reloc, "32Bit", true, 0x000000ff, 0x000000ff, true},
+ 
+   {
+    SHORT_JUMP, 0, 1, 8, false, 0, complain_overflow_bitfield,
+    coff_maxq20_reloc, "SHORT_JMP", true, 0x000000ff, 0x000000ff, true},
+ 
+   {
+    ABSOLUTE_ADDR_FOR_DATA, 0, 2, 32, false, 0, complain_overflow_bitfield,
+    coff_maxq20_reloc, "INTERSEGMENT_RELOC", true, 0x00000000, 0x00000000,
+    false},
+ 
+   {
+    BFD_RELOC_16, 0, 1, 8, false, 0, complain_overflow_bitfield,
+    coff_maxq20_reloc, "16Bit", true, 0x000000ff, 0x000000ff, true},
+ 
+   {
+    LONG_JUMP, 0, 2, 32, false, 0, complain_overflow_bitfield,
+    coff_maxq20_reloc, "LONG_JUMP", true, 0x00000000, 0x00000000, false},
+ 
+   {
+    BFD_RELOC_8, 0, 1, 8, false, 0, complain_overflow_bitfield,
+    coff_maxq20_reloc, "8bit", true, 0x000000ff, 0x000000ff, true},
+ 
+   EMPTY_HOWTO (8),
+   EMPTY_HOWTO (9),
+   EMPTY_HOWTO (10),
+ 
+ };
+ 
+ /* Map BFD reloc types to MAXQ COFF reloc types.  */
+ typedef struct maxq_reloc_map
+ {
+   bfd_reloc_code_real_type bfd_reloc_val;
+   unsigned int maxq_reloc_val;
+   reloc_howto_type *table;
+ }
+ reloc_map;
+ 
+ static const reloc_map maxq_reloc_map[] = {
+   {BFD_RELOC_16_PCREL_S2, SHORT_JUMP, howto_table},
+   {BFD_RELOC_16, LONG_JUMP, howto_table},
+ };
+ 
+ static reloc_howto_type *
+ maxq_reloc_type_lookup (abfd, code)
+      bfd *abfd ATTRIBUTE_UNUSED;
+      bfd_reloc_code_real_type code;
+ {
+   unsigned int i;
+ 
+   for (i = 0; i < sizeof (reloc_map) / sizeof (struct maxq_reloc_map); i++)
+     {
+       const reloc_map *entry;
+ 
+       entry = maxq_reloc_map + i;
+ 
+       switch (code)
+ 	{
+ 	  /* SHORT JUMP */
+ 	case BFD_RELOC_16_PCREL_S2:
+ 	  return (&howto_table[3]);
+ 
+ 	  /* INTERSEGMENT JUMP */
+ 	case BFD_RELOC_24:
+ 	  return (&howto_table[4]);
+ 
+ 	  /* BYTE RELOC */
+ 	case BFD_RELOC_8:
+ 	  return (&howto_table[7]);
+ 
+ 	  /* WORD RELOC */
+ 	case BFD_RELOC_16:
+ 	  return (&howto_table[5]);
+ 
+ 	  /* LONG RELOC */
+ 	case BFD_RELOC_32:
+ 	  return (&howto_table[2]);
+ 
+ 	  /* LONG JUMP */
+ 	case BFD_RELOC_14:
+ 	  return (&howto_table[6]);
+ 
+ 	default:
+ 	  return NULL;
+ 	}
+     }
+ 
+   return NULL;
+ }
+ 
+ #define coff_bfd_reloc_type_lookup maxq_reloc_type_lookup
+ 
+ /* Perform any necessary magic to the addend in a reloc entry.  */
+ #define CALC_ADDEND(abfd, symbol, ext_reloc, cache_ptr) \
+  cache_ptr->addend =  ext_reloc.r_offset;
+ 
+ #include "coffcode.h"
+ 
+ #ifndef TARGET_UNDERSCORE
+ #define TARGET_UNDERSCORE 1
+ #endif
+ 
+ #ifndef EXTRA_S_FLAGS
+ #define EXTRA_S_FLAGS 0
+ #endif
+ 
+ /* Forward declaration for use initialising alternative_target field.  */
+ CREATE_LITTLE_COFF_TARGET_VEC (maxqcoff_vec, "coff-maxq", 0, EXTRA_S_FLAGS,
+ 			       TARGET_UNDERSCORE, NULL, COFF_SWAP_TABLE);
+ /* 
+    CREATE_BIG_COFF_TARGET_VEC (maxqcoffbig_vec, "coff-maxq", 0,
+    EXTRA_S_FLAGS, TARGET_UNDERSCORE, NULL, COFF_SWAP_TABLE); */
Index: bfd/coffcode.h
===================================================================
RCS file: /cvs/src/src/bfd/coffcode.h,v
retrieving revision 1.101
diff -c -3 -p -r1.101 coffcode.h
*** bfd/coffcode.h	19 Dec 2003 10:01:59 -0000	1.101
--- bfd/coffcode.h	2 Nov 2004 13:51:33 -0000
*************** coff_set_arch_mach_hook (abfd, filehdr)
*** 1975,1980 ****
--- 1975,1988 ----
        machine = 88100;
        break;
  #endif
+ 
+ #ifdef MAXQ20MAGIC
+     case MAXQ20MAGIC:
+       arch = bfd_arch_maxq;
+       machine = 0;
+       break;
+ #endif
+ 
  #ifdef Z8KMAGIC
      case Z8KMAGIC:
        arch = bfd_arch_z8k;
*************** coff_set_flags (abfd, magicp, flagsp)
*** 2851,2856 ****
--- 2859,2872 ----
        return TRUE;
        break;
  #endif
+ 
+ #ifdef MAXQ20MAGIC
+     case bfd_arch_maxq:
+         *magicp = MAXQ20MAGIC;
+       return true;
+       break;
+ #endif
+ 
  #ifdef A29K_MAGIC_BIG
      case bfd_arch_a29k:
        if (bfd_big_endian (abfd))
*************** coff_write_object_contents (abfd)
*** 4042,4047 ****
--- 4058,4069 ----
      internal_a.magic = NMAGIC; /* Assume separate i/d.  */
  #endif
  
+ #ifdef MAXQ20MAGIC
+ #define __A_MAGIC_SET__
+       internal_a.magic = MAXQ20MAGIC;
+ #endif
+  
+ 
  #ifndef __A_MAGIC_SET__
  #include "Your aouthdr magic number is not being set!"
  #else
Index: bfd/config.bfd
===================================================================
RCS file: /cvs/src/src/bfd/config.bfd,v
retrieving revision 1.152.6.6
diff -c -3 -p -r1.152.6.6 config.bfd
*** bfd/config.bfd	17 May 2004 16:16:32 -0000	1.152.6.6
--- bfd/config.bfd	2 Nov 2004 13:51:33 -0000
*************** m6811*|m68hc11*) targ_archs="bfd_m68hc11
*** 58,63 ****
--- 58,64 ----
  m6812*|m68hc12*) targ_archs="bfd_m68hc12_arch bfd_m68hc11_arch" ;;
  m68*)	         targ_archs=bfd_m68k_arch ;;
  m88*)	         targ_archs=bfd_m88k_arch ;;
+ maxq*)		 targ_archs=bfd_maxq_arch ;;
  mips*)	         targ_archs=bfd_mips_arch ;;
  or32*)		 targ_archs=bfd_or32_arch ;;
  pdp11*)	         targ_archs=bfd_pdp11_arch ;;
*************** case "${targ}" in
*** 737,743 ****
      targ_selvecs=ieee_vec
      targ_underscore=yes
      ;;
- 
    m88*-harris-cxux* | m88*-*-dgux* | m88*-*-sysv4*)
      targ_defvec=bfd_elf32_m88k_vec
      targ_selvecs=m88kbcs_vec
--- 738,743 ----
*************** case "${targ}" in
*** 750,756 ****
      targ_defvec=m88kbcs_vec
      targ_underscore=yes
      ;;
! 
    mcore-*-elf)
      targ_defvec=bfd_elf32_mcore_big_vec
      targ_selvecs="bfd_elf32_mcore_big_vec bfd_elf32_mcore_little_vec"
--- 750,761 ----
      targ_defvec=m88kbcs_vec
      targ_underscore=yes
      ;;
!   maxq-*-coff)
!     targ_defvec=maxqcoff_vec
!     ;;
!   maxq-*-ihex)
!     targ_defvec=ihex_vec
!     ;;
    mcore-*-elf)
      targ_defvec=bfd_elf32_mcore_big_vec
      targ_selvecs="bfd_elf32_mcore_big_vec bfd_elf32_mcore_little_vec"
Index: bfd/configure
===================================================================
RCS file: /cvs/src/src/bfd/configure,v
retrieving revision 1.166.4.8
diff -c -3 -p -r1.166.4.8 configure
*** bfd/configure	17 May 2004 19:34:36 -0000	1.166.4.8
--- bfd/configure	2 Nov 2004 13:51:37 -0000
*************** do
*** 6430,6435 ****
--- 6430,6436 ----
      m68ksysvcoff_vec)		tb="$tb coff-svm68k.lo cofflink.lo" ;;
      m88kbcs_vec)		tb="$tb coff-m88k.lo" ;;
      m88kmach3_vec)		tb="$tb m88kmach3.lo aout32.lo" ;;
+     maxqcoff_vec)               tb="$tb coff-maxq.lo"; target_size=16 ;;
      mach_o_be_vec)              tb="$tb mach-o.lo" ;;
      mach_o_le_vec)              tb="$tb mach-o.lo" ;;
      mach_o_fat_vec)             tb="$tb mach-o.lo" ;;
Index: bfd/configure.in
===================================================================
RCS file: /cvs/src/src/bfd/configure.in,v
retrieving revision 1.143.4.8
diff -c -3 -p -r1.143.4.8 configure.in
*** bfd/configure.in	17 May 2004 19:34:36 -0000	1.143.4.8
--- bfd/configure.in	2 Nov 2004 13:51:37 -0000
*************** do
*** 739,744 ****
--- 739,745 ----
      m68ksysvcoff_vec)		tb="$tb coff-svm68k.lo cofflink.lo" ;;
      m88kbcs_vec)		tb="$tb coff-m88k.lo" ;;
      m88kmach3_vec)		tb="$tb m88kmach3.lo aout32.lo" ;;
+     maxqcoff_vec)               tb="$tb coff-maxq.lo"; target_size=16 ;;
      mach_o_be_vec)              tb="$tb mach-o.lo" ;;
      mach_o_le_vec)              tb="$tb mach-o.lo" ;;
      mach_o_fat_vec)             tb="$tb mach-o.lo" ;;
Index: bfd/cpu-maxq.c
===================================================================
RCS file: bfd/cpu-maxq.c
diff -N bfd/cpu-maxq.c
*** /dev/null	1 Jan 1970 00:00:00 -0000
--- bfd/cpu-maxq.c	2 Nov 2004 13:51:37 -0000
***************
*** 0 ****
--- 1,50 ----
+ /* BFD support for the MAXQ20/10 architecture.
+    Copyright  2003, 2004,2005
+    Free Software Foundation, Inc.
+ 
+    Written by Vineet Sharma(vineets@noida.hcltech.com)
+ 	      Inderpreet Singh(inderpreetb@noida.hcltech.com)		
+ 
+ This file is part of BFD, the Binary File Descriptor library.
+ 
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+ 
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ GNU General Public License for more details.
+ 
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+ 
+ #include "bfd.h"
+ #include "sysdep.h"
+ #include "libbfd.h"
+ 
+ #ifndef true
+ #define true (1==1)
+ #endif
+ 
+ #ifndef false
+ #define false (0==1)
+ #endif
+ 
+ /* MAXQ Archtecture info */
+ const bfd_arch_info_type bfd_maxq_arch = {
+   16,				/* 16 bits in a word */
+   16,				/* 16 bits in an address */
+   8,				/* 16 bits in a byte */
+   bfd_arch_maxq,		/* enum bfd_archtecture arch */
+   0,				/* only 1 machine */
+   "maxq",			/* arch_name */
+   "maxq",			/* printable name */
+   0,				/* section align power */
+   true,				/* the_default: if this is the machine */
+   bfd_default_compatible,	/* bfd_arch_info */
+   bfd_default_scan,
+   NULL
+ };
Index: bfd/targets.c
===================================================================
RCS file: /cvs/src/src/bfd/targets.c,v
retrieving revision 1.103.6.3
diff -c -3 -p -r1.103.6.3 targets.c
*** bfd/targets.c	6 May 2004 02:43:16 -0000	1.103.6.3
--- bfd/targets.c	2 Nov 2004 13:51:37 -0000
*************** extern const bfd_target vms_vax_vec;
*** 724,729 ****
--- 724,730 ----
  extern const bfd_target w65_vec;
  extern const bfd_target we32kcoff_vec;
  extern const bfd_target z8kcoff_vec;
+ extern const bfd_target maxqcoff_vec;
  
  /* These are always included.  */
  extern const bfd_target srec_vec;
*************** static const bfd_target * const _bfd_tar
*** 982,987 ****
--- 983,989 ----
  	&m68ksysvcoff_vec,
  	&m88kbcs_vec,
  	&m88kmach3_vec,
+ 	&maxqcoff_vec,
  	&mach_o_be_vec,
  	&mach_o_le_vec,
  	&mach_o_fat_vec,
*************** static const bfd_target * const _bfd_tar
*** 1064,1069 ****
--- 1066,1072 ----
  	&w65_vec,
  	&we32kcoff_vec,
  	&z8kcoff_vec,
+ 	&maxqcoff_vec,
  	&bfd_elf32_am33lin_vec,
  #endif /* not SELECT_VECS */
  
Index: gas/configure
===================================================================
RCS file: /cvs/src/src/gas/configure,v
retrieving revision 1.162.6.6
diff -c -3 -p -r1.162.6.6 configure
*** gas/configure	17 May 2004 16:16:36 -0000	1.162.6.6
--- gas/configure	2 Nov 2004 13:51:41 -0000
*************** for this_target in $target $canon_target
*** 4171,4176 ****
--- 4171,4177 ----
        m683??)		cpu_type=m68k ;;
        m5200)		cpu_type=m68k ;;
        m8*)		cpu_type=m88k ;;
+       maxq)             cpu_type=maxq ;;
        mips*el)		cpu_type=mips endian=little ;;
        mips*)		cpu_type=mips endian=big ;;
        or32*)		cpu_type=or32 endian=big ;;
*************** echo "$as_me: WARNING: GAS support for $
*** 4405,4414 ****
        m68k-*-openbsd*)			fmt=aout em=nbsd bfd_gas=yes ;;
        m68k-apple-aux*)			fmt=coff em=aux ;;
        m68k-*-psos*)			fmt=elf em=psos;;
- 
        m88k-motorola-sysv3*)		fmt=coff em=delt88 ;;
        m88k-*-coff*)			fmt=coff ;;
! 
        mcore-*-elf)			fmt=elf ;;
        mcore-*-pe)			fmt=coff em=pe bfd_gas=yes ;;
  
--- 4406,4415 ----
        m68k-*-openbsd*)			fmt=aout em=nbsd bfd_gas=yes ;;
        m68k-apple-aux*)			fmt=coff em=aux ;;
        m68k-*-psos*)			fmt=elf em=psos;;
        m88k-motorola-sysv3*)		fmt=coff em=delt88 ;;
        m88k-*-coff*)			fmt=coff ;;
!       maxq-*-coff)                      fmt=coff ;;
!       maxq-*-ihex)                      fmt=coff ;; 
        mcore-*-elf)			fmt=elf ;;
        mcore-*-pe)			fmt=coff em=pe bfd_gas=yes ;;
  
Index: gas/configure.in
===================================================================
RCS file: /cvs/src/src/gas/configure.in,v
retrieving revision 1.147.6.4
diff -c -3 -p -r1.147.6.4 configure.in
*** gas/configure.in	17 May 2004 16:16:37 -0000	1.147.6.4
--- gas/configure.in	2 Nov 2004 13:51:41 -0000
*************** changequote([,])dnl
*** 143,148 ****
--- 143,149 ----
        m8*)		cpu_type=m88k ;;
        mips*el)		cpu_type=mips endian=little ;;
        mips*)		cpu_type=mips endian=big ;;
+      maxq)             cpu_type=maxq ;;
        or32*)		cpu_type=or32 endian=big ;;
        pjl*)		cpu_type=pj endian=little ;;
        pj*)		cpu_type=pj endian=big ;;
*************** changequote([,])dnl
*** 368,377 ****
        m68k-*-openbsd*)			fmt=aout em=nbsd bfd_gas=yes ;;
        m68k-apple-aux*)			fmt=coff em=aux ;;
        m68k-*-psos*)			fmt=elf em=psos;;
- 
        m88k-motorola-sysv3*)		fmt=coff em=delt88 ;;
        m88k-*-coff*)			fmt=coff ;;
! 
        mcore-*-elf)			fmt=elf ;;
        mcore-*-pe)			fmt=coff em=pe bfd_gas=yes ;;
  
--- 369,378 ----
        m68k-*-openbsd*)			fmt=aout em=nbsd bfd_gas=yes ;;
        m68k-apple-aux*)			fmt=coff em=aux ;;
        m68k-*-psos*)			fmt=elf em=psos;;
        m88k-motorola-sysv3*)		fmt=coff em=delt88 ;;
        m88k-*-coff*)			fmt=coff ;;
!       maxq-*-coff)      		fmt=coff ;;                   # FOR MAXQ20 Coff
!       maxq-*-ihex) 	         	fmt=coff ;;                 # FOR MAXQ20 Intel-HEX
        mcore-*-elf)			fmt=elf ;;
        mcore-*-pe)			fmt=coff em=pe bfd_gas=yes ;;
  
Index: gas/config/obj-coff.h
===================================================================
RCS file: /cvs/src/src/gas/config/obj-coff.h,v
retrieving revision 1.20
diff -c -3 -p -r1.20 obj-coff.h
*** gas/config/obj-coff.h	20 Nov 2003 00:01:54 -0000	1.20
--- gas/config/obj-coff.h	2 Nov 2004 13:51:41 -0000
***************
*** 95,100 ****
--- 95,106 ----
  #define TARGET_FORMAT "coff-or32-big"
  #endif
  
+ #ifdef TC_MAXQ20
+ #include "coff/maxq.h"
+ #define TARGET_FORMAT "coff-maxq"
+ #endif
+ 
+ 
  #ifdef TC_I960
  #include "coff/i960.h"
  #define TARGET_FORMAT "coff-Intel-little"
Index: gas/config/tc-maxq.c
===================================================================
RCS file: gas/config/tc-maxq.c
diff -N gas/config/tc-maxq.c
*** /dev/null	1 Jan 1970 00:00:00 -0000
--- gas/config/tc-maxq.c	2 Nov 2004 13:51:42 -0000
***************
*** 0 ****
--- 1,3614 ----
+ /* tc-maxq.c -- assembler code for a MAXQ chip. Copyright 2003, 2004 Free
+    Software Foundation, Inc. Contributed by HCL Technologies Pvt. Ltd.
+ 
+    Author: Vineet Sharma(vineets@noida.hcltech.com) Inderpreet
+    S.(inderpreetb@noida.hcltech.com)
+ 
+    This file is part of GAS.
+ 
+    GAS is free software; you can redistribute it and/or modify it under the
+    terms of the GNU General Public License as published by the Free Software
+    Foundation; either version 2, or (at your option) any later version.
+ 
+    GAS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more
+    details.
+ 
+    You should have received a copy of the GNU General Public License along
+    with GAS; see the file COPYING.  If not, write to the Free Software
+    Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+ 
+ #include "as.h"
+ #include "safe-ctype.h"
+ #include "subsegs.h"
+ #include "dwarf2dbg.h"
+ #include "tc-maxq.h"
+ #include "opcode/maxq.h"
+ #include "ctype.h"
+ 
+ #ifndef MAXQ10S
+ #define MAXQ10S 1
+ #endif
+ 
+ #ifndef _STRING_H
+ #include "string.h"
+ #endif
+ 
+ #ifndef DEFAULT_ARCH
+ #define DEFAULT_ARCH "MAXQ20"
+ #endif
+ 
+ #ifndef MAX_OPERANDS
+ #define MAX_OPERANDS 2
+ #endif
+ 
+ #ifndef MAX_MNEM_SIZE
+ #define MAX_MNEM_SIZE 8
+ #endif
+ 
+ #ifndef END_OF_INSN
+ #define END_OF_INSN '\0'
+ #endif
+ 
+ #ifndef IMMEDIATE_PREFIX
+ #define IMMEDIATE_PREFIX '#'
+ #endif
+ 
+ #ifndef MAX_REG_NAME_SIZE
+ #define MAX_REG_NAME_SIZE 4
+ #endif
+ 
+ #ifndef MAX_MEM_NAME_SIZE
+ #define MAX_MEM_NAME_SIZE 9
+ #endif
+ 
+ /* opcode for PFX[0].  */
+ #define PFX0 0x0b
+ 
+ /* Set default to MAXQ20 */
+ unsigned int max_version = 20;
+ 
+ const char *default_arch = DEFAULT_ARCH;
+ 
+ /* Type of the operand: Register,Immediate,Memory access,flag or bit. */
+ union _maxq20_op
+ {
+   const reg_entry *reg;
+   char imms;			/* This is to store the immediate value
+ 				   operand */
+   expressionS *disps;
+   symbolS *data;
+   const mem_access *mem;
+   int flag;
+   const reg_bit *r_bit;
+ };
+ 
+ typedef union _maxq20_op maxq20_opcode;
+ 
+ /* For handling optional L/S in Maxq20 */
+ #ifdef BFD_ASSEMBLER
+ 
+ /* Exposed For Linker - maps indirectly to the liker relocations */
+ #define LONG_PREFIX  		MAXQ_LONGJUMP	/* BFD_RELOC_16 */
+ #define SHORT_PREFIX 		MAXQ_SHORTJUMP	/* BFD_RELOC_16_PCREL_S2 */
+ #define ABSOLUTE_ADDR_FOR_DATA 	MAXQ_INTERSEGMENT
+ 
+ #define NO_PREFIX    		0
+ #define EXPLICT_LONG_PREFIX     14
+ 
+ #else
+ 
+ #define EXPLICT_LONG_PREFIX 14
+ #define LONG_PREFIX  5
+ #define SHORT_PREFIX 1
+ #define ABSOLUTE_ADDR_FOR_DATA 0
+ #define NO_PREFIX    0
+ 
+ #endif
+ 
+ /* Pheripheral initialization function */
+ static void pmmain PARAMS ((void));
+ static void make_new_reg_table PARAMS ((void));
+ 
+ /* The main instruction structure containing fields to describe instrn */
+ typedef struct _maxq20_insn
+ {
+   /* The opcode information for the MAXQ20 */
+   MAXQ20_OPCODE_INFO op;
+ 
+   /* The number of operands */
+   unsigned int operands;
+ 
+   /* Number of different types of operands - Comments can be removed if reqd. 
+    */
+   unsigned int reg_operands, mem_operands, disp_operands, data_operands;
+   unsigned int imm_operands, imm_bit_operands, bit_operands, flag_operands;
+ 
+   /* Types of the individual operands */
+   UNKNOWN_OP types[MAX_OPERANDS];
+ 
+   /* Relocation type for operand : to be investigated into */
+   int reloc[MAX_OPERANDS];
+ 
+   /* Complete information of the Operands */
+   maxq20_opcode maxq20_op[MAX_OPERANDS];
+ 
+   /* Choice of prefix register whenever needed */
+   int prefix;
+ 
+   /* Optional Prefix for Instructions like LJUMP, SJUMP etc */
+   unsigned char Instr_Prefix;
+ 
+   /* 16 bit Instruction word */
+   unsigned char instr[2];
+ }
+ maxq20_insn;
+ 
+ /* Definitions of all possible characters that can start an operand */
+ const char *extra_symbol_chars = "@(#";
+ 
+ /* Special Character that would start a comment */
+ const char comment_chars[] = ";";
+ 
+ /* Starts a comment when it appears at the start of a line */
+ const char line_comment_chars[] = ";#";
+ 
+ /* Line Separator */
+ const char line_separator_chars[] = "";	/* originally may b by sudeep "\n" */
+ 
+ /* 
+  *  The following are used for option processing 
+  */
+ 
+ /* This is added to the mach independent string passed to getopt */
+ const char *md_shortopts = "q";
+ 
+ /* Characters for exponent and floating point */
+ const char EXP_CHARS[] = "eE";
+ const char FLT_CHARS[] = "";
+ 
+ /* This is for the machine dependent option handling */
+ #define OPTION_EB               (OPTION_MD_BASE + 0)
+ #define OPTION_EL               (OPTION_MD_BASE + 1)
+ #define MAXQ_10                 (OPTION_MD_BASE + 2)
+ #define MAXQ_20			(OPTION_MD_BASE + 3)
+ 
+ struct option md_longopts[] = {
+   {"MAXQ10", no_argument, NULL, MAXQ_10},
+   {"MAXQ20", no_argument, NULL, MAXQ_20},
+   {NULL, no_argument, NULL, 0}
+ };
+ size_t md_longopts_size = sizeof (md_longopts);
+ 
+ /* md_undefined_symbol We have no need for this function */
+ symbolS *
+ md_undefined_symbol (name)
+      char *name;
+ {
+   name = name;			/* Just to ignore the Warnings */
+   return 0;
+ }
+ 
+ int
+ md_parse_option (c, arg)
+      int c;
+      char *arg ATTRIBUTE_UNUSED;
+ {
+   /* Any options support will be added onto this switch case */
+   switch (c)
+     {
+     case MAXQ_10:
+       max_version = 10;
+       break;
+     case MAXQ_20:
+       max_version = 20;
+       break;
+ 
+     default:
+       return 0;
+     }
+ 
+   return 1;
+ }
+ 
+ /* When a usage message is printed, this function is called and it prints a
+    description of the machine specific options */
+ 
+ void
+ md_show_usage (stream)
+      FILE *stream;
+ {
+   /* Over here we will fill the description of the machine specific options */
+ 
+   fprintf (stream, _(" MAXQ-specific assembler options:\n"));
+ 
+   fprintf (stream, _("\
+ 	-MAXQ20		       generate obj for MAXQ20(default)\n\
+ 	-MAXQ10		       generate obj for MAXQ10\n\
+ 	"));
+ }
+ 
+ #ifdef BFD_ASSEMBLER
+ unsigned long
+ maxq20_mach ()
+ {
+   if (!(strcmp (default_arch, "MAXQ20")))
+     return 0;
+ 
+   as_fatal (_("Unknown architecture"));
+   return 1;
+ }
+ 
+ arelent *
+ tc_gen_reloc (section, fixp)
+      asection *section ATTRIBUTE_UNUSED;
+      fixS *fixp;
+ {
+   arelent *rel;
+   bfd_reloc_code_real_type code;
+ 
+   switch (fixp->fx_r_type)
+     {
+ 
+     case MAXQ_INTERSEGMENT:
+     case MAXQ_LONGJUMP:
+     case BFD_RELOC_16_PCREL_S2:
+       code = fixp->fx_r_type;
+       break;
+     case 0:
+     default:
+       switch (fixp->fx_size)
+ 	{
+ 	default:
+ 	  as_bad_where (fixp->fx_file, fixp->fx_line,
+ 			_("can not do %d byte relocation"), fixp->fx_size);
+ 	  code = BFD_RELOC_32;
+ 	  break;
+ 
+ 	case 1:
+ 	  code = BFD_RELOC_8;
+ 	  break;
+ 	case 2:
+ 	  code = BFD_RELOC_16;
+ 	  break;
+ 	case 4:
+ 	  code = BFD_RELOC_32;
+ 	  break;
+ 	}
+     }
+ 
+   rel = (arelent *) xmalloc (sizeof (arelent));
+   rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
+   *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
+ 
+   rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
+   rel->addend = fixp->fx_addnumber;
+   rel->howto = bfd_reloc_type_lookup (stdoutput, code);
+   if (rel->howto == NULL)
+     {
+       as_bad_where (fixp->fx_file, fixp->fx_line,
+ 		    _("cannot represent relocation type %s"),
+ 		    bfd_get_reloc_code_name (code));
+ 
+       /* Set howto to a garbage value so that we can keep going.  */
+       rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
+       assert (rel->howto != NULL);
+     }
+ 
+   return rel;
+ 
+ }
+ 
+ #endif
+ 
+ /* md_estimate_size_before_relax()
+ 
+    Called just before relax() for rs_machine_dependent frags.  The MAXQ
+    assembler uses these frags to handle 16 bit absolute jumps which require a 
+    prefix instruction to be inserted. Any symbol that is now undefined will
+    not become defined. Return the correct fr_subtype in the frag. Return the
+    initial "guess for variable size of frag"(This will be eiter 2 or 0) to
+    caller. The guess is actually the growth beyond the fixed part.  Whatever
+    we do to grow the fixed or variable part contributes to our returned
+    value. */
+ 
+ int
+ md_estimate_size_before_relax (fragP, segment)
+      fragS *fragP;
+      segT segment;
+ {
+   /* Check whether the symbol has been resolved or not. Otherwise we will
+      have to generate a fixup */
+   if ((S_GET_SEGMENT (fragP->fr_symbol) != segment)
+       || fragP->fr_subtype == EXPLICT_LONG_PREFIX)
+     {
+       RELOC_ENUM reloc_type;
+       unsigned char *opcode;
+       int old_fr_fix;
+ 
+       /* Now this symbol has not been defined in this file. Hence we will
+          have to create a fixup */
+       int size = 2;		/* This is for the prefix instruction */
+ 
+       if (fragP->fr_subtype == EXPLICT_LONG_PREFIX)
+ 	fragP->fr_subtype = LONG_PREFIX;
+ 
+       if (S_GET_SEGMENT (fragP->fr_symbol) != segment
+ 	  && ((!(fragP->fr_subtype) == EXPLICT_LONG_PREFIX)))
+ 	fragP->fr_subtype = ABSOLUTE_ADDR_FOR_DATA;
+ 
+       reloc_type =
+ 	(fragP->fr_subtype ? fragP->fr_subtype : ABSOLUTE_ADDR_FOR_DATA);
+ 
+       fragP->fr_subtype = reloc_type;
+ 
+       if (reloc_type == SHORT_PREFIX)
+ 	size = 0;
+       old_fr_fix = fragP->fr_fix;
+       opcode = (unsigned char *) fragP->fr_opcode;
+ 
+       fragP->fr_fix += (size);
+ 
+       fix_new (fragP, old_fr_fix - 2, size + 2,
+ 	       fragP->fr_symbol, fragP->fr_offset, 0, reloc_type);
+       frag_wane (fragP);
+       return fragP->fr_fix - old_fr_fix;
+     }
+ 
+   if (fragP->fr_subtype == SHORT_PREFIX)
+     {
+       fragP->fr_subtype = SHORT_PREFIX;
+       return 0;
+     }
+ 
+   if (fragP->fr_subtype == NO_PREFIX || fragP->fr_subtype == LONG_PREFIX)
+     {
+ 
+       unsigned long instr;
+       unsigned long call_addr;
+       long diff;
+       fragS *f;
+       diff = diff ^ diff;;
+       call_addr = call_addr ^ call_addr;
+       instr = 0;
+       f = NULL;
+ 
+       /* segment_info_type *seginfo = seg_info (segment); */
+       instr = fragP->fr_address + fragP->fr_fix - 2;
+ 
+       /* This is the offset if it is a PC relative jump */
+       call_addr = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
+       diff = (call_addr - instr);
+       if (diff >= (-128 * 2) && diff <= (2 * 127))
+ 	{
+ 	  fragP->fr_subtype = NO_PREFIX;
+ 	  return 0;
+ 	  /* Now as offset is an 8 bit value, we will pass that to the jump
+ 	     instruction directly. */
+ 	}
+       else
+ 	{
+ 	  fragP->fr_subtype = LONG_PREFIX;
+ 	  return 2;
+ 	}
+     }
+ 
+   as_fatal (_
+ 	    ("Illegal Reloc type in md_estimate_size_before_relax for line : %d"),
+ 	    frag_now->fr_line);
+   return 0;
+ }
+ 
+ /* Equal to MAX_PRECISION in atof-ieee.c */
+ #define MAX_LITTLENUMS 6
+ 
+ /* Turn a string in input_line_pointer into a floating point constant of type 
+    TYPE, and store the appropriate bytes in *LITP.  The number of LITTLENUMS
+    emitted is stored in *SIZEP.  An error message is returned, or NULL on OK. 
+  */
+ char *
+ md_atof (type, litP, sizeP)
+      int type;
+      char *litP;
+      int *sizeP;
+ {
+   int prec;
+   LITTLENUM_TYPE words[4];
+   char *t;
+   int i;
+ 
+   switch (type)
+     {
+     case 'f':
+       prec = 2;
+       break;
+ 
+     case 'd':
+       prec = 2;
+       /* The size of Double has been changed to 2 words ie 32 bits */
+       /* prec = 4; */
+       break;
+ 
+     default:
+       *sizeP = 0;
+       return _("bad call to md_atof");
+     }
+ 
+   t = atof_ieee (input_line_pointer, type, words);
+   if (t)
+     input_line_pointer = t;
+ 
+   *sizeP = prec * 2;
+ 
+   for (i = prec - 1; i >= 0; i--)
+     {
+       md_number_to_chars (litP, (valueT) words[i], 2);
+       litP += 2;
+     }
+   return NULL;
+ 
+ }
+ 
+ void
+ maxq20_cons_fix_new (frag, off, len, exp)
+      fragS *frag;
+      unsigned int off;
+      unsigned int len;
+      expressionS *exp;
+ {
+ 
+   int r = 0;			/* ABSOLUTE_ADDR_FOR_DATA */
+ 
+   switch (len)
+     {
+     case 2:
+       r = MAXQ_WORDDATA;	/* Word+n */
+       break;
+     case 4:
+       r = MAXQ_LONGDATA;	/* Long+n */
+       break;
+     }
+ 
+   fix_new_exp (frag, off, len, exp, 0, r);
+   return;			/* This function has to modified as well */
+ }
+ 
+ short
+ tc_coff_fix2rtype (fixP)
+      fixS *fixP;
+ {
+ 
+   return fixP->fx_r_type;
+ 
+ }
+ 
+ int
+ tc_coff_sizemachdep (fragP)
+      fragS *fragP;
+ {
+   if (fragP->fr_next)
+     return (fragP->fr_next->fr_address - fragP->fr_address);
+   else
+     return 0;
+ }
+ 
+ /* GAS will call this for every rs_machine_dependent fragment. The
+    instruction is compleated using the data from the relaxation pass. It may
+    also create any necessary relocations.  */
+ #ifdef BFD_ASSEMBLER
+ 
+ void
+ md_convert_frag (headers, seg, fragP)
+      bfd *headers ATTRIBUTE_UNUSED;
+      segT seg ATTRIBUTE_UNUSED;
+      fragS *fragP;
+ 
+ #else
+ 
+ void
+ md_convert_frag (headers, sec, fragP)
+      object_headers *headers ATTRIBUTE_UNUSED;
+      segT sec ATTRIBUTE_UNUSED;
+      fragS *fragP;
+ 
+ #endif
+ 
+ {
+   unsigned char *opcode;
+   offsetT target_address;
+   offsetT opcode_address;
+   offsetT displacement_from_opcode_start;
+   int address;
+   opcode = fragP->fr_opcode;
+   address = 0;
+   target_address = opcode_address = displacement_from_opcode_start = 0;
+ 
+   target_address =
+     (S_GET_VALUE (fragP->fr_symbol) / MAXQ_OCTETS_PER_BYTE) +
+     (fragP->fr_offset / MAXQ_OCTETS_PER_BYTE);
+ 
+   opcode_address =
+     (fragP->fr_address / MAXQ_OCTETS_PER_BYTE) +
+     ((fragP->fr_fix - 2) / MAXQ_OCTETS_PER_BYTE);
+ 
+   displacement_from_opcode_start = (target_address - opcode_address);
+ 
+   if ((displacement_from_opcode_start >= -128
+        && displacement_from_opcode_start <= 127)
+       && (fragP->fr_subtype == SHORT_PREFIX
+ 	  || fragP->fr_subtype == NO_PREFIX))
+ 
+     /* Its a displacement */
+     {
+       char *p = (char *) &opcode[0];
+ 
+       *p = (char) displacement_from_opcode_start;
+ 
+     }
+ 
+   else
+     /* Its an absolute 16 bit jump. Now we have to load the prefix operator
+        with the upper 8 bits.  */
+     {
+ 
+       if (fragP->fr_subtype == SHORT_PREFIX)	/* If its a option for short */
+ 	{
+ 	  as_bad (_("Cant make long jump/call into short jump/call : %d"),
+ 		  fragP->fr_line);
+ 	  return;
+ 	}
+ 
+       else
+ 	{
+ 	  /* Check whether the symbol has been resolved or not. Otherwise we
+ 	     will have to generate a fixup.  */
+ 
+ 	  if (fragP->fr_subtype != SHORT_PREFIX)
+ 	    {
+ 	      RELOC_ENUM reloc_type;
+ 	      unsigned char *opcode;
+ 	      int old_fr_fix;
+ 	      /* Now this is a basolute jump/call. Hence we will have to
+ 	         create a fixup.  */
+ 
+ 	      int size = 2;	/* This is for the prefix instruction */
+ 
+ 	      if (fragP->fr_subtype == NO_PREFIX)
+ 		fragP->fr_subtype = LONG_PREFIX;
+ 
+ 	      reloc_type =
+ 		(fragP->fr_subtype ? fragP->fr_subtype : LONG_PREFIX);
+ 
+ 	      if (reloc_type == 1)
+ 		size = 0;
+ 	      old_fr_fix = fragP->fr_fix;
+ 	      opcode = (unsigned char *) fragP->fr_opcode;
+ 
+ 	      fragP->fr_fix += (size);
+ 
+ 	      fix_new (fragP, old_fr_fix - 2, size + 2,
+ 		       fragP->fr_symbol, fragP->fr_offset, 0, reloc_type);
+ 	      frag_wane (fragP);
+ 
+ 	    }
+ 	}
+ 
+     }
+ }
+ 
+ long
+ md_pcrel_from (fixP)
+      fixS *fixP;
+ {
+   return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
+ }
+ 
+ #if 0
+ /* Not required any more Handling of the org directive which just adds nop,
+    which is a 16 bit opcode, instead of zeros.  */
+ 
+ static segT
+ get_segmented_expression (expP)
+      register expressionS *expP;
+ {
+   register segT retval;
+ 
+   retval = expression (expP);
+   if (expP->X_op == O_illegal
+       || expP->X_op == O_absent || expP->X_op == O_big)
+     {
+       as_bad (_("expected address expression"));
+       expP->X_op = O_constant;
+       expP->X_add_number = 0;
+       retval = absolute_section;
+     }
+   return retval;
+ }
+ 
+ static segT
+ get_known_segmented_expression (expP)
+      register expressionS *expP;
+ {
+   register segT retval;
+ 
+   if ((retval = get_segmented_expression (expP)) == undefined_section)
+     {
+       /* There is no easy way to extract the undefined symbol from the
+          expression.  */
+       if (expP->X_add_symbol != NULL
+ 	  && S_GET_SEGMENT (expP->X_add_symbol) != expr_section)
+ 	as_warn (_("symbol \"%s\" undefined; zero assumed"),
+ 		 S_GET_NAME (expP->X_add_symbol));
+       else
+ 	as_warn (_("some symbol undefined; zero assumed"));
+       retval = absolute_section;
+       expP->X_op = O_constant;
+       expP->X_add_number = 0;
+     }
+   know (retval == absolute_section || SEG_NORMAL (retval));
+   return (retval);
+ }
+ 
+ /* This function handles the org psedo-op .org new-lc, fill.  */
+ void
+ do_orgb (ignore)
+      int ignore ATTRIBUTE_UNUSED;
+ {
+   register segT segment;
+   expressionS exp;
+   register long fill;
+   int n_fill;
+   int max;
+ 
+ #ifdef md_flush_pending_output
+   md_flush_pending_output ();
+ #endif
+ 
+   max = 0;
+   n_fill = 1;
+   segment = get_known_segmented_expression (&exp);
+   if (*input_line_pointer == ',')
+     {
+       input_line_pointer++;
+       fill = get_absolute_expression ();
+     }
+   else
+     {
+       if (subseg_text_p (now_seg))
+ 	{
+ 	  n_fill = 2;
+ 	  fill = NOP_OPCODE;
+ 	}
+       fill = 0;
+     }
+ 
+   if (!need_pass_2)
+     {
+       if (segment != now_seg && segment != absolute_section)
+ 	as_bad (_("invalid segment \"%s\""), segment_name (segment));
+ 
+       if (now_seg == absolute_section)
+ 	{
+ 	  if (fill != 0)
+ 	    as_warn (_("ignoring fill value in absolute section"));
+ 
+ 	  if (exp.X_op != O_constant)
+ 	    {
+ 	      as_bad (_
+ 		      ("only constant offsets supported in absolute section"));
+ 	      exp.X_add_number = 0;
+ 	    }
+ 	  abs_section_offset = exp.X_add_number;
+ 	}
+       else
+ 	{
+ 	  char *p;
+ 	  symbolS *sym = exp.X_add_symbol;
+ 
+ 	  /* TO convert into word OCTETS_PER_BYTE; */
+ 	  offsetT off = exp.X_add_number * 2;
+ 
+ 	  if (exp.X_op != O_constant && exp.X_op != O_symbol)
+ 	    {
+ 	      /* Handle complex expressions.  */
+ 	      sym = make_expr_symbol (&exp);
+ 	      off = 0;
+ 	    }
+ 
+ 	  p = frag_var (rs_org, n_fill, n_fill, (relax_substateT) max,
+ 			(symbolS *) 0, (offsetT) off, (char *) 0);
+ 
+ 	  if (n_fill == 2)
+ 	    {
+ 
+ 	      *p++ = 0x3A;	/* NOP_OPCODE */
+ 	      *p = 0xDA;
+ 
+ 	    }
+ 
+ 	  else
+ 	    {
+ 	      *p = fill;
+ 
+ 	    }
+ 
+ 	}			/* else */
+ 
+     }				/* if need_pass==2 */
+ 
+ }				/* EOF */
+ 
+ #endif
+ 
+ /* Writes the val to the buf, where n is the nuumber of bytes to write.  */
+ void
+ maxq_number_to_chars (buf, val, n)
+      char *buf;
+      valueT val;
+      int n;
+ {
+   if (target_big_endian)
+     /* This function defined in write.c */
+     number_to_chars_bigendian (buf, val, n);
+ 
+   else
+     number_to_chars_littleendian (buf, val, n);
+ 
+ }
+ 
+ /* GAS will call this for each fixup. It's main objective is to store the
+    correct value in the object file. 'fixup_segment' performs the generic
+    overflow check on the 'valueT *val' argument after md_apply_fix3 returns.
+    If the overflow check is relevant for the target machine, then
+    'md_apply_fix3' should modify 'valueT *val', typically to the value stored 
+    in the object file (not to be done in MAXQ).  */
+ 
+ void
+ md_apply_fix3 (fixP, valT, seg)
+      fixS *fixP;
+      valueT *valT;
+      segT seg ATTRIBUTE_UNUSED;
+ {
+ 
+   char *p = fixP->fx_frag->fr_literal + fixP->fx_where;
+   char *frag_to_fix_at =
+     fixP->fx_frag->fr_literal + fixP->fx_frag->fr_fix - 2;
+ 
+   if (fixP)
+     {
+       if (fixP->fx_frag && valT)
+ 	{
+ 
+ 	  /* If the relaxation substate is not defined we make it equal to
+ 	     the kind of relocation the fixup is generated for.  */
+ 	  if (!fixP->fx_frag->fr_subtype)
+ 	    fixP->fx_frag->fr_subtype = fixP->fx_r_type;
+ 
+ 	  /* For any instruction in which either we have specified an
+ 	     absolute address or it is a long jump we need to add a PFX0
+ 	     instruction to it. In this case as the instruction has already
+ 	     being written at 'fx_where' in the frag we copy it at the end of 
+ 	     the frag(which is where the relocation was generated) as when
+ 	     the relocation is generated the frag is grown by 2 type, this is 
+ 	     where we copy the contents of fx_where and add a pfx0 at
+ 	     fx_where */
+ 	  if ((fixP->fx_frag->fr_subtype == ABSOLUTE_ADDR_FOR_DATA) ||
+ 	      (fixP->fx_frag->fr_subtype == LONG_PREFIX))
+ 
+ 	    {
+ 	      *(frag_to_fix_at + 1) = *(p + 1);
+ 	      maxq_number_to_chars (p + 1, PFX0, 1);
+ 
+ 	    }
+ 
+ #ifdef BFD_ASSEMBLER
+ 	  /* Remember value for tc_gen_reloc.  */
+ 	  fixP->fx_addnumber = *valT;
+ #endif
+ 	}
+ 
+       /* This prob can be fixed by defining tc_fix_adjustable */
+ #ifndef BFD_ASSEMBLER
+       if (fixP->fx_addsy)
+ 	{
+ 	  if (S_GET_SEGMENT (fixP->fx_addsy))
+ 	    segment_info[S_GET_SEGMENT (fixP->fx_addsy)].dot = NULL;
+ 	}
+ #endif
+ 
+       /* Some fixups generated by GAS which gets resovled before this this
+          func. is called need to be wriiten to the frag as here we are going
+          to go away with the relocations fx_done=1.  */
+       if (fixP->fx_addsy == NULL)
+ 	{
+ 	  maxq_number_to_chars (p, *valT, fixP->fx_size);
+ 	  fixP->fx_addnumber = *valT;
+ 	  fixP->fx_done = 1;
+ 
+ 	}
+ 
+       return;
+     }
+ }
+ 
+ /* Tables for lexical analysis */
+ static char mnemonic_chars[256];
+ static char register_chars[256];
+ static char operand_chars[256];
+ static char identifier_chars[256];
+ static char digit_chars[256];
+ 
+ /* Lexical Macros */
+ #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char)(x)])
+ #define is_register_char(x) (register_chars[(unsigned char)(x)])
+ #define is_operand_char(x)  (operand_chars[(unsigned char)(x)])
+ #define is_space_char(x) (x==' ')
+ #define is_identifier_char(x) (identifier_chars[(unsigned char)(x)])
+ #define is_digit_char(x) (identifier_chars[(unsigned char)(x)])
+ 
+ /* Special characters for operands */
+ static char operand_special_chars[] = "[]@.-+";
+ 
+ /* md_assemble() will always leave the instruction passed to it unaltered. To 
+    do this we store the instruction in a special stack */
+ static char save_stack[32];
+ static char *save_stack_p;
+ 
+ #define END_STRING_AND_SAVE(s) \
+         do                     \
+         {                      \
+           *save_stack_p++=*(s);\
+           *s='\0';             \
+         }                      \
+         while(0)
+ 
+ #define RESTORE_END_STRING(s)    \
+         do                       \
+         {                        \
+           *(s)=*(--save_stack_p);\
+         }                        \
+         while(0)
+ 
+ /* The instruction we are assembling */
+ static maxq20_insn i;
+ 
+ /* The current template */
+ static MAXQ20_OPCODES *current_templates;
+ 
+ /* The displacement operand if any */
+ static expressionS disp_expressions;
+ 
+ /* Current Operand we are working on (0:1st operand,1:2nd operand) */
+ static int this_operand;
+ 
+ /* The prefix instruction if used */
+ static char PFX_INSN[2];
+ static char INSERT_BUFFER[2];
+ 
+ /* For interface with expression() ????? */
+ extern char *input_line_pointer;
+ 
+ /*----------------------------- THE HASH TABLES----------------------------*/
+ /* Operand Hash Table */
+ static struct hash_control *op_hash;
+ 
+ /* Register Hash Table */
+ static struct hash_control *reg_hash;
+ 
+ /* Memory reference Hash Table */
+ static struct hash_control *mem_hash;
+ 
+ /* Bit hash table */
+ static struct hash_control *bit_hash;
+ 
+ /* Memory Access syntax table */
+ static struct hash_control *mem_syntax_hash;
+ 
+ /*------------------------------------------------------------------------*/
+ 
+ /* This is a const array of type 'pseudo_typeS'. It is a mapping from
+    pseudo-op names to functions. You should use this table to implement
+    pseudo-ops which are specific to the cpu */
+ const pseudo_typeS md_pseudo_table[] = {
+ 
+   {"int", cons, 2},		/* size of 'int' has been changed to 1 word
+ 				   (i.e) 16 bits */
+ 
+ #if 0
+   {"orgb", s_org, 2},
+   {"org", do_orgb, 2},		/* handles the org psedo-op in do_orgb. This
+ 				   handling makes enables us to add nop
+ 				   (0x3ada) insted of the default 0 to fill
+ 				   with. Not Used.  */
+ #endif
+ 
+   {NULL, 0, 0},
+ 
+ };
+ 
+ #if defined(BFD_HEADERS)
+ #ifdef RELSZ
+ const int md_reloc_size = RELSZ;	/* Coff headers */
+ #else
+ const int md_reloc_size = 12;	/* something else headers */
+ #endif
+ #else
+ const int md_reloc_size = 12;	/* Not bfdized */
+ #endif
+ 
+ #define SET_PFX_ARG(x) (PFX_INSN[1] = x)
+ 
+ /*********************FUNCTION PROTOTYPES*****************************/
+ static char *parse_insn PARAMS ((char *line, char *mnemonic));
+ static char *parse_operands PARAMS ((char *l, const char *mnemonic));
+ static int maxq20_operand PARAMS ((char *operand_string));
+ static int match_template PARAMS ((void));
+ static int match_filters PARAMS ((void));
+ static reg_entry *parse_register PARAMS ((char *reg_string, char **end_op));
+ static reg_bit *parse_register_bit PARAMS ((char *reg_string, char **end_op));
+ static mem_access *maxq20_mem_access
+ PARAMS ((char *mem_string, char **end_op));
+ static void output_insn PARAMS ((void));
+ static void output_data
+ PARAMS ((fragS * insn_start_frag, offsetT insn_start_off));
+ static void output_disp
+ PARAMS ((fragS * insn_start_frag, offsetT insn_start_off));
+ static int decode_insn PARAMS ((void));
+ static int match_operands PARAMS ((int, MAX_ARG_TYPE, MAX_ARG_TYPE, int));
+ static void pfx_for_imm_val PARAMS ((int));
+ static int maxq20_displacement PARAMS ((char *, char *));
+ static int maxq20_immediate PARAMS ((char *));
+ static int pwr PARAMS ((int, int));
+ static symbolS *maxq20_data PARAMS ((char *));
+ static void set_prefix PARAMS ((void));
+ static unsigned char IS_A_LSINSTR PARAMS ((const char *));
+ static void LS_Processing PARAMS ((const char *));
+ static char check_for_parse PARAMS ((const char *));
+ static int extract_int_val PARAMS ((const char *));
+ 
+ /* function prototypes */
+ static reg_entry *parse_reg_by_index PARAMS ((char *));
+ 
+ /* This function sets the PFX value coresponding to the specs. Source
+    Destination Index Selection ---------------------------------- Write To|
+    SourceRegRange | Dest Addr Range
+    ------------------------------------------------------ PFX[0] | 0h-Fh |
+    0h-7h PFX[1] | 10h-1Fh | 0h-7h PFX[2] | 0h-Fh | 8h-Fh PFX[3] | 10h-1Fh |
+    8h-Fh PFX[4] | 0h-Fh | 10h-17h PFX[5] | 10h-1Fh | 10h-17h PFX[6] | 0h-Fh | 
+    18h-1Fh PFX[7] | 0h-Fh | 18h-1Fh */
+ void
+ set_prefix ()
+ {
+   short int src_index = 0, dst_index = 0;
+ 
+   if (i.operands == 0)
+     return;
+   if (i.operands == 1)		/* Only SRC is Present */
+     {
+       if (i.types[0] == REG)
+ 	{
+ 	  if (!strcmp (i.op.name, "POP") || !strcmp (i.op.name, "POPI"))
+ 	    {
+ 	      dst_index = i.maxq20_op[0].reg[0].Mod_index;
+ 	      src_index = 0x00;
+ 	    }
+ 	  else			/* Only SRC is Present */
+ 	    {
+ 	      src_index = i.maxq20_op[0].reg[0].Mod_index;
+ 	      dst_index = 0x00;
+ 	    }
+ 	}			/* i.types[0] == REG */
+     }
+ 
+   if (i.operands == 2)
+     {
+       if (i.types[0] == REG && i.types[1] == REG)
+ 	{
+ 	  dst_index = i.maxq20_op[0].reg[0].Mod_index;
+ 	  src_index = i.maxq20_op[1].reg[0].Mod_index;
+ 	}
+       else if (i.types[0] != REG && i.types[1] == REG)	/* DST is Absent */
+ 	{
+ 	  src_index = i.maxq20_op[1].reg[0].Mod_index;
+ 	  dst_index = 0x00;
+ 	}
+       else if (i.types[0] == REG && i.types[1] != REG)	/* Id SRC is Absent */
+ 	{
+ 	  dst_index = i.maxq20_op[0].reg[0].Mod_index;
+ 	  src_index = 0x00;
+ 	}
+       else if (i.types[0] == BIT && i.maxq20_op[0].r_bit)
+ 	{
+ 	  dst_index = i.maxq20_op[0].r_bit->reg->Mod_index;
+ 	  src_index = 0x00;
+ 	}
+ 
+       else if (i.types[1] == BIT && i.maxq20_op[1].r_bit)
+ 	{
+ 	  dst_index = 0x00;
+ 	  src_index = i.maxq20_op[1].r_bit->reg->Mod_index;
+ 	}
+     }
+ 
+   if (src_index >= 0x00 && src_index <= 0xF)
+     {
+       if (dst_index >= 0x00 && dst_index <= 0x07)
+ 	{
+ 	  /* Set PFX[0] */
+ 	  i.prefix = 0;
+ 	}
+       else if (dst_index >= 0x08 && dst_index <= 0x0F)
+ 	{
+ 	  /* Set PFX[2] */
+ 	  i.prefix = 2;
+ 	}
+       else if (dst_index >= 0x10 && dst_index <= 0x17)
+ 	{
+ 	  /* Set PFX[4] */
+ 	  i.prefix = 4;
+ 	}
+       else if (dst_index >= 0x18 && dst_index <= 0x1F)
+ 	{
+ 	  /* Set PFX[6] */
+ 	  i.prefix = 6;
+ 	}
+       return;
+     }
+   else if (src_index >= 0x10 && src_index <= 0x1F)
+     {
+       if (dst_index >= 0x00 && dst_index <= 0x07)
+ 	{
+ 	  /* Set PFX[1] */
+ 	  i.prefix = 1;
+ 	}
+       else if (dst_index >= 0x08 && dst_index <= 0x0F)
+ 	{
+ 	  /* Set PFX[3] */
+ 	  i.prefix = 3;
+ 	}
+       else if (dst_index >= 0x10 && dst_index <= 0x17)
+ 	{
+ 	  /* Set PFX[5] */
+ 	  i.prefix = 5;
+ 	}
+       else if (dst_index >= 0x18 && dst_index <= 0x1F)
+ 	{
+ 	  /* Set PFX[7] */
+ 	  i.prefix = 7;
+ 	}
+       return;
+     }
+ }
+ 
+ /* These are the basic machine dependent initialisations w Function
+    md_begin() */
+ void
+ md_begin ()
+ {
+   const char *hash_err = NULL;
+   int c = 0;
+   char *p;
+   const MAXQ20_OPCODE_INFO *optab;
+   MAXQ20_OPCODES *core_optab;	/* For opcodes of the same name. This will
+ 				   be inserted into the hash table */
+   struct reg *reg_tab;
+   struct mem_access_syntax *memsyntab;
+   struct mem_access *memtab;
+   struct bit_name *bittab;
+ 
+   /* initilize pherioipheral modules */
+   pmmain ();
+ 
+   /* Initialise the opcode hash table */
+   op_hash = hash_new ();
+ 
+   optab = op_table;		/* Initialise it to the first entry of the
+ 				   maxq20 operand table */
+ 
+   /* Setup for loop.  */
+   core_optab = (MAXQ20_OPCODES *) xmalloc (sizeof (MAXQ20_OPCODES));
+   core_optab->start = optab;
+ 
+   while (1)
+     {
+       ++optab;
+       if (optab->name == NULL || strcmp (optab->name, (optab - 1)->name) != 0)
+ 	{
+ 
+ 	  /* different name --> ship out current template list; add to hash
+ 	     table; & begin anew.  */
+ 	  core_optab->end = optab;
+ #ifdef MAXQ10S
+ 	  if (max_version == 10)
+ 	    {
+ 	      if (((optab - 1)->arch == MAXQ10) || ((optab - 1)->arch == MAX))
+ 		{
+ 		  hash_err = hash_insert (op_hash,
+ 					  (optab - 1)->name,
+ 					  (PTR) core_optab);
+ 		}
+ 	    }
+ 	  else if (max_version == 20)
+ 	    {
+ 	      /* MAXQ20 */
+ 	      if (((optab - 1)->arch == MAXQ20) || ((optab - 1)->arch == MAX))
+ 		{
+ #endif
+ 		  hash_err = hash_insert (op_hash,
+ 					  (optab - 1)->name,
+ 					  (PTR) core_optab);
+ #if MAXQ10S
+ 		}
+ 	    }
+ 	  else
+ 	    {
+ 	      as_fatal (_("Internal Error: Illegal Architecure specified"));
+ 	    }
+ 
+ #endif
+ 	  if (hash_err)
+ 	    {
+ 	      as_fatal (_("Internal Error:  Can't hash %s: %s"),
+ 			(optab - 1)->name, hash_err);
+ 	    }
+ 	  if (optab->name == NULL)
+ 	    break;
+ 	  core_optab = (MAXQ20_OPCODES *) xmalloc (sizeof (MAXQ20_OPCODES));
+ 	  core_optab->start = optab;
+ 	}
+     }
+ 
+   /* Initialise a new register table */
+   reg_hash = hash_new ();
+ 
+   for (reg_tab = system_reg_table;
+        reg_tab <
+        (system_reg_table +
+ 	sizeof (system_reg_table) / sizeof (system_reg_table[0])); reg_tab++)
+     {
+ #if MAXQ10S
+       switch (max_version)
+ 	{
+ 	case 10:		/* MAXQ10 */
+ 	  if ((reg_tab->arch == MAXQ10) || (reg_tab->arch == MAX))
+ 	    {
+ 	      hash_err =
+ 		hash_insert (reg_hash, reg_tab->reg_name, (PTR) reg_tab);
+ 	    }
+ 	  break;
+ 
+ 	case 20:		/* MAXQ20 */
+ 	  if ((reg_tab->arch == MAXQ20) || (reg_tab->arch == MAX))
+ 	    {
+ #endif
+ 	      hash_err =
+ 		hash_insert (reg_hash, reg_tab->reg_name, (PTR) reg_tab);
+ 
+ #if MAXQ10S
+ 	    }
+ 	  break;
+ 	default:
+ 	  as_fatal (_("Invalid architecture type"));
+ 	}
+ #endif
+ 
+       if (hash_err)
+ 	{
+ 	  as_fatal (_("Internal Error : Can't Hash %s : %s"),
+ 		    reg_tab->reg_name, hash_err);
+ 	}
+     }
+ 
+   /* Pheripheral Registers Entry */
+   for (reg_tab = new_reg_table;
+        reg_tab < (new_reg_table + num_of_reg - 1); reg_tab++)
+     {
+ 
+       hash_err = hash_insert (reg_hash, reg_tab->reg_name, (PTR) reg_tab);
+ 
+       if (hash_err)
+ 	{
+ 	  as_fatal (_("Internal Error : Can't Hash %s : %s"),
+ 		    reg_tab->reg_name, hash_err);
+ 
+ 	}
+ 
+     }
+ 
+   /* Initialise a new memory operand table */
+   mem_hash = hash_new ();
+ 
+   for (memtab = mem_table;
+        memtab < mem_table + sizeof (mem_table) / sizeof (mem_table[0]);
+        memtab++)
+     {
+       hash_err = hash_insert (mem_hash, memtab->name, (PTR) memtab);
+       if (hash_err)
+ 	{
+ 	  as_fatal (_("Internal Error : Can't Hash %s : %s"),
+ 		    memtab->name, hash_err);
+ 	}
+     }
+ 
+   bit_hash = hash_new ();
+ 
+   for (bittab = bit_table;
+        bittab < bit_table + sizeof (bit_table) / sizeof (bit_table[0]);
+        bittab++)
+     {
+       hash_err = hash_insert (bit_hash, bittab->name, (PTR) bittab);
+       if (hash_err)
+ 	{
+ 	  as_fatal (_("Internal Error : Can't Hash %s : %s"),
+ 		    bittab->name, hash_err);
+ 	}
+     }
+ 
+   mem_syntax_hash = hash_new ();
+ 
+   for (memsyntab = mem_access_syntax_table;
+        memsyntab <
+        mem_access_syntax_table +
+        sizeof (mem_access_syntax_table) / sizeof (mem_access_syntax_table[0]);
+        memsyntab++)
+     {
+       hash_err =
+ 	hash_insert (mem_syntax_hash, memsyntab->name, (PTR) memsyntab);
+       if (hash_err)
+ 	{
+ 	  as_fatal (_("Internal Error : Can't Hash %s : %s"),
+ 		    memsyntab->name, hash_err);
+ 	}
+     }
+ 
+   /* Initialise the lexical tables,mnemonic chars,operand chars */
+   {
+     for (c = 0; c < 256; c++)
+       {
+ 	if (ISDIGIT (c))
+ 	  {
+ 	    digit_chars[c] = c;
+ 	    mnemonic_chars[c] = c;
+ 	    operand_chars[c] = c;
+ 	    register_chars[c] = c;
+ 	  }
+ 	else if (ISLOWER (c))
+ 	  {
+ 	    mnemonic_chars[c] = c;
+ 	    operand_chars[c] = c;
+ 	    register_chars[c] = c;
+ 	  }
+ 	else if (ISUPPER (c))
+ 	  {
+ 	    mnemonic_chars[c] = TOLOWER (c);
+ 	    register_chars[c] = c;
+ 	    operand_chars[c] = c;
+ 	  }
+ 
+ 	if (ISALPHA (c) || ISDIGIT (c))
+ 	  {
+ 	    identifier_chars[c] = c;
+ 	  }
+ 	else if (c > 128)
+ 	  {
+ 	    identifier_chars[c] = c;
+ 	    operand_chars[c] = c;
+ 	  }
+       }
+ 
+     /* All the special characters */
+     register_chars['@'] = '@';
+     register_chars['+'] = '+';
+     register_chars['-'] = '-';
+     digit_chars['-'] = '-';
+     identifier_chars['_'] = '_';
+     identifier_chars['.'] = '.';
+     register_chars['['] = '[';
+     register_chars[']'] = ']';
+     operand_chars['_'] = '_';
+     operand_chars['#'] = '#';
+     mnemonic_chars['['] = '[';
+     mnemonic_chars[']'] = ']';
+ 
+     for (p = operand_special_chars; *p != '\0'; p++)
+       {
+ 	operand_chars[(unsigned char) *p] = (unsigned char) *p;
+       }
+   }
+ }
+ 
+ /* md_assemble - Parse Instr - Seprate menmonics and operands - lookup the
+    menmunonic in the operand table - Parse operands and populate the
+    structure/template - Match the operand with opcode and its validity -
+    Output Instr. */
+ void
+ md_assemble (line)
+      char *line;
+ {
+   int j;
+ 
+   char mnemonic[MAX_MNEM_SIZE];
+   char temp4prev[256];
+   static char prev_insn[256];
+ 
+   /* Initialize globals.  */
+   memset (&i, '\0', sizeof (i));
+   for (j = 0; j < MAX_OPERANDS; j++)
+     i.reloc[j] = NO_RELOC;
+ 
+   i.prefix = -1;
+   PFX_INSN[0] = 0;
+   PFX_INSN[1] = 0;
+   INSERT_BUFFER[0] = 0;
+   INSERT_BUFFER[1] = 0;
+ 
+   memcpy (temp4prev, line, strlen (line) + 1);
+ 
+   save_stack_p = save_stack;
+ 
+   line = (char *) parse_insn (line, mnemonic);
+   if (line == NULL)
+     return;
+ 
+   line = (char *) parse_operands (line, mnemonic);
+   if (line == NULL)
+     return;
+ 
+   /* Next, we find a template that matches the given insn, making sure the
+      overlap of the given operands types is consistent with the template
+      operand types.  */
+ 
+   if (!match_template ())
+     return;
+ 
+   /* In the MAXQ20, there are certain register combinations, and other
+      restrictions which are not allowed. We will try to resolve these right
+      now */
+   if (!match_filters ())
+     return;
+ 
+   /* check for the approprate PFX register */
+   set_prefix ();
+   pfx_for_imm_val (0);
+ 
+   if (!decode_insn ())		/* decode insn. */
+ 
+     need_pass_2 = 1;
+ 
+   /* Check for Exlipct PFX instruction */
+   if (PFX_INSN[0] && (strstr (prev_insn, "PFX") || strstr (prev_insn, "pfx")))
+     as_warn (_("Ineffective insntruction %s \n"), prev_insn);
+ 
+   memcpy (prev_insn, temp4prev, strlen (temp4prev) + 1);
+ 
+   /* We are ready to output the insn.  */
+   output_insn ();
+ 
+ }
+ 
+ /* parse_insn: Separate mnemonics and the operands.  */
+ static char *
+ parse_insn (line, mnemonic)
+      char *line;
+      char *mnemonic;
+ {
+   char *l = line;
+   char *token_start = l;
+   char *mnem_p;
+   char temp[MAX_MNEM_SIZE];
+   int ii = 0;
+   memset (temp, END_OF_INSN, MAX_MNEM_SIZE);
+   mnem_p = mnemonic;
+   while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
+     {
+       ii++;
+       mnem_p++;
+       if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
+ 	{
+ 	  as_bad (_("no such instruction: `%s'"), token_start);
+ 	  return NULL;
+ 	}
+       l++;
+     }				/* while */
+ 
+   if (!is_space_char (*l) && *l != END_OF_INSN)
+     {
+       as_bad (_("invalid character %s in mnemonic"), l);
+       return NULL;
+     }				/* if is_space */
+ 
+   while (ii)
+     {
+       temp[ii - 1] = toupper ((char) mnemonic[ii - 1]);
+       ii--;
+     }
+ 
+   LS_Processing (temp);
+ 
+   if (i.Instr_Prefix != 0 && IS_A_LSINSTR (temp))
+     memcpy (temp, temp + 1, MAX_MNEM_SIZE);	/* Skip the optional L-S */
+ 
+   /* Look up instruction (or prefix) via hash table.  */
+   current_templates = (MAXQ20_OPCODES *) hash_find (op_hash, temp);
+ 
+   if (current_templates != NULL)
+     {
+       return l;
+     }
+   else
+     {
+       as_bad (_("no such instruction: `%s'"), token_start);
+       return NULL;
+     }
+ 
+ }
+ 
+ /* Parse_operand takes as input instruction and operands and Parse operands
+    and makes entry in the template.  */
+ 
+ static char *
+ parse_operands (l, mnemonic)
+      char *l;
+      const char *mnemonic;
+ {
+   char *token_start;
+ 
+   /* 1 if operand is pending after ','. */
+   short int expecting_operand = 0;
+ 
+   /* Non-zero if operand parens not balanced.  */
+   short int paren_not_balanced;
+ 
+   int operand_ok;
+ 
+   /* For Overcoming Warning of unused variable */
+   if (mnemonic)
+     operand_ok = 0;
+ 
+   while (*l != END_OF_INSN)
+     {
+       /* Skip optional white space before operand.  */
+       if (is_space_char (*l))
+ 	++l;
+ 
+       if (!is_operand_char (*l) && *l != END_OF_INSN)
+ 	{
+ 	  as_bad (_("invalid character %c before operand %d"),
+ 		  (char) (*l), i.operands + 1);
+ 	  return NULL;
+ 	}
+       token_start = l;		/* after white space */
+ 
+       paren_not_balanced = 0;
+       while (paren_not_balanced || *l != ',')
+ 	{
+ 	  if (*l == END_OF_INSN)
+ 
+ 	    {
+ 	      if (paren_not_balanced)
+ 		{
+ 		  as_bad (_("unbalanced brackets in operand %d."),
+ 			  i.operands + 1);
+ 		  return NULL;
+ 		}
+ 	      else
+ 		break;		/* we are done */
+ 	    }
+ 	  else if (!is_operand_char (*l) && !is_space_char (*l))
+ 	    {
+ 	      as_bad (_("invalid character %c in operand %d"),
+ 		      (char) (*l), i.operands + 1);
+ 	      return NULL;
+ 	    }
+ 	  if (*l == '[')
+ 	    ++paren_not_balanced;
+ 	  if (*l == ']')
+ 	    --paren_not_balanced;
+ 	  l++;
+ 	}			/* while paren_not_balenced */
+ 
+       if (l != token_start)
+ 	{			/* Yes, we've read in another operand.  */
+ 	  this_operand = i.operands++;
+ 	  if (i.operands > MAX_OPERANDS)
+ 	    {
+ 	      as_bad (_("spurious operands; (%d operands/instruction max)"),
+ 		      MAX_OPERANDS);
+ 	      return NULL;
+ 	    }
+ 	  /* Now parse operand adding info to 'i' as we go along.  */
+ 	  END_STRING_AND_SAVE (l);
+ 
+ 	  operand_ok = maxq20_operand (token_start);
+ 
+ 	  RESTORE_END_STRING (l);
+ 
+ 	  if (!operand_ok)
+ 	    return NULL;
+ 	}
+       else
+ 	{
+ 	  if (expecting_operand)
+ 	    {
+ 	    expecting_operand_after_comma:
+ 	      as_bad (_("expecting operand after ','; got nothing"));
+ 	      return NULL;
+ 	    }
+ 	}
+       if (*l == ',')
+ 	{
+ 	  if (*(++l) == END_OF_INSN)
+ 	    {
+ 	      /* Just skip it, if it's \n complain.  */
+ 	      goto expecting_operand_after_comma;
+ 	    }
+ 	  expecting_operand = 1;
+ 
+ 	}
+     }
+   return l;
+ }
+ 
+ static reg_entry *
+ parse_reg_by_index (imm_start)
+      char *imm_start;
+ {
+   int k = 0, mid = 0, rid = 0, val = 0, j = 0;
+   char temp[4] = { 0 };
+   reg_entry *reg = NULL;
+ 
+   do
+     {
+       if (isdigit (imm_start[k]))
+ 	{
+ 	  temp[k] = imm_start[k] - '0';
+ 	}
+ 
+       else if (isalpha (imm_start[k])
+ 	       && (imm_start[k] = tolower (imm_start[k])) < 'g')
+ 	{
+ 	  temp[k] = 10 + (int) (imm_start[k] - 'a');
+ 	}
+ 
+       else if (imm_start[k] == 'h')
+ 	break;
+ 
+       else if (imm_start[k] == END_OF_INSN)
+ 	{
+ 	  imm_start[k] = 'd';
+ 	  break;
+ 	}
+ 
+       else
+ 	{
+ 	  return NULL;		/* not a hex digit */
+ 	}
+       k++;
+     }
+   while (imm_start[k] != '\n');
+ 
+   switch (imm_start[k])
+     {
+     case 'h':
+       for (j = 0; j < k; j++)
+ 	{
+ 	  val += temp[j] * pwr (16, k - j - 1);
+ 	}
+       break;
+     case 'd':
+       for (j = 0; j < k; j++)
+ 	{
+ 	  if (temp[j] > 9)
+ 	    {
+ 	      return NULL;	/* not a number */
+ 	    }
+ 	  val += temp[j] * pwr (10, k - j - 1);
+ 	  break;
+ 	}
+     }
+ 
+   /* get the module and register id's */
+   mid = val & 0x0f;
+   rid = (val >> 4) & 0x0f;
+ 
+   if (mid < 6)
+     {
+       /* search the pheripheral reg table. */
+       for (j = 0; j < num_of_reg; j++)
+ 	{
+ 	  if (new_reg_table[j].opcode == val)
+ 	    {
+ 	      reg = (reg_entry *) & new_reg_table[j];
+ 	      break;
+ 	    }
+ 	}
+     }
+ 
+   else
+     {
+       /* search the system register table. */
+       j = 0;
+       while (system_reg_table[j].reg_name != NULL)
+ 	{
+ 	  if (system_reg_table[j].opcode == val)
+ 	    {
+ 	      reg = (reg_entry *) & system_reg_table[j];
+ 	      break;
+ 	    }
+ 	  j++;
+ 	}
+     }
+ 
+   if (reg == NULL)
+     {
+       as_bad (_("Invalid register value %s"), imm_start);
+       return reg;
+     }
+ 
+ #if CHANGE_PFX
+   if (this_operand == 0 && reg != NULL)
+     {
+       if (reg->Mod_index > 7)
+ 	i.prefix = 2;
+       else
+ 	i.prefix = 0;
+     }
+ #endif
+   return (reg_entry *) reg;
+ }
+ 
+ /* Parse OPERAND_STRING into the maxq20_insn structure I.  Returns non-zero
+    on error.  */
+ 
+ static int
+ maxq20_operand (operand_string)
+      char *operand_string;
+ {
+   reg_entry *r = NULL;
+   reg_bit *rb = NULL;
+   mem_access *m = NULL;
+   char *end_op = NULL;
+   symbolS *sym = NULL;
+   char *base_string = NULL;
+   int ii = 0;
+ 
+   /* Start and end of displacement string expression (if found).  */
+   char *displacement_string_start = NULL;
+   char *displacement_string_end = NULL;
+ 
+   char case_str_op_string[MAX_OPERAND_SIZE + 1];	/* This maintains the 
+ 							   case sentivness */
+   char str_op_string[MAX_OPERAND_SIZE + 1];
+   char *org_case_op_string = case_str_op_string;
+   char *op_string = str_op_string;
+ 
+   memset (op_string, END_OF_INSN, (MAX_OPERAND_SIZE + 1));
+   memset (org_case_op_string, END_OF_INSN, (MAX_OPERAND_SIZE + 1));
+ 
+   memcpy (op_string, operand_string, strlen (operand_string) + 1);
+   memcpy (org_case_op_string, operand_string, strlen (operand_string) + 1);
+ 
+   ii = strlen (operand_string) + 1;
+ 
+   if (ii > MAX_OPERAND_SIZE)
+     {
+       as_bad (_("Size of Operand '%s' greater than %d"), op_string,
+ 	      MAX_OPERAND_SIZE);
+       return 0;
+     }
+ 
+   while (ii)
+     {
+       op_string[ii - 1] = toupper ((char) op_string[ii - 1]);
+       ii--;
+     }
+ 
+   if (is_space_char (*op_string))
+     ++op_string;
+ 
+   if (isxdigit (operand_string[0]))
+     {
+       /* Now the operands can start with an Integer. */
+       r = parse_reg_by_index (op_string);
+       if (r != NULL)
+ 	{
+ 	  if (is_space_char (*op_string))
+ 	    ++op_string;
+ 	  i.types[this_operand] = REG;	/* Set the type */
+ 	  i.maxq20_op[this_operand].reg = r;	/* Set the Register value */
+ 	  i.reg_operands++;
+ 	  return 1;
+ 	}
+ 
+       /* get the origanal string. */
+       memcpy (op_string, operand_string, strlen (operand_string) + 1);
+       ii = strlen (operand_string) + 1;
+ 
+       while (ii)
+ 	{
+ 	  op_string[ii - 1] = toupper ((char) op_string[ii - 1]);
+ 	  ii--;
+ 	}
+     }
+ 
+   /* check for flags. */
+   if (!strcmp (op_string, "Z"))
+     {
+       if (is_space_char (*op_string))
+ 	++op_string;
+ 
+       i.types[this_operand] = FLAG;	/* Set the type */
+       i.maxq20_op[this_operand].flag = FLAG_Z;	/* Set the Register value */
+ 
+       i.flag_operands++;
+ 
+       return 1;
+     }
+ 
+   else if (!strcmp (op_string, "NZ"))
+     {
+       if (is_space_char (*op_string))
+ 	++op_string;
+ 
+       i.types[this_operand] = FLAG;	/* Set the type */
+       i.maxq20_op[this_operand].flag = FLAG_NZ;	/* Set the Register value */
+       i.flag_operands++;
+       return 1;
+     }
+ 
+   else if (!strcmp (op_string, "NC"))
+     {
+       if (is_space_char (*op_string))
+ 	++op_string;
+ 
+       i.types[this_operand] = FLAG;	/* Set the type */
+       i.maxq20_op[this_operand].flag = FLAG_NC;	/* Set the Register value */
+       i.flag_operands++;
+       return 1;
+     }
+ 
+   else if (!strcmp (op_string, "E"))
+     {
+       if (is_space_char (*op_string))
+ 	++op_string;
+ 
+       i.types[this_operand] = FLAG;	/* Set the type */
+       i.maxq20_op[this_operand].flag = FLAG_E;	/* Set the Register value */
+ 
+       i.flag_operands++;
+ 
+       return 1;
+     }
+ 
+   else if (!strcmp (op_string, "S"))
+     {
+       if (is_space_char (*op_string))
+ 	++op_string;
+ 
+       i.types[this_operand] = FLAG;	/* Set the type */
+       i.maxq20_op[this_operand].flag = FLAG_S;	/* Set the Register value */
+ 
+       i.flag_operands++;
+ 
+       return 1;
+     }
+ 
+   else if (!strcmp (op_string, "C"))
+     {
+       if (is_space_char (*op_string))
+ 	++op_string;
+ 
+       i.types[this_operand] = FLAG;	/* Set the type */
+       i.maxq20_op[this_operand].flag = FLAG_C;	/* Set the Register value */
+ 
+       i.flag_operands++;
+ 
+       return 1;
+     }
+ 
+   else if (!strcmp (op_string, "NE"))
+     {
+ 
+       if (is_space_char (*op_string))
+ 	++op_string;
+ 
+       i.types[this_operand] = FLAG;	/* Set the type */
+ 
+       i.maxq20_op[this_operand].flag = FLAG_NE;	/* Set the Register value */
+ 
+       i.flag_operands++;
+ 
+       return 1;
+     }
+ 
+   /* CHECK FOR REGISTER BIT */
+   else if ((rb = parse_register_bit (op_string, &end_op)) != NULL)
+     {
+       op_string = end_op;
+ 
+       if (is_space_char (*op_string))
+ 	++op_string;
+ 
+       i.types[this_operand] = BIT;
+ 
+       i.maxq20_op[this_operand].r_bit = rb;
+ 
+       i.bit_operands++;
+ 
+       return 1;
+     }
+ 
+   else if (*op_string == IMMEDIATE_PREFIX)	/* FOR IMMEDITE */
+     {
+       if (is_space_char (*op_string))
+ 	++op_string;
+ 
+       i.types[this_operand] = IMM;
+ 
+       if (!maxq20_immediate (op_string))
+ 	{
+ 	  as_bad (_("illegal immediate operand '%s'"), op_string);
+ 	  return 0;
+ 	}
+       return 1;
+     }
+ 
+   else if (*op_string == ABSOLUTE_PREFIX || !strcmp (op_string, "NUL"))
+     {
+      if (is_space_char (*op_string))
+ 	++op_string;
+ 
+       /* For new requiremnt of copiler of for, @(BP,cons) */
+       if (check_for_parse (op_string))
+ 	{
+ 	  memset (op_string, '\0', strlen (op_string) + 1);
+ 	  memcpy (op_string, "@BP[OFFS]\0", 11);
+ 	}
+ 
+       i.types[this_operand] = MEM;
+ 
+       if ((m = maxq20_mem_access (op_string, &end_op)) == NULL)
+ 	{
+ 	  as_bad (_("Invalid operand for memory access '%s'"), op_string);
+ 	  return 0;
+ 	}
+       i.maxq20_op[this_operand].mem = m;
+ 
+       i.mem_operands++;
+ 
+       return 1;
+     }
+ 
+   else if ((r = parse_register (op_string, &end_op)) != NULL)	/* check for
+ 								   register. */
+     {
+       op_string = end_op;
+ 
+       if (is_space_char (*op_string))
+ 	++op_string;
+ 
+       i.types[this_operand] = REG;	/* Set the type */
+       i.maxq20_op[this_operand].reg = r;	/* Set the Register value */
+       i.reg_operands++;
+       return 1;
+     }
+ 
+   if (this_operand == 1)
+     {
+       /* Changed for orginal case of data refrence on 30 Nov 2003 */
+       /* The operand can either be a data reference or a symbol reference */
+       if ((sym = maxq20_data (org_case_op_string)) != NULL)	/* Check for data memory */
+ 	{
+ 	  while (is_space_char (*op_string))
+ 	    ++op_string;
+ 
+ 	  /* Set the type of the operand */
+ 	  i.types[this_operand] = DATA;
+ 
+ 	  /* Set the value of the data */
+ 	  i.maxq20_op[this_operand].data = sym;
+ 	  i.data_operands++;
+ 
+ 	  return 1;
+ 	}
+ 
+       else if (is_digit_char (*op_string) || is_identifier_char (*op_string))
+ 	{
+ 	  /* This is a memory reference of some sort. char *base_string;
+ 	     Start and end of displacement string expression (if found). char 
+ 	     *displacement_string_start; char *displacement_string_end. */
+ 	  base_string = org_case_op_string + strlen (org_case_op_string);
+ 
+ 	  --base_string;
+ 	  if (is_space_char (*base_string))
+ 	    --base_string;
+ 
+ 	  /* If we only have a displacement, set-up for it to be parsed
+ 	     later.  */
+ 	  displacement_string_start = org_case_op_string;
+ 	  displacement_string_end = base_string + 1;
+ 	  if (displacement_string_start != displacement_string_end)
+ 	    {
+ 	      if (!maxq20_displacement (displacement_string_start,
+ 					displacement_string_end))
+ 		{
+ 		  as_bad (_("illegal displacement operand "));
+ 		  return 0;
+ 		}
+ 	      /* A displacement operand found. */
+ 	      i.types[this_operand] = DISP;	/* Set the type */
+ 	      return 1;
+ 	    }
+ 	}
+     }
+   
+   /* check for displacement. */
+   else if (is_digit_char (*op_string) || is_identifier_char (*op_string))
+     {
+       /* This is a memory reference of some sort. char *base_string;
+          Start and end of displacement string expression (if found). char
+          *displacement_string_start; char *displacement_string_end; */
+       base_string = org_case_op_string + strlen (org_case_op_string);
+ 
+       --base_string;
+       if (is_space_char (*base_string))
+ 	--base_string;
+ 
+       /* If we only have a displacement, set-up for it to be parsed later.  */
+       displacement_string_start = org_case_op_string;
+       displacement_string_end = base_string + 1;
+       if (displacement_string_start != displacement_string_end)
+ 	{
+ 	  if (!maxq20_displacement (displacement_string_start,
+ 				    displacement_string_end))
+ 	    return 0;
+ 	  /* A displacement operand found */
+ 	  i.types[this_operand] = DISP;	/* Set the type */
+ 	}
+     }
+   return 1;
+ }
+ 
+ static int
+ match_template ()
+ {
+   /* Points to template once we've found it.  */
+   const MAXQ20_OPCODE_INFO *t;
+   char inv_oper;
+   inv_oper = 0;
+   for (t = current_templates->start; t < current_templates->end; t++)
+     {
+       /* Must have right number of operands.  */
+       if (i.operands != t->op_number)
+ 	continue;
+       else if (!t->op_number)
+ 	{
+ 	  break;
+ 	}
+       switch (i.operands)
+ 	{
+ 	case 2:
+ 	  if (!match_operands (i.types[1], i.maxq20_op[1].flag, t->arg[1], 1))
+ 	    {
+ 	      inv_oper = 1;
+ 	      continue;
+ 	    }
+ 	case 1:
+ 	  if (!match_operands (i.types[0], i.maxq20_op[0].flag, t->arg[0], 0))
+ 	    {
+ 	      inv_oper = 2;
+ 	      continue;
+ 	    }
+ 	}
+       break;
+     }				/* end of for */
+ 
+   if (t == current_templates->end)
+     {
+       /* We found no match.  */
+       as_bad (_("operand %d is invalid for `%s'"),
+ 	      inv_oper, current_templates->start->name);
+       return 0;
+     }
+ 
+   /* Copy the template we have found */
+   i.op = *t;
+   return 1;
+ }
+ 
+ /* This function filters out the various combinations of operands which are
+    not allowed for a particular instruction */
+ static int
+ match_filters ()
+ {
+   /* Now we have at our disposal the instruction i. We will be using the
+      following fields i.op.name : This is the mnemonic name. i.types[2] :
+      These are the types of the operands (REG/IMM/DISP/MEM/BIT/FLAG/IMMBIT)
+      i.maxq20_op[2] : This contains the specific info of the operands */
+ 
+   /* Our first filter : NO ALU OPERATIONS CAN HAVE THE ACTIVE ACCUMULATOR AS
+      SOURCE */
+   if (!strcmp (i.op.name, "AND") || !strcmp (i.op.name, "OR")
+       || !strcmp (i.op.name, "XOR") || !strcmp (i.op.name, "ADD")
+       || !strcmp (i.op.name, "ADDC") || !strcmp (i.op.name, "SUB")
+       || !strcmp (i.op.name, "SUBB"))
+     {
+       if (i.types[0] == REG)
+ 	{
+ 	  if (i.maxq20_op[0].reg->Mod_name == 0xa)
+ 	    {
+ 	      as_bad (_
+ 		      ("The Accumulator cannot be used as a source in ALU instructions\n"));
+ 	      return 0;
+ 	    }
+ 	}
+     }
+ 
+   if (!strcmp (i.op.name, "MOVE") && (i.types[0] == MEM || i.types[1] == MEM)
+       && i.operands == 2)
+     {
+       mem_access_syntax *mem_op = NULL;
+ 
+       if (i.types[0] == MEM)
+ 	{
+ 	  mem_op =
+ 	    (mem_access_syntax *) hash_find (mem_syntax_hash,
+ 					     i.maxq20_op[0].mem->name);
+ 	  if ((mem_op->type == SRC) && mem_op)
+ 	    {
+ 	      as_bad (_("'%s' operand cant be used as destination in %s"),
+ 		      mem_op->name, i.op.name);
+ 	      return 0;
+ 	    }
+ 	  else if ((mem_op->invalid_op != NULL) && (i.types[1] == MEM)
+ 		   && mem_op)
+ 	    {
+ 	      int k = 0;
+ 	      for (k = 0; k < 5 || !mem_op->invalid_op[k]; k++)
+ 		{
+ 		  if (mem_op->invalid_op[k] != NULL)
+ 		    if (!strcmp
+ 			(mem_op->invalid_op[k], i.maxq20_op[1].mem->name))
+ 		      {
+ 			as_bad (_
+ 				("Invalid Instruction '%s' operand cant be used with %s"),
+ 				mem_op->name, i.maxq20_op[1].mem->name);
+ 			return 0;
+ 		      }
+ 		}
+ 	    }
+ 	}
+       if (i.types[1] == MEM)
+ 	{
+ 	  mem_op = NULL;
+ 	  mem_op =
+ 	    (mem_access_syntax *) hash_find (mem_syntax_hash,
+ 					     i.maxq20_op[1].mem->name);
+ 	  if (mem_op->type == DST && mem_op)
+ 	    {
+ 	      as_bad (_("'%s' operand cant be used as source in %s"),
+ 		      mem_op->name, i.op.name);
+ 	      return 0;
+ 	    }
+ 	  else if (mem_op->invalid_op != NULL && i.types[0] == MEM && mem_op)
+ 	    {
+ 	      int k = 0;
+ 	      for (k = 0; k < 5 || !mem_op->invalid_op[k]; k++)
+ 		{
+ 		  if (mem_op->invalid_op[k] != NULL)
+ 		    if (!strcmp
+ 			(mem_op->invalid_op[k], i.maxq20_op[0].mem->name))
+ 		      {
+ 			as_bad (_
+ 				("Invalid Instruction '%s' operand cant be used with %s"),
+ 				mem_op->name, i.maxq20_op[0].mem->name);
+ 			return 0;
+ 		      }
+ 		}
+ 	    }
+ 	  else if (i.types[0] == REG
+ 		   && !strcmp (i.maxq20_op[0].reg->reg_name, "OFFS")
+ 		   && mem_op)
+ 	    {
+ 	      if (!strcmp (mem_op->name, "@BP[OFFS--]")
+ 		  || !strcmp (mem_op->name, "@BP[OFFS++]"))
+ 		{
+ 		  as_bad (_
+ 			  ("Invalid Instruction '%s' operand cant be used with %s"),
+ 			  mem_op->name, i.maxq20_op[0].mem->name);
+ 		  return 0;
+ 
+ 		}
+ 	    }
+ 	}
+     }
+ 
+   /* Added for SRC and DST in one operand instructioni i.e OR @--DP[1] added
+      on 10-March-2004 */
+   if ((i.types[0] == MEM) && (i.operands == 1)
+       && !(!strcmp (i.op.name, "POP") || !strcmp (i.op.name, "POPI")))
+     {
+       mem_access_syntax *mem_op = NULL;
+ 
+       if (i.types[0] == MEM)
+ 	{
+ 	  mem_op =
+ 	    (mem_access_syntax *) hash_find (mem_syntax_hash,
+ 					     i.maxq20_op[0].mem->name);
+ 	  if (mem_op->type == DST && mem_op)
+ 	    {
+ 	      as_bad (_("'%s' operand cant be used as source in %s"),
+ 		      mem_op->name, i.op.name);
+ 	      return 0;
+ 	    }
+ 	}
+     }
+ 
+   if (i.operands == 2 && i.types[0] == IMM)
+     {
+       as_bad (_("'%s' instruction cant have first operand as Immediate vale"),
+ 	      i.op.name);
+       return 0;
+     }
+ 
+   /* Our second filter : SP or @SP-- cannot be used with PUSH or POP */
+   if (!strcmp (i.op.name, "PUSH") || !strcmp (i.op.name, "POP")
+       || !strcmp (i.op.name, "POPI"))
+     {
+       if (i.types[0] == REG)
+ 	{
+ 	  if (!strcmp (i.maxq20_op[0].reg->reg_name, "SP"))
+ 	    {
+ 	      as_bad (_("SP cannot be used with %s\n"), i.op.name);
+ 	      return 0;
+ 	    }
+ 	}
+       else if (i.types[0] == MEM
+ 	       && !strcmp (i.maxq20_op[0].mem->name, "@SP--"))
+ 	{
+ 	  as_bad (_("@SP-- cannot be used with PUSH\n"));
+ 	  return 0;
+ 	}
+ 
+     }
+ 
+   /* This filter checks that two memory references using DP's cannot be used
+      together in an instruction */
+   if (!strcmp (i.op.name, "MOVE") && i.mem_operands == 2)
+     {
+       if (strlen (i.maxq20_op[0].mem->name) != 6 ||
+ 	  strcmp (i.maxq20_op[0].mem->name, i.maxq20_op[1].mem->name))
+ 	{
+ 	  if (!strncmp (i.maxq20_op[0].mem->name, "@DP", 3)
+ 	      && !strncmp (i.maxq20_op[1].mem->name, "@DP", 3))
+ 	    {
+ 	      as_bad (_
+ 		      ("Operands either contradictory or use the data bus in read/write state together"));
+ 	      return 0;
+ 	    }
+ 
+ 	  if (!strncmp (i.maxq20_op[0].mem->name, "@SP", 3)
+ 	      && !strncmp (i.maxq20_op[1].mem->name, "@SP", 3))
+ 	    {
+ 	      as_bad (_
+ 		      ("Operands either contradictory or use the data bus in read/write state together"));
+ 	      return 0;
+ 	    }
+ 
+ 	}
+       if ((i.maxq20_op[1].mem != NULL)
+ 	  && !strncmp (i.maxq20_op[1].mem->name, "NUL", 3))
+ 	{
+ 	  as_bad (_("MOVE Cant Use NUL as SRC"));
+ 	  return 0;
+ 
+ 	}
+     }
+ 
+   /* This filter checks that contradictory movement between DP register and
+      Memory access using DP followed by increment or decrement */
+ 
+   if (!strcmp (i.op.name, "MOVE") && i.mem_operands == 1
+       && i.reg_operands == 1)
+     {
+       int memnum, regnum;
+       memnum = (i.types[0] == MEM) ? 0 : 1;
+       regnum = (memnum == 0) ? 1 : 0;
+       if (!strncmp (i.maxq20_op[regnum].reg->reg_name, "DP", 2) &&
+ 	  !strncmp ((i.maxq20_op[memnum].mem->name) + 1,
+ 		    i.maxq20_op[regnum].reg->reg_name, 5)
+ 	  && strcmp ((i.maxq20_op[memnum].mem->name) + 1,
+ 		     i.maxq20_op[regnum].reg->reg_name))
+ 	{
+ 	  as_bad (_
+ 		  ("Contradictory movement between DP register and memory access using DP"));
+ 	  return 0;
+ 	}
+       else if (!strcmp (i.maxq20_op[regnum].reg->reg_name, "SP") &&
+ 	       !strncmp ((i.maxq20_op[memnum].mem->name) + 1,
+ 			 i.maxq20_op[regnum].reg->reg_name, 2))
+ 	{
+ 	  as_bad (_
+ 		  ("SP and @SP-- cannot be used together in a move instruction"));
+ 	  return 0;
+ 	}
+     }
+ 
+   /* This filter restricts the instructions containing source and destination 
+      bits to only CTRL module of the serial registers. Peripheral registers
+      yet to be defined */
+ 
+   if (i.bit_operands == 1 && i.operands == 2)
+     {
+       int bitnum = (i.types[0] == BIT) ? 0 : 1;
+       if (strcmp (i.maxq20_op[bitnum].r_bit->reg->reg_name, "ACC"))	/* Nov 
+ 									   05 
+ 									   2003 
+ 									   changed 
+ 									   from 
+ 									   Acc 
+ 									 */
+ 	{
+ 	  if (i.maxq20_op[bitnum].r_bit->reg->Mod_name >= 0x7 &&
+ 	      i.maxq20_op[bitnum].r_bit->reg->Mod_name != CTRL)
+ 	    {
+ 	      as_bad (_
+ 		      ("Only Module 8 system registers allowed in this operation"));
+ 	      return 0;
+ 	    }
+ 	}
+     }
+ 
+   /* This filter is for checking the register bits */
+   if (i.bit_operands == 1 || i.operands == 2)
+     {
+       int bitnum = 0, size = 0;
+ 
+       bitnum = (i.types[0] == BIT) ? 0 : 1;
+       if (i.bit_operands == 1)
+ 	{
+ 	  switch (i.maxq20_op[bitnum].r_bit->reg->rtype)
+ 	    {
+ 
+ 	    case Reg_8W:
+ 	      size = 7;		/* 8 bit register, both read and write */
+ 	      break;
+ 	    case Reg_16W:
+ 	      size = 15;
+ 	      break;
+ 	    case Reg_8R:
+ 	      size = 7;
+ 	      if (bitnum == 0)
+ 		{
+ 		  as_fatal (_("Read only Register used as destination"));
+ 		  return 0;
+ 		}
+ 	      break;
+ 
+ 	    case Reg_16R:
+ 	      size = 15;
+ 	      if (bitnum == 0)
+ 		{
+ 		  as_fatal (_("Read only Register used as destination"));
+ 		  return 0;
+ 		}
+ 	      break;
+ 
+ 	    }
+ 	  if (size < (i.maxq20_op[bitnum].r_bit)->bit)
+ 	    {
+ 	      as_bad (_("Bit No '%d'exceeds register size in this operation"),
+ 		      (i.maxq20_op[bitnum].r_bit)->bit);
+ 	      return 0;
+ 	    }
+ 	}
+ 
+       if (i.bit_operands == 2)
+ 	{
+ 	  switch ((i.maxq20_op[0].r_bit)->reg->rtype)
+ 	    {
+ 
+ 	    case Reg_8W:
+ 	      size = 7;		/* 8 bit register, both read and write */
+ 	      break;
+ 	    case Reg_16W:
+ 	      size = 15;
+ 	      break;
+ 	    case Reg_8R:
+ 	    case Reg_16R:
+ 	      as_fatal (_("Read only Register used as destination"));
+ 	      return 0;
+ 	    }
+ 
+ 	  if (size < (i.maxq20_op[0].r_bit)->bit)
+ 	    {
+ 	      as_bad (_
+ 		      ("Bit No '%d' exceeds register size in this operation"),
+ 		      (i.maxq20_op[0].r_bit)->bit);
+ 	      return 0;
+ 	    }
+ 
+ 	  size = 0;
+ 	  switch ((i.maxq20_op[1].r_bit)->reg->rtype)
+ 	    {
+ 
+ 	    case Reg_8R:
+ 	    case Reg_8W:
+ 	      size = 7;		/* 8 bit register, both read and write */
+ 	      break;
+ 	    case Reg_16R:
+ 	    case Reg_16W:
+ 	      size = 15;
+ 	      break;
+ 	    }
+ 	  if (size < (i.maxq20_op[1].r_bit)->bit)
+ 	    {
+ 	      as_bad (_
+ 		      ("Bit No '%d' exceeds register size in this operation"),
+ 		      (i.maxq20_op[1].r_bit)->bit);
+ 	      return 0;
+ 	    }
+ 
+ 	}
+ 
+     }
+ 
+   /* No branch operations should occur into the data memory. Hence any memory 
+      references have to be filtered out when used with instructions like
+      jump, djnz[] and call */
+ 
+   if (!strcmp (i.op.name, "JUMP") || !strcmp (i.op.name, "CALL")
+       || !strncmp (i.op.name, "DJNZ", 4))
+     {
+       if (i.mem_operands)
+ 	{
+ 	  as_warn (_
+ 		   ("Memory References cannot be used with branching operations\n"));
+ 	  /* This patch has to be used in case we need to generate an error:
+ 
+ 	     as_bad(_("Memory References cannot be used with branching
+ 	     operations\n")); return 0; */
+ 	}
+     }
+ 
+   if (!strcmp (i.op.name, "DJNZ"))
+     {
+       if (!
+ 	  (strcmp (i.maxq20_op[0].reg->reg_name, "LC[0]")
+ 	   || strcmp (i.maxq20_op[0].reg->reg_name, "LC[1]")))
+ 	{
+ 	  as_bad (_("DJNZ uses only LC[n] register \n"));
+ 	  return 0;
+ 	}
+     }
+ 
+   /* No destination register used should be read only!!!! */
+   if ((i.operands == 2 && i.types[0] == REG) || !strcmp (i.op.name, "POP")
+       || !strcmp (i.op.name, "POPI"))
+     {				/* The destination is a register */
+       int regnum = 0;
+       if (!strcmp (i.op.name, "POP") || !strcmp (i.op.name, "POPI"))
+ 	{
+ 	  regnum = 0;
+ #if Sudeep
+ 	  regnum = 1;
+ #elseif
+ 	  regnum = 0;
+ #endif
+ 	  if (i.types[regnum] == MEM)
+ 	    {
+ 	      mem_access_syntax *mem_op = NULL;
+ 
+ 	      mem_op =
+ 		(mem_access_syntax *) hash_find (mem_syntax_hash,
+ 						 i.maxq20_op[regnum].mem->
+ 						 name);
+ 	      if (mem_op->type == SRC && mem_op)
+ 		{
+ 		  as_bad (_
+ 			  ("'%s' operand cant be used as destination  in %s"),
+ 			  mem_op->name, i.op.name);
+ 		  return 0;
+ 		}
+ 	    }
+ 	}
+ 
+       if (i.maxq20_op[regnum].reg->rtype == Reg_8R
+ 	  || i.maxq20_op[regnum].reg->rtype == Reg_16R)
+ 	{
+ 	  as_bad (_("Read only register used for writing purposes '%s'"),
+ 		  i.maxq20_op[regnum].reg->reg_name);
+ 	  return 0;
+ 	}
+ 
+     }
+ 
+   /* While moving the address of a data in the data section, the destination
+      should be either data pointers only */
+   if ((i.data_operands) && (i.operands == 2))
+     {
+       if ((i.types[0] != REG) && (i.types[0] != MEM))
+ 	{
+ 	  as_bad (_("Invalid destination for this kind of source."));
+ 	  return 0;
+ 	}
+ #if 0
+       if (i.types[0] == REG
+ 	  && strncmp (i.maxq20_op[0].reg->reg_name, "DP", 2))
+ #endif
+ 	if (i.types[0] == REG && i.maxq20_op[0].reg->rtype == Reg_8W)
+ 	  {
+ 	    as_bad (_
+ 		    ("Invalid register as destination for this kind of source.Only data pointers can be used."));
+ 	    return 0;
+ 	  }
+     }
+   return 1;
+ }
+ 
+ /* REG_STRING starts *before* REGISTER_PREFIX.  */
+ static reg_entry *
+ parse_register (reg_string, end_op)
+      char *reg_string;
+      char **end_op;
+ {
+   char *s = reg_string;
+   char *p = NULL;
+   char reg_name_given[MAX_REG_NAME_SIZE + 1];
+   reg_entry *r = NULL;
+ 
+   r = NULL;
+   p = NULL;
+ 
+   /* Skip possible REGISTER_PREFIX and possible whitespace.  */
+ 
+   if (is_space_char (*s))
+     ++s;
+ 
+   p = reg_name_given;
+   while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
+     {
+       if (p >= reg_name_given + MAX_REG_NAME_SIZE)
+ 	return (reg_entry *) NULL;
+       s++;
+     }
+ 
+   *end_op = s;
+ 
+   r = (reg_entry *) hash_find (reg_hash, reg_name_given);
+ 
+ #if CHANGE_PFX
+   if (this_operand == 0 && r != NULL)
+     {
+       if (r->Mod_index > 7)
+ 	i.prefix = 2;
+       else
+ 	i.prefix = 0;
+     }
+ #endif
+   return r;
+ 
+ }
+ 
+ static reg_bit *
+ parse_register_bit (reg_string, end_op)
+      char *reg_string;
+      char **end_op;
+ {
+   const char *s = reg_string;
+   short k = 0;
+   char diff = 0;
+   reg_bit *rb = NULL;
+   reg_entry *r = NULL;
+   bit_name *b = NULL;
+   char temp_bitname[MAX_REG_NAME_SIZE + 2];
+   char temp[MAX_REG_NAME_SIZE + 1];
+ 
+   memset (&temp, '\0', (MAX_REG_NAME_SIZE + 1));
+   memset (&temp_bitname, '\0', (MAX_REG_NAME_SIZE + 2));
+ 
+   diff = 0;
+   r = NULL;
+   rb = NULL;
+   rb = (reg_bit *) xmalloc (sizeof (reg_bit));
+   rb->reg = (reg_entry *) xmalloc (sizeof (reg_entry));
+   k = 0;
+ 
+   /* For supporting bit names */
+ 
+   b = (bit_name *) hash_find (bit_hash, reg_string);
+ 
+   if (b != NULL)
+     {
+       *end_op = reg_string + strlen (reg_string);
+       strcpy (temp_bitname, b->reg_bit);
+       s = temp_bitname;
+     }
+   if (strchr (s, '.'))		/* If there is "." in the string */
+     {
+ 
+       while (*s != '.')
+ 	{
+ 	  if (*s == '\0')
+ 	    return NULL;
+ 	  temp[k] = *s++;
+ 
+ 	  k++;
+ 	}
+       temp[k] = '\0';
+     }
+ 
+   if ((r = parse_register (temp, end_op)) == NULL)
+     return NULL;
+ 
+   rb->reg = r;
+   s++;				// to skip the "."
+   if (isdigit ((char) *s))
+     rb->bit = atoi (s);
+   else if (isalpha ((char) *s))
+     {
+       rb->bit = (char) *s - 'a';
+       rb->bit += 10;
+       if (rb->bit > 15)
+ 	{
+ 	  as_bad (_("Invalid bit number : '%c'"), (char) *s);
+ 	  return NULL;
+ 	}
+     }
+ 
+   if (b != NULL)
+     diff = strlen (temp_bitname) - strlen (temp) - 1;
+   else
+     diff = strlen (reg_string) - strlen (temp) - 1;
+ 
+   if (*(s + diff) != '\0')
+     {
+ 
+       as_bad (_("Illegal character after operand '%s'"), reg_string);
+       return NULL;
+     }
+   return rb;
+ }
+ 
+ static mem_access *
+ maxq20_mem_access (mem_string, end_op)
+      char *mem_string;
+      char **end_op;
+ {
+   char *s = mem_string;
+   char *p;
+   char mem_name_given[MAX_MEM_NAME_SIZE + 1];
+   mem_access *m;
+ 
+   m = NULL;
+ 
+   /* Skip possible whitespace.  */
+   if (is_space_char (*s))
+     ++s;
+ 
+   p = mem_name_given;
+   while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
+     {
+       if (p >= mem_name_given + MAX_MEM_NAME_SIZE)
+ 	return (mem_access *) NULL;
+       s++;
+     }
+ 
+   *end_op = s;
+ 
+   m = (mem_access *) hash_find (mem_hash, mem_name_given);
+ 
+   return m;
+ 
+ }
+ 
+ static int
+ maxq20_immediate (imm_start)
+      char *imm_start;
+ {
+   int val = 0, val_pfx = 0;
+   char sign_val = 0;
+   int k = 0, j;
+   int temp[4] = { 0 };
+ 
+   imm_start++;
+ 
+   if (imm_start[1] == '\0' && (imm_start[0] == '0' || imm_start[0] == '1')
+       && (this_operand == 1 && ((i.types[0] == BIT || i.types[0] == FLAG))))
+     {
+       val = imm_start[0] - '0';
+       i.imm_bit_operands++;
+       i.types[this_operand] = IMMBIT;
+       i.maxq20_op[this_operand].imms = (char) val;
+ #if CHANGE_PFX
+       if (i.prefix == 2)
+ 	{
+ 	  pfx_for_imm_val (0);
+ 	}
+ #endif
+       return 1;
+     }
+ 
+   /* Check For Sign Charcater */
+   sign_val = 0;
+ 
+   do
+     {
+       if (imm_start[k] == '-' && k == 0)
+ 	sign_val = -1;
+ 
+       else if (imm_start[k] == '+' && k == 0)
+ 	sign_val = 1;
+ 
+       else if (isdigit (imm_start[k]))
+ 	{
+ 	  temp[k] = imm_start[k] - '0';
+ 	}
+       else if (isalpha (imm_start[k])
+ 	       && (imm_start[k] = tolower (imm_start[k])) < 'g')
+ 	{
+ 	  temp[k] = 10 + (int) (imm_start[k] - 'a');
+ 	}
+       else if (imm_start[k] == 'h')
+ 	break;
+       else if (imm_start[k] == '\0')
+ 	{
+ 	  imm_start[k] = 'd';
+ 	  break;
+ 	}
+ 
+       else
+ 	{
+ 	  as_bad (_("Invalid Character in immediate Value : %c"),
+ 		  imm_start[k]);
+ 	  return 0;
+ 	}
+       k++;
+     }
+   while (imm_start[k] != '\n');
+ 
+   switch (imm_start[k])
+     {
+     case 'h':
+       for (j = (sign_val ? 1 : 0); j < k; j++)
+ 	{
+ 	  val += temp[j] * pwr (16, k - j - 1);
+ 	}
+       break;
+     case 'd':
+       for (j = (sign_val ? 1 : 0); j < k; j++)
+ 	{
+ 	  if (temp[j] > 9)
+ 	    {
+ 	      as_bad (_("Invalid Character in immediate value : %c"),
+ 		      imm_start[j]);
+ 	      return 0;
+ 	    }
+ 	  val += temp[j] * pwr (10, k - j - 1);
+ 	}
+     }
+ 
+   if (!sign_val)
+     sign_val = 1;
+ 
+   /* Now over here the value val stores the 8 bit/16 bit value. We will put a 
+      check if we are moving a 16 bit immediate value into an 8 bit register. 
+      In that case we will generate a warning and move only the lower 8 bits */
+   if (val > 65535)
+     {
+       as_bad (_("Immediate value greater than 16 bits"));
+       return 0;
+     }
+ 
+   val = val * sign_val;
+ 
+   /* If it is a stack pointer and the value is greater than the maximum
+      permissible size */
+   if (this_operand == 1)
+     {
+       if ((val * sign_val) > MAX_STACK && i.types[0] == REG
+ 	  && !strcmp (i.maxq20_op[0].reg->reg_name, "SP"))
+ 	{
+ 	  as_warn (_
+ 		   ("Attempt to move a value in the stack pointer greater than the size of the stack"));
+ 	  val = val & MAX_STACK;
+ 	}
+ 
+       /* check the range for 8 bit registers */
+       else if (((val * sign_val) > 0xFF) && (i.types[0] == REG)
+ 	       && (i.maxq20_op[0].reg->rtype == Reg_8W))
+ 	{
+ 	  as_warn (_
+ 		   ("Attempt to move 16 bit value into an 8 bit register.Truncating..\n"));
+ 	  val = val & 0xfe;
+ 	}
+ 
+       else if (((sign_val == -1) || (val > 0xFF)) && (i.types[0] == REG)
+ 	       && (i.maxq20_op[0].reg->rtype == Reg_8W))
+ 	{
+ 	  val_pfx = val >> 8;
+ 	  val = ((val) & 0x00ff);
+ 	  SET_PFX_ARG (val_pfx);
+ 	  i.maxq20_op[this_operand].imms = (char) val;	// Add PFX for -ve
+ 							// val
+ 	}
+ 
+       else if ((val <= 0xff) && (i.types[0] == REG)
+ 	       && (i.maxq20_op[0].reg->rtype == Reg_8W))
+ 	{
+ 	  i.maxq20_op[this_operand].imms = (char) val;	// No PFX required
+ 	}
+ 
+       /* check for 16 bit registers */
+       else if (((sign_val == -1) || val > 0xFE) && i.types[0] == REG
+ 	       && i.maxq20_op[0].reg->rtype == Reg_16W)
+ 	{
+ 	  /* Add PFX for any negative value -> 16bit register */
+ 	  val_pfx = val >> 8;
+ 	  val = ((val) & 0x00ff);
+ 	  SET_PFX_ARG (val_pfx);
+ 	  i.maxq20_op[this_operand].imms = (char) val;
+ 	}
+ 
+       else if (val < 0xFF && i.types[0] == REG
+ 	       && i.maxq20_op[0].reg->rtype == Reg_16W)
+ 	{
+ 	  i.maxq20_op[this_operand].imms = (char) val;
+ 	}
+ 
+       /* all the immediate memory access - no PFX */
+       else if (i.types[0] == MEM)
+ 	{
+ 	  if ((sign_val == -1) || val > 0xFE)
+ 	    {
+ 	      /* add a PFX */
+ 	      val_pfx = val >> 8;
+ 	      val = ((val) & 0x00ff);
+ 	      SET_PFX_ARG (val_pfx);
+ 	      i.maxq20_op[this_operand].imms = (char) val;
+ 
+ 	    }
+ 
+ 	  else
+ 	    i.maxq20_op[this_operand].imms = (char) val;
+ 	}
+ 
+       /* special handling for immediate jumps like jump nz, #03h etc */
+       else if (val < 0xFF && i.types[0] == FLAG)
+ 	{
+ 	  i.maxq20_op[this_operand].imms = (char) val;
+ 	}
+ 
+       else if ((((sign_val == -1) || val > 0xFE)) && i.types[0] == FLAG)
+ 	{			/* add a PFX */
+ 	  val_pfx = val >> 8;
+ 	  val = ((val) & 0x00ff);
+ 	  SET_PFX_ARG (val_pfx);
+ 	  i.maxq20_op[this_operand].imms = (char) val;
+ 
+ 	}
+ 
+       else
+ 	{
+ 	  as_bad (_("Invalid immediate move operation"));
+ 	  return 0;
+ 	}
+ 
+     }
+ 
+   else				/* all the instruction with operation on ACC: 
+ 				   like ADD src, etc. */
+     {
+       if ((sign_val == -1) || val > 0xFE)
+ 	{
+ 	  /* add a PFX */
+ 	  val_pfx = val >> 8;
+ 	  val = ((val) & 0x00ff);
+ 	  SET_PFX_ARG (val_pfx);
+ 	  i.maxq20_op[this_operand].imms = (char) val;
+ 
+ 	}
+ 
+       else
+ 	i.maxq20_op[this_operand].imms = (char) val;
+ 
+     }
+ 
+   i.imm_operands++;
+   return 1;
+ }
+ 
+ void
+ pfx_for_imm_val (int arg)
+ {
+   if (i.prefix == -1)
+     return;			// No PFX needed
+ 
+   if (i.prefix == 0 && arg == 0 && PFX_INSN[1] == 0 && !(i.data_operands))
+     return;
+ 
+   if (!(i.prefix < 0) && !(i.prefix > 7))
+     PFX_INSN[0] = (i.prefix << 4) | PFX0;
+ 
+   if (!PFX_INSN[1])
+     PFX_INSN[1] = arg;
+ 
+ }
+ 
+ static int
+ match_operands (int type, MAX_ARG_TYPE flag_type, MAX_ARG_TYPE arg_type,
+ 		int op_num)
+ {
+   switch (type)
+     {
+     case REG:
+       if ((arg_type & A_REG) == A_REG)
+ 	return 1;
+       break;
+     case IMM:
+       if ((arg_type & A_IMM) == A_IMM)
+ 	return 1;
+       break;
+     case IMMBIT:
+       if ((arg_type & A_BIT_0) == A_BIT_0 && (i.maxq20_op[op_num].imms == 0))
+ 	return 1;
+       else if ((arg_type & A_BIT_1) == A_BIT_1
+ 	       && (i.maxq20_op[op_num].imms == 1))
+ 	return 1;
+       break;
+     case MEM:
+       if ((arg_type & A_MEM) == A_MEM)
+ 	return 1;
+       break;
+ 
+     case FLAG:
+       if ((arg_type & flag_type) == flag_type)
+ 	return 1;
+ 
+       break;
+ #if 0
+     case FLAG:
+       if ((arg_type & FLAG_C) == FLAG_C)
+ 	return 1;
+       else if ((arg_type & FLAG_NC) == FLAG_NC)
+ 	return 1;
+       else if ((arg_type & FLAG_Z) == FLAG_Z)
+ 	return 1;
+       else if ((arg_type & FLAG_NZ) == FLAG_NZ)
+ 	return 1;
+       else if ((arg_type & FLAG_S) == FLAG_S)
+ 	return 1;
+       else if ((arg_type & FLAG_E) == FLAG_E)
+ 	return 1;
+       else if ((arg_type & FLAG_NE) == FLAG_NE)
+ 	return 1;
+       break;
+ #endif
+ 
+     case BIT:
+       if ((arg_type & ACC_BIT) == ACC_BIT && !strcmp (i.maxq20_op[op_num].r_bit->reg->reg_name, "ACC"))	/* chnged 
+ 													   from 
+ 													   Acc 
+ 													   Nov 
+ 													   5 
+ 													   2003 
+ 													 */
+ 	return 1;
+       else if ((arg_type & SRC_BIT) == SRC_BIT && (op_num == 1))
+ 	return 1;
+       else if ((op_num == 0) && (arg_type & DST_BIT) == DST_BIT)
+ 	return 1;
+       break;
+     case DISP:
+       if ((arg_type & A_DISP) == A_DISP)
+ 	return 1;
+     case DATA:
+       if ((arg_type & A_DATA) == A_DATA)
+ 	return 1;
+     case BIT_BUCKET:
+       if ((arg_type & A_BIT_BUCKET) == A_BIT_BUCKET)
+ 	return 1;
+     }
+   return 0;
+ 
+ }				// THis function has not yet been completely
+ 				// defined
+ 
+ static int
+ decode_insn ()
+ {
+   /* Check for the format Bit if defined */
+   if (i.op.format == 0 || i.op.format == 1)
+     i.instr[0] = i.op.format << 7;
+   else				/* Format bit not defined. We will have to be 
+ 				   find it out ourselves */
+     {
+       if (i.imm_operands == 1 || i.data_operands == 1 || i.disp_operands == 1)
+ 	i.op.format = 0;
+       else
+ 	i.op.format = 1;
+       i.instr[0] = i.op.format << 7;
+     }
+ 
+   /* Now for the destination register. */
+ 
+   /* If destination register is already defined . The conditions are the
+      following: (1) The second entry in the destination array should be 0 (2) 
+      If there are two operands then the first entry should not be a register,
+      memory or a register bit (3) If there are less than two operands and the
+      it is not a pop operation (4) The second argument is the carry
+      flag(applicable to move Acc.<b>,C.  */
+ 
+   if (i.op.dst[1] == 0
+       &&
+       ((i.types[0] != REG && i.types[0] != MEM && i.types[0] != BIT
+ 	&& i.operands == 2) || (i.operands < 2 && strcmp (i.op.name, "POP")
+ 				&& strcmp (i.op.name, "POPI"))
+        || (i.op.arg[1] == FLAG_C)))
+     {
+       i.op.dst[0] &= 0x7f;
+       i.instr[0] |= i.op.dst[0];
+     }
+   else if (i.op.dst[1] == 0 && !strcmp (i.op.name, "DJNZ")
+ 	   &&
+ 	   (((i.types[0] == REG)
+ 	     && (!strcmp (i.maxq20_op[0].reg->reg_name, "LC[0]")
+ 		 || !strcmp (i.maxq20_op[0].reg->reg_name, "LC[1]")))))
+     {
+       i.op.dst[0] &= 0x7f;
+       if (!strcmp (i.maxq20_op[0].reg->reg_name, "LC[0]"))
+ 	i.instr[0] |= 0x4D;
+ 
+       if (!strcmp (i.maxq20_op[0].reg->reg_name, "LC[1]"))
+ 	i.instr[0] |= 0x5D;
+ 
+     }
+ 
+   else				/* Target register will have to be specified */
+     {
+ 
+       if (i.types[0] == REG
+ 	  && (i.op.dst[0] == REG || i.op.dst[0] == (REG | MEM)))
+ 	{
+ 	  unsigned char temp = (i.maxq20_op[0].reg)->opcode;
+ 	  temp &= 0x7f;
+ 	  i.instr[0] |= temp;
+ 	}
+ 
+       else if (i.types[0] == MEM && (i.op.dst[0] == (REG | MEM)))
+ 	{
+ 	  unsigned char temp = (i.maxq20_op[0].mem)->opcode;
+ 	  temp &= 0x7f;
+ 	  i.instr[0] |= temp;
+ 	}
+       else if (i.types[0] == BIT && (i.op.dst[0] == REG))
+ 	{
+ 	  unsigned char temp = (i.maxq20_op[0].r_bit)->reg->opcode;
+ 	  temp &= 0x7f;
+ 	  i.instr[0] |= temp;
+ 	}
+       else if (i.types[1] == BIT && (i.op.dst[0] == BIT))
+ 	{
+ 	  unsigned char temp = (i.maxq20_op[1].r_bit)->bit;
+ 	  temp = temp << 4;
+ 	  temp |= i.op.dst[1];
+ 	  temp &= 0x7f;
+ 	  i.instr[0] |= temp;
+ 	}
+ 
+       else
+ 	{
+ 	  as_bad (_("Invalid Instruction"));
+ 	  return 0;
+ 	}
+     }
+ 
+   /* Now for the source register */
+ 
+   /* If Source register is already known. The following conditions are
+      checked: (1) There are no operands (2) If there is only one operand and
+      it is a flag (3) If the operation is MOVE C,#0/#1 (4) If it is a POP
+      operation */
+ 
+   if (i.operands == 0 || (i.operands == 1 && i.types[0] == FLAG)
+       || (i.types[0] == FLAG && i.types[1] == IMMBIT)
+       || !strcmp (i.op.name, "POP") || !strcmp (i.op.name, "POPI"))
+     {
+       char temp = i.op.src[0];
+       i.instr[1] = temp;
+     }
+   else if (i.imm_operands == 1 && ((i.op.src[0] & IMM) == IMM))	/* Its an
+ 								   immediate
+ 								   operand */
+     {
+       i.instr[1] = i.maxq20_op[this_operand].imms;
+     }
+   else if (i.types[this_operand] == REG && ((i.op.src[0] & REG) == REG))	/* Its 
+ 										   a 
+ 										   register! 
+ 										 */
+     {
+       i.instr[1] = (char) ((i.maxq20_op[this_operand].reg)->opcode);
+     }
+   else if (i.types[this_operand] == BIT && ((i.op.src[0] & REG) == REG))
+     {
+       i.instr[1] = (char) (i.maxq20_op[this_operand].r_bit->reg->opcode);
+     }
+   else if (i.types[this_operand] == MEM && ((i.op.src[0] & MEM) == MEM))	/* Its 
+ 										   a 
+ 										   memory 
+ 										   reference 
+ 										 */
+     {
+       i.instr[1] = (char) ((i.maxq20_op[this_operand].mem)->opcode);
+     }
+   else if (i.types[this_operand] == DATA && ((i.op.src[0] & DATA) == DATA))	/* It 
+ 										   is 
+ 										   a 
+ 										   data 
+ 										   reference 
+ 										 */
+     {
+       /* This will copy only the lower order bytes into the instruction. The
+          higher order bytes have already been copied into the prefix register 
+        */
+       i.instr[1] = 0;
+ 
+     }
+   /* Decoding the source in the case when the second array entry is not 0.
+      This means that the source register has been divided into two nibbles */
+ 
+   else if (i.op.src[1] != 0)
+     {
+       /* If the first operand is a accumulator bit then the first 4 bits will 
+          be filled with the bit number */
+       if (i.types[0] == BIT && ((i.op.src[0] & BIT) == BIT))
+ 	{
+ 	  unsigned char temp = (i.maxq20_op[0].r_bit)->bit;
+ 	  temp = temp << 4;
+ 	  temp |= i.op.src[1];
+ 	  i.instr[1] = temp;
+ 	}
+       /* In case of MOVE dst.<b>,#1 The first nibble in the source register
+          has to start with a zero. This is called a ZEROBIT */
+       else if (i.types[0] == BIT && ((i.op.src[0] & ZEROBIT) == ZEROBIT))
+ 	{
+ 	  char temp = (i.maxq20_op[0].r_bit)->bit;
+ 	  temp = temp << 4;
+ 	  temp |= i.op.src[1];
+ 	  temp &= 0x7f;
+ 	  i.instr[1] = temp;
+ 	}
+       /* Similarly for a ONEBIT */
+       else if (i.types[0] == BIT && ((i.op.src[0] & ONEBIT) == ONEBIT))
+ 	{
+ 	  char temp = (i.maxq20_op[0].r_bit)->bit;
+ 	  temp = temp << 4;
+ 	  temp |= i.op.src[1];
+ 	  temp |= 0x80;
+ 	  i.instr[1] = temp;
+ 	}
+       /* In case the second operand is a register bit (MOVE C,Acc.<b> or MOVE 
+          C,src.<b> */
+       else if (i.types[1] == BIT)
+ 	{
+ 	  if (i.op.src[1] == 0 && i.op.src[1] == REG)
+ 	    {
+ 	      i.instr[1] = (i.maxq20_op[1].r_bit)->reg->opcode;
+ 	    }
+ 	  else if (i.op.src[0] == BIT && i.op.src)
+ 	    {
+ 	      char temp = (i.maxq20_op[1].r_bit)->bit;
+ 	      temp = temp << 4;
+ 	      temp |= i.op.src[1];
+ 	      i.instr[1] = temp;
+ 	    }
+ 	}
+       else
+ 	{
+ 	  as_bad (_("Invalid Instruction"));
+ 	  return 0;
+ 	}
+     }
+   return 1;
+ }
+ 
+ static int
+ maxq20_displacement (disp_start, disp_end)
+      char *disp_start;
+      char *disp_end;
+ {
+   expressionS *exp;
+   segT exp_seg = 0;
+   char *save_input_line_pointer;
+ #ifndef LEX_AT
+   char *gotfree_input_line;
+ #endif
+   gotfree_input_line = NULL;
+   exp = &disp_expressions;
+   i.maxq20_op[this_operand].disps = exp;
+   i.disp_operands++;
+   save_input_line_pointer = input_line_pointer;
+   input_line_pointer = disp_start;
+   END_STRING_AND_SAVE (disp_end);
+ 
+ #ifndef LEX_AT
+   /* gotfree_input_line = lex_got (&i.reloc[this_operand], NULL); if
+      (gotfree_input_line) input_line_pointer = gotfree_input_line; */
+ #endif
+   exp_seg = expression (exp);
+ 
+   SKIP_WHITESPACE ();
+   if (*input_line_pointer)
+     as_bad (_("junk `%s' after expression"), input_line_pointer);
+ #if GCC_ASM_O_HACK
+   RESTORE_END_STRING (disp_end + 1);
+ #endif
+   RESTORE_END_STRING (disp_end);
+   input_line_pointer = save_input_line_pointer;
+ #ifndef LEX_AT
+   if (gotfree_input_line)
+     free (gotfree_input_line);
+ #endif
+   if (exp->X_op == O_absent || exp->X_op == O_big)
+     {
+       /* Missing or bad expr becomes absolute 0.  */
+       as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
+ 	      disp_start);
+       exp->X_op = O_constant;
+       exp->X_add_number = 0;
+       exp->X_add_symbol = (symbolS *) 0;
+       exp->X_op_symbol = (symbolS *) 0;
+     }
+ #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
+ 
+   if (exp->X_op != O_constant
+ #ifdef BFD_ASSEMBLER
+       && OUTPUT_FLAVOR == bfd_target_aout_flavour
+ #endif
+       && exp_seg != absolute_section
+       && exp_seg != text_section
+       && exp_seg != data_section
+       && exp_seg != bss_section && exp_seg != undefined_section
+ #ifdef BFD_ASSEMBLER
+       && !bfd_is_com_section (exp_seg)
+ #endif
+     )
+     {
+ #ifdef BFD_ASSEMBLER
+       as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
+ #else
+       as_bad (_("unimplemented segment type %d in operand"), exp_seg);
+ #endif
+       return 0;
+     }
+ #endif
+   i.maxq20_op[this_operand].disps = exp;
+   return 1;
+ }
+ 
+ void
+ output_insn ()
+ {
+   fragS *insn_start_frag;
+   offsetT insn_start_off;
+   char *p;
+ 
+   /* Tie dwarf2 debug info to the address at the start of the insn. We can't
+      do this after the insn has been output as the current frag may have been 
+      closed off.  eg. by frag_var.  */
+   dwarf2_emit_insn (0);
+ 
+   /* To ALign the text section on word */
+ 
+   frag_align (1, 0, 1);
+ 
+   /* We initialise the frags for this particular instruction */
+   insn_start_frag = frag_now;
+   insn_start_off = frag_now_fix ();
+ 
+   /* If there are displacement operators(unresolved) present, then handle
+      them separately */
+   if (i.disp_operands)
+     {
+       output_disp (insn_start_frag, insn_start_off);
+       return;
+     }
+ 
+   if (i.data_operands)
+     {
+       output_data (insn_start_frag, insn_start_off);
+       return;
+     }
+   /* Check whether the INSERT_BUFFER has to be written */
+   if (strcmp (INSERT_BUFFER, ""))
+     {
+       p = frag_more (2);
+ 
+       *p++ = INSERT_BUFFER[1];
+       *p = INSERT_BUFFER[0];
+ 
+     }
+ 
+   /* Check whether the prefix instruction has to be written */
+   if (strcmp (PFX_INSN, ""))
+     {
+       p = frag_more (2);
+ 
+       *p++ = PFX_INSN[1];
+       *p = PFX_INSN[0];		/* Sudeep did i.PFX.. changed on 10/9/03 */
+ 
+     }
+ 
+   p = frag_more (2);
+   /* For Little endian */
+   *p++ = i.instr[1];
+   *p = i.instr[0];
+ 
+ }
+ 
+ /* This is a function for outputting displacement operands */
+ void
+ output_data (insn_start_frag, insn_start_off)
+      fragS *insn_start_frag;
+      offsetT insn_start_off;
+ {
+   char *p;
+   relax_substateT subtype;
+   symbolS *sym;
+   offsetT off;
+   int diff;
+   diff = 0;
+   off = 0;
+   insn_start_frag = frag_now;
+   insn_start_off = frag_now_fix ();
+ 
+   subtype = EXPLICT_LONG_PREFIX;
+ 
+   frag_grow (2 + 2);
+   p = frag_more (2);
+ 
+   sym = i.maxq20_op[this_operand].data;
+ #ifdef BFD_ASSEMBLER
+   off = 0;
+   /* off = (((expressionS *)symbol_get_value_expression(sym))->X_add_number); 
+    */
+ #else
+   off = 0;
+   /* off = (i.maxq20_op[this_operand].data)->sy_value.X_add_number; */
+ #endif
+ 
+   *p = i.instr[1];		/* This will be overwritten later when the
+ 				   symbol is resolved */
+   *(p + 1) = i.instr[0];
+ 
+   if (i.maxq20_op[this_operand].disps->X_op != O_constant	/* Changed
+ 								   6Feb2004
+ 								   for konark 
+ 								   bug */
+       && i.maxq20_op[this_operand].disps->X_op != O_symbol)
+     {
+       /* Handle complex expressions.  */
+       /* Commented on 6Feb2004 Vineet */
+       /* Becaouse data is already in terms of symbol so no need to convert it 
+          from expression to symbol */
+       /* sym = make_expr_symbol (i.maxq20_op[this_operand].disps); */
+       off = 0;
+     }
+ 
+   frag_var (rs_machine_dependent, 2, i.reloc[this_operand], subtype, sym, off,
+ 	    p);
+ }
+ 
+ /* This is a function for outputting displacement operands */
+ void
+ output_disp (insn_start_frag, insn_start_off)
+      fragS *insn_start_frag;
+      offsetT insn_start_off;
+ {
+   char *p;
+   relax_substateT subtype;
+   symbolS *sym;
+   offsetT off;
+   int diff;
+   diff = 0;
+   insn_start_frag = frag_now;
+   insn_start_off = frag_now_fix ();
+ 
+   switch (i.Instr_Prefix)
+     {
+ 
+     case LONG_PREFIX:
+       subtype = EXPLICT_LONG_PREFIX;
+       break;
+     case SHORT_PREFIX:
+       subtype = SHORT_PREFIX;
+       break;
+     default:
+       subtype = NO_PREFIX;
+       break;
+     }
+ 
+   /* Its a symbol. Here we end the frag and start the relaxation. Now in our
+      case there is no need for relaxation. But we do need support for a
+      prefix operator. Hence we will check whethere is room for 4 bytes ( 2
+      for prefix + 2 for the current instruction ) Hence if at a particular
+      time we find out whether the prefix operator is reqd , we shift the
+      current instruction two places ahead and insert the prefix instruction */
+   frag_grow (2 + 2);
+   p = frag_more (2);
+ 
+   sym = i.maxq20_op[this_operand].disps->X_add_symbol;
+   off = i.maxq20_op[this_operand].disps->X_add_number;
+ 
+   if (i.maxq20_op[this_operand].disps->X_add_symbol != NULL && sym && frag_now
+       && (subtype != EXPLICT_LONG_PREFIX))
+     {
+ 
+       /* If in Same frag */
+       if (frag_now == symbol_get_frag (sym))
+ 	{
+ 	  diff =
+ 	    ((((expressionS *) symbol_get_value_expression (sym))->
+ 	      X_add_number) - insn_start_off);
+ 
+ 	  diff = diff / MAXQ_OCTETS_PER_BYTE;
+ 
+ 	  if (diff >= -128 && diff <= 127)
+ 	    {
+ 	      i.instr[1] = (char) diff;
+ 
+ 	      *p = i.instr[1];	/* This will be overwritten later when the
+ 				   symbol is resolved */
+ 	      *(p + 1) = i.instr[0];
+ 
+ 	      return;		/* No Need to create a FIXUP */
+ 
+ 	    }
+ 	}
+ 
+     }
+ 
+   *p = i.instr[1];		/* This will be overwritten later when the
+ 				   symbol is resolved */
+   *(p + 1) = i.instr[0];
+ 
+   if (i.maxq20_op[this_operand].disps->X_op != O_constant	/* Nov 3
+ 								   /2003
+ 								   orginally
+ 								   [0].disp */
+       && i.maxq20_op[this_operand].disps->X_op != O_symbol)
+     {
+       /* Handle complex expressions.  */
+       sym = make_expr_symbol (i.maxq20_op[this_operand].disps);
+       off = 0;
+     }
+ 
+   /* Vineet : This has been added for md_estimate_size_before_relax to
+      estimate the correct size */
+   if (subtype != SHORT_PREFIX)
+     i.reloc[this_operand] = LONG_PREFIX;
+ 
+   frag_var (rs_machine_dependent, 2, i.reloc[this_operand], subtype, sym, off,
+ 	    p);
+ }
+ 
+ /* Function to calculate x to the power of y. Just to avoid the math
+    libraries. */
+ int
+ pwr (x, y)
+    int x;
+    int y;
+ {
+   int k, ans = 1;
+   for (k = 0; k < y; k++)
+     {
+       ans *= x;
+     }
+   return ans;
+ }
+ 
+ /* This function checks whether the operand is a variable in the data segment 
+    and if so, it returns its symbol entry from the symbol table. */
+ static symbolS *
+ maxq20_data (op_string)
+      char *op_string;
+ {
+   symbolS *symbolP;
+   symbolP = symbol_find (op_string);
+ #ifdef BFD_ASSEMBLER
+   if (symbolP != NULL && S_GET_SEGMENT (symbolP) != now_seg
+       && S_GET_SEGMENT (symbolP) != bfd_und_section_ptr)
+ #else
+   if (symbolP != NULL && S_GET_SEGMENT (symbolP) != now_seg
+       && S_GET_SEGMENT (symbolP) != SEG_UNKNOWN)
+ #endif
+     {
+       int val_pfx =
+ #ifdef BFD_ASSEMBLER
+ 	0;
+ #else
+ 	(symbolP->sy_value.X_add_number) >> 8;
+ #endif
+ 
+       /* In case we do not want to always include the prefix instruction and
+          let the loader handle the job or in case of a 8 bit addressing mode, 
+          we will just check for val_pfx to be equal to zero and then load the 
+          prefix instruction. Otherwise no prefix instruction needs to be
+          loaded. */
+       pfx_for_imm_val (val_pfx);	/* The prefix register will have to
+ 					   be loaded automatically as we have 
+ 					   a 16 bit addressing field. */
+       return symbolP;
+     }
+   else
+     return NULL;
+ }
+ 
+ unsigned char
+ IS_A_LSINSTR (ln_pointer)
+      const char *ln_pointer;
+ {
+   int i = 0;
+   for (i = 0; LSInstr[i] != NULL; i++)
+     {
+       if (!strcmp (LSInstr[i], ln_pointer))
+ 	return 1;
+     }
+ 
+   return 0;
+ }
+ 
+ void
+ LS_Processing (line)
+      const char *line;
+ {
+ 
+   if (IS_A_LSINSTR (line))
+     {
+       if ((line[0] == 'L') || (line[0] == 'l'))
+ 	{
+ 	  i.prefix = 0;
+ 	  INSERT_BUFFER[0] = PFX0;
+ 	  i.Instr_Prefix = LONG_PREFIX;
+ 	  return;
+ 	}
+ 
+       if ((line[0] == 'S') || (line[0] == 's'))
+ 	{
+ 	  i.Instr_Prefix = SHORT_PREFIX;
+ 	  return;
+ 	}
+ 
+       i.Instr_Prefix = NO_PREFIX;
+       return;
+ 
+     }
+   i.Instr_Prefix = LONG_PREFIX;
+   return;
+ }
+ 
+ int
+ extract_int_val (imm_start)
+      const char *imm_start;
+ {
+   int k, j, val;
+   char sign_val;
+   int temp[4];
+   k = 0;
+   j = 0;
+   val = 0;
+   sign_val = 0;
+   do
+     {
+       if (imm_start[k] == '-' && k == 0)
+ 	sign_val = -1;
+ 
+       else if (imm_start[k] == '+' && k == 0)
+ 	sign_val = 1;
+ 
+       else if (isdigit (imm_start[k]))
+ 	{
+ 	  temp[k] = imm_start[k] - '0';
+ 	}
+       else if (isalpha (imm_start[k]) && (tolower (imm_start[k])) < 'g')
+ 	{
+ 	  temp[k] = 10 + (int) (tolower (imm_start[k]) - 'a');
+ 	}
+       else if (tolower (imm_start[k]) == 'h')
+ 	break;
+       else if ((imm_start[k] == '\0') || (imm_start[k] == ']'))
+ 	{
+ 	  /* imm_start[k]='d'; */
+ 	  break;
+ 	}
+       else
+ 	{
+ 	  as_bad (_("Invalid Character in immediate Value : %c"),
+ 		  imm_start[k]);
+ 	  return 0;
+ 	}
+       k++;
+ 
+     }
+   while (imm_start[k] != '\n');
+ 
+   switch (imm_start[k])
+     {
+     case 'h':
+       for (j = (sign_val ? 1 : 0); j < k; j++)
+ 	{
+ 	  val += temp[j] * pwr (16, k - j - 1);
+ 	}
+       break;
+     default:
+       for (j = (sign_val ? 1 : 0); j < k; j++)
+ 	{
+ 	  if (temp[j] > 9)
+ 	    {
+ 	      as_bad (_("Invalid Character in immediate value : %c"),
+ 		      imm_start[j]);
+ 	      return 0;
+ 	    }
+ 	  val += temp[j] * pwr (10, k - j - 1);
+ 	}
+     }
+ 
+   if (!sign_val)
+     sign_val = 1;
+ 
+   return (val * sign_val);
+ }
+ 
+ char
+ check_for_parse (line)
+      const char *line;
+ {
+   int val;
+   if (*(line + 1) == '[')
+     {
+       do
+ 	{
+ 	  line++;
+ 	  if ((*line == '-') || (*line == '+'))
+ 	    break;
+ 
+ 	}
+       while (!is_space_char (*line));
+ 
+       if ((*line == '-') || (*line == '+'))
+ 	val = extract_int_val (line);
+       else
+ 	val = extract_int_val (line + 1);
+ 
+       INSERT_BUFFER[0] = 0x3E;
+       INSERT_BUFFER[1] = val;
+ 
+       return 1;
+     }
+ 
+   return 0;
+ }
+ 
+ void
+ make_new_reg_table ()
+ {
+   unsigned long size_pm = sizeof (peripheral_reg_table);
+   num_of_reg = size_pm / sizeof (peripheral_reg_table[0]);
+ 
+   new_reg_table = (reg_entry *) xmalloc (size_pm);
+   if (new_reg_table == NULL)
+     as_bad (_("Cannot allocate memory"));
+ 
+   memcpy (new_reg_table, peripheral_reg_table, size_pm);
+ }
+ 
+ /* pmmain performs the initilizations for the pheripheral modules. */
+ void
+ pmmain ()
+ {
+ 
+   make_new_reg_table ();
+   return;
+ }
Index: gas/config/tc-maxq.h
===================================================================
RCS file: gas/config/tc-maxq.h
diff -N gas/config/tc-maxq.h
*** /dev/null	1 Jan 1970 00:00:00 -0000
--- gas/config/tc-maxq.h	2 Nov 2004 13:51:42 -0000
***************
*** 0 ****
--- 1,188 ----
+ /* tc-maxq.h -- Header file for the asssembler(MAXQ) Copyright 2003, 2004
+    Free Software Foundation, Inc. Contributed by HCL Technologies Pvt.
+    Ltd.
+ 
+    Written by Vineet Sharma(vineets@noida.hcltech.com) Inderpreet
+    S.(inderpreetb@noida.hcltech.com)
+ 
+    This file is part of GAS.
+ 
+    GAS is free software; you can redistribute it and/or modify it under the
+    terms of the GNU General Public License as published by the Free Software
+    Foundation; either version 2, or (at your option) any later version.
+ 
+    GAS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more
+    details.
+ 
+    You should have received a copy of the GNU General Public License along
+    with GAS; see the file COPYING.  If not, write to the Free Software
+    Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+ 
+ #ifndef _TC_MAXQ_H_
+ #define  _TC_MAXQ_H_
+ 
+ #ifndef NO_RELOC
+ #define NO_RELOC 0
+ #endif
+ 
+ /* 
+    `md_short_jump_size' `md_long_jump_size' `md_create_short_jump'
+    `md_create_long_jump' If `WORKING_DOT_WORD' is defined, GAS will not do
+    broken word processing (*note Broken words::.).  Otherwise, you should set
+    `md_short_jump_size' to the size of a short jump (a jump that is just long
+    enough to jump around a long jmp) and `md_long_jump_size' to the size of a
+    long jump (a jump that can go anywhere in the function), You should define
+    `md_create_short_jump' to create a short jump around a long jump, and
+    define `md_create_long_jump' to create a long jump.  */
+ #define WORKING_DOT_WORD
+ typedef enum _RELOC_ENUM
+ { MAXQ_WORDDATA = 5,		/* Word+n */
+   MAXQ_LONGDATA = 2,		/* Long+n */
+   MAXQ_INTERSEGMENT = 4,	/* /Text to any other segment */
+   MAXQ_SHORTJUMP = BFD_RELOC_16_PCREL_S2,	/* PC Relative */
+   MAXQ_LONGJUMP = 6,		/* Absolute Jump */
+   EXTERNAL_RELOC = 8, INTERSEGMENT_RELOC
+ }
+ RELOC_ENUM;
+ 
+ #ifndef NEED_FX_R_TYPE
+ #define NEED_FX_R_TYPE		/* For defining our own rloc type.  */
+ #endif
+ 
+ #ifndef MAX_STACK
+ #define MAX_STACK 0xf
+ #endif
+ 
+ #ifndef TC_MAXQ20
+ #define TC_MAXQ20 1
+ #endif
+ 
+ #ifndef MAX_OPERAND_SIZE
+ #define MAX_OPERAND_SIZE 255
+ #endif
+ 
+ #ifndef MAXQ_INSTRUCTION_SIZE
+ #define MAXQ_INSTRUCTION_SIZE 2	/* 16 - BITS */
+ #endif
+ 
+ #if MAXQ_INSTRUCTION_SIZE
+ #define MAXQ_OCTETS_PER_BYTE 	MAXQ_INSTRUCTION_SIZE
+ #else
+ #define MAXQ_OCTETS_PER_BYTE 	OCTETS_PER_BYTE
+ #endif
+ 
+ /* if this macro is defined gas will use this instead of comment_chars.  */
+ #define tc_comments_chars maxq20_comment_chars
+ 
+ #define tc_coff_symbol_emit_hook(a)     ;	/* not used */
+ 
+ #define md_section_align(SEGMENT, SIZE)     (SIZE)
+ 
+ /* Locally defined symbol shoudnot be adjusted to section symbol.  */
+ #define tc_fix_adjustable(FIX) 0
+ 
+ #define TC_COFF_SIZEMACHDEP(frag) tc_coff_sizemachdep (frag)
+ extern int tc_coff_sizemachdep PARAMS ((fragS * frag));
+ 
+ /* This specifies that the target has been defined as little endian -
+    default.  */
+ #define TARGET_BYTES_BIG_ENDIAN 0
+ 
+ #define MAX_MEM_NAME_SIZE 12
+ #define MAX_REG_NAME_SIZE 7
+ #define MAX_MNEM_SIZE 8
+ 
+ #define END_OF_INSN '\0'
+ 
+ #ifndef ANSI_PROTOTYPES
+ #define ANSI_PROTOTYPES 0
+ #endif /* */
+ 
+ /* This macro is the BFD archetectureto pass to 'bfd_set_arch_mach'.  */
+ #define TARGET_ARCH		bfd_arch_maxq
+ 
+ /* This macro is the BFD machine number to pass to 'bfd_set_arch_mach'. if
+    not defines GAS will use 0 */
+ #define TARGET_MACH     	(maxq20_mach())
+ extern unsigned long maxq20_mach PARAMS ((void));
+ 
+ /* AOUT format */
+ #ifdef TE_LINUX
+ #define AOUT_TARGET_FORMAT	"a.out-maxq-linux"
+ #endif /* */
+ 
+ #ifndef AOUT_TARGET_FORMAT
+ #define AOUT_TARGET_FORMAT	"a.out-maxq"
+ #endif /* */
+ 
+ /* COFF format */
+ #ifndef BFD_ASSEMBLER
+ 
+ /* Defines the magic number we are using for the maxq-coff. defined in coff.h 
+  */
+ #define COFF_MAGIC MAXQ20MAGIC
+ #define BFD_ARCH bfd_arch_maxq
+ 
+ /* Whether the reloc should be outputted to the file or not. This is only
+    true if the symbol we are relocating for is not empty */
+ #define TC_COUNT_RELOC(fixp) ((fixp) -> fx_addsy != NULL)
+ 
+ /* This macro translates between an internal fix and an coff reloc type */
+ #define TC_COFF_FIX2RTYPE(fixP) tc_coff_fix2rtype(fixP)
+ extern short tc_coff_fix2rtype PARAMS ((struct fix *));
+ 
+ #endif /* BFD_ASSEMBLER */
+ 
+ #ifndef LEX_AT
+ 
+ /* We define this macro to generate a fixup for a data allocation pseudo-op. 
+  */
+ #define TC_CONS_FIX_NEW(FRAG,OFF,LEN,EXP) maxq20_cons_fix_new(FRAG,OFF,LEN,EXP)
+ extern void maxq20_cons_fix_new
+ PARAMS ((fragS *, unsigned int, unsigned int, expressionS *));
+ 
+ #endif /* LEX_AT */
+ 
+ /* Define md_number_to_chars as the appropriate standard big endian or This
+    should just call either `number_to_chars_bigendian' or
+    `number_to_chars_littleendian', whichever is appropriate.  On targets like 
+    the MIPS which support options to change the endianness, which function to 
+    call is a runtime decision.  On other targets, `md_number_to_chars' can be 
+    a simple macro.  */
+ #define md_number_to_chars maxq_number_to_chars
+ extern void maxq_number_to_chars (char *, valueT, int);
+ 
+ /* If this macro is defined, it is a pointer to a NULL terminated list of
+    chracters which may appear in an operand. GAS already assumes that all
+    alphanumeric chracters, and '$', '.', and '_' may appear in an
+    operand("symbol_char"in app.c). This macro may be defined to treat
+    additional chracters as appearing in an operand. This affects the way in
+    which GAS removes whitespaces before passing the string to md_assemble.  */
+ #define tc_symbol_chars_extra_symbol_chars
+ 
+ /* Define away the call to md_operand in the expression parsing code. This is 
+    called whenever the expression parser can't parse the input and gives the
+    assembler backend a chance to deal with it instead.  */
+ # define md_operand(x)
+ 
+ #define MAX_OPERANDS 2		/* Max operands per instructions */
+ #define MAX_IMMEDIATE_OPERANDS 1	/* Max immediate operations per
+ 					   instruction */
+ #define MAX_MEMORY_OPERANDS 1	/* Max memory operands per instruction */
+ 
+ /* Define the prefix we are using while trying to use an immediate value in
+    an instruction. e.g move A[0], #03h.  */
+ #define IMMEDIATE_PREFIX '#'
+ 
+ #define ABSOLUTE_PREFIX '@'
+ 
+ /* This here defines the opcode of the nop operation on the MAXQ. We did
+    declare it here when we tried to fill the align bites with nop's but GAS
+    only expects nop's to be single byte instruction.  */
+ #define NOP_OPCODE (char)0xDA3A
+ 
+ #define SIZE_OF_PM sizeof(pmodule)	/* size of the structure */
+ 
+ #endif /* TC_MAXQ_H */
Index: include/dis-asm.h
===================================================================
RCS file: /cvs/src/src/include/dis-asm.h,v
retrieving revision 1.46
diff -c -3 -p -r1.46 dis-asm.h
*** include/dis-asm.h	14 Nov 2003 15:12:43 -0000	1.46
--- include/dis-asm.h	2 Nov 2004 13:51:43 -0000
*************** extern int print_insn_i370		(bfd_vma, di
*** 195,200 ****
--- 195,202 ----
  extern int print_insn_m68hc11		(bfd_vma, disassemble_info *);
  extern int print_insn_m68hc12		(bfd_vma, disassemble_info *);
  extern int print_insn_m68k		(bfd_vma, disassemble_info *);
+ extern int print_insn_maxq_little	(bfd_vma, disassemble_info *);
+ extern int print_insn_maxq_big		(bfd_vma, disassemble_info *);
  extern int print_insn_z8001		(bfd_vma, disassemble_info *);
  extern int print_insn_z8002		(bfd_vma, disassemble_info *);
  extern int print_insn_h8300		(bfd_vma, disassemble_info *);
Index: include/coff/maxq.h
===================================================================
RCS file: include/coff/maxq.h
diff -N include/coff/maxq.h
*** /dev/null	1 Jan 1970 00:00:00 -0000
--- include/coff/maxq.h	2 Nov 2004 13:51:43 -0000
***************
*** 0 ****
--- 1,58 ----
+ /* COFF spec for MAXQ
+ 
+    Copyright 2001 Free Software Foundation, Inc.
+ 
+    This program is free software; you can redistribute it and/or modify it
+    under the terms of the GNU General Public License as published by the Free 
+    Software Foundation; either version 2 of the License, or (at your option)
+    any later version.
+ 
+    This program is distributed in the hope that it will be useful, but
+    WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 
+    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+    for more details.
+ 
+    You should have received a copy of the GNU General Public License along
+    with this program; if not, write to the Free Software Foundation, Inc., 59 
+    Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ 
+    Contributed by Vineet Sharma(vineets@noida.hcltech.com) Inderpreet
+    S.(inderpreetb@noida.hcltech.com) HCL Technologies Ltd.  */
+ 
+ #define L_LNNO_SIZE 2
+ 
+ #include "coff/external.h"
+ 
+ /* Bits for f_flags: F_RELFLG relocation info stripped from file F_EXEC file
+    is executable (no unresolved external references) F_LNNO line numbers
+    stripped from file F_LSYMS local symbols stripped from file F_AR32WR file
+    has byte ordering of an AR32WR machine (e.g. vax).  */
+ 
+ #define F_RELFLG        (0x0001)
+ #define F_EXEC          (0x0002)
+ #define F_LNNO          (0x0004)
+ #define F_LSYMS         (0x0008)
+ 
+ /* 
+  * Magic numbers for maxq
+  *  
+  */
+ #define MAXQ20MAGIC 0xa0	/* Defined by vineet */
+ 
+ #define MAXQ20BADMAG(x) (  ((x).f_magic != MAXQ20MAGIC) )
+ 
+ #define BADMAG(x)  MAXQ20BADMAG(x)
+ 
+ /* 
+  * Relocation information declaration and related definitions
+  */
+ struct external_reloc
+ {
+   char r_vaddr[4];		/* (virtual) address of reference */
+   char r_symndx[4];		/* index into symbol table */
+   char r_type[2];		/* relocation type */
+   char r_offset[2];		/* addend */
+ };
+ 
+ #define	RELOC		struct external_reloc
+ #define	RELSZ		10+2	/* sizeof (RELOC) */
Index: include/opcode/maxq.h
===================================================================
RCS file: include/opcode/maxq.h
diff -N include/opcode/maxq.h
*** /dev/null	1 Jan 1970 00:00:00 -0000
--- include/opcode/maxq.h	2 Nov 2004 13:51:43 -0000
***************
*** 0 ****
--- 1,1128 ----
+ /* maxq.h -- Header file for MAXQ opcode table Copyright (C) 2001, 2003 Free
+    Software Foundation, Inc.
+ 
+    This file is part of GDB, GAS, and the GNU binutils.
+ 
+    Written by Vineet Sharma(vineets@noida.hcltech.com)
+    Inderpreet Singh (inderpreetb@noida.hcltech.com)
+ 
+    GDB, GAS, and the GNU binutils are free software; you can redistribute
+    them and/or modify them under the terms of the GNU General Public License
+    as published by the Free Software Foundation; either version 2, or (at
+    your option) any later version.
+ 
+    GDB, GAS, and the GNU binutils are distributed in the hope that they will
+    be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General
+    Public License for more details.
+ 
+    You should have received a copy of the GNU General Public License along
+    with this file; see the file COPYING.  If not, write to the Free Software
+    Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+ 
+ #ifndef _MAXQ20_H_
+ #define  _MAXQ20_H_
+ 
+ /*********************************************************************
+ *  This file contains the opcode table for the MAXQ10/20 processor. The table
+ *    has been designed on the lines of the SH processor with the following 
+ * fields:
+ * (1) Instruction Name
+ * (2) Instruction arguments description
+ * (3) Description of the breakup of the opcode (1+7+8|8+8|1+4+4|1+7+1+3+4
+ *     |1+3+4+1+3+4|1+3+4+8|1+1+2+4+8)  
+ * (4) Architecture supported
+ *
+ * The Register table is also defined. It contains the following fields
+ * (1) Register name
+ * (2) Module Number
+ * (3) Module Index
+ * (4) Opcode
+ * (5) Regtype
+ *
+ * The Memory access table is defined containing the various opcodes for 
+ * memory access containing the following fields
+ * (1) Memory access Operand Name
+ * (2) Memory access Operand opcode
+ ******************************************************************** */
+ 
+ # define MAXQ10 0x0001
+ # define MAXQ20 0x0002
+ # define MAX (MAXQ10|MAXQ20)
+ 
+ /* This is for the NOP instruction Specify : 1st bit : NOP_FMT 1st byte:
+    NOP_DST 2nd byte: NOP_SRC */
+ # define NOP_FMT 1
+ # define NOP_SRC 0x3A
+ # define NOP_DST 0x5A
+ typedef enum
+ { ZEROBIT = 0x1,		/* A zero followed by 3 bits */
+   ONEBIT = 0x2,			/* A one followed by 3 bits */
+   REG = 0x4,			/* Register */
+   MEM = 0x8,			/* Memory access */
+   IMM = 0x10,			/* Immediate value */
+   DISP = 0x20,			/* Displacement value */
+   BIT = 0x40,			/* Bit value */
+   FMT = 0x80,			/* The format bit */
+   IMMBIT = 0x100,		/* An immediate bit */
+   FLAG = 0x200,			/* A Flag */
+   DATA = 0x400,			/* symbol in the data section */
+   BIT_BUCKET = 0x800,		/* FOr BIT BUCKET */
+ 
+ }
+ UNKNOWN_OP;
+ typedef enum
+ { A_IMM = 0x01,			/* An 8 bit immediate value */
+   A_REG = 0x2,			/* An 8 bit source register */
+   A_MEM = 0x4,			/* A 7 bit destination register */
+   FLAG_C = 0x8,			/* Carry Flag */
+   FLAG_NC = 0x10,		/* No Carry (~C) flag */
+   FLAG_Z = 0x20,		/* Zero Flag */
+   FLAG_NZ = 0x40,		/* Not Zero Flag */
+   FLAG_S = 0x80,		/* Sign Flag */
+   FLAG_E = 0x100,		/* Equals Flag */
+   FLAG_NE = 0x200,		/* Not Equal Flag */
+   ACC_BIT = 0x400,		/* One of the 16 accumulator bits of the form 
+ 				   Acc.<b> */
+   DST_BIT = 0x800,		/* One of the 8 bits of the specified SRC */
+   SRC_BIT = 0x1000,		/* One of the 8 bits of the specified source 
+ 				   register */
+   A_BIT_0 = 0x2000,		/* #0 */
+   A_BIT_1 = 0x4000,		/* #1 */
+   A_DISP = 0x8000,		/* Displacement Operand */
+   A_DATA = 0x10000,		/* Data in the data section */
+   A_BIT_BUCKET = 0x200000,
+ }
+ MAX_ARG_TYPE;
+ typedef struct
+ {
+   char *name;			/* Name of the instruction */
+   unsigned int op_number;	/* Operand Number or the number of operands */
+   MAX_ARG_TYPE arg[2];		/* Types of operands */
+   int format;			/* Format bit */
+   int dst[2];			/* Destination in the move instruction */
+   int src[2];			/* Source in the move instruction */
+   int arch;			/* The Machine architecture */
+   unsigned int instr_id;	/* Added for decode and dissassembly */
+ }
+ MAXQ20_OPCODE_INFO;
+ 
+ /* Structure for holding opcodes of the same name */
+ typedef struct
+ {
+   const MAXQ20_OPCODE_INFO *start;	/* The first opcode */
+   const MAXQ20_OPCODE_INFO *end;	/* The last opcode */
+ }
+ MAXQ20_OPCODES;
+ 
+ /* The entry into the hash table will be of the type MAXX_OPCODES */
+ 
+ /* The definition of the table */
+ const MAXQ20_OPCODE_INFO op_table[] = {
+   /* LOGICAL OPERATIONS */
+   /* AND src : f001 1010 ssss ssss */
+   {"AND", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x1a, 0},
+    {REG | MEM | IMM | DISP, 0}, MAX, 0x11},
+   /* AND Acc.<b> : 1111 1010 bbbb 1010 */
+   {"AND", 1, {ACC_BIT, 0}, 1, {0x1a, 0}, {BIT, 0xa}, MAX, 0x39},
+   /* OR src : f010 1010 ssss ssss */
+   {"OR", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x2a, 0},
+    {REG | MEM | IMM | DISP, 0}, MAX, 0x12},
+   /* OR Acc.<b> : 1010 1010 bbbb 1010 */
+   {"OR", 1, {ACC_BIT, 0}, 1, {0x2a, 0}, {BIT, 0xa}, MAX, 0x3A},
+   /* XOR src : f011 1010 ssss ssss */
+   {"XOR", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x3a, 0},
+    {REG | MEM | IMM | DISP, 0}, MAX, 0x13},
+   /* XOR Acc.<b> : 1011 1010 bbbb 1010 */
+   {"XOR", 1, {ACC_BIT, 0}, 1, {0x3a, 0}, {BIT, 0xa}, MAX, 0x3B},
+   /* LOGICAL OPERATIONS INVOLVING ONLY THE ACCUMULATOR */
+   /* CPL : 1000 1010 0001 1010 */
+   {"CPL", 0, {0, 0}, 1, {0x0a, 0}, {0x1a, 0}, MAX, 0x21},
+   /* CPL C : 1101 1010 0010 1010 */
+   {"CPL", 1, {FLAG_C, 0}, 1, {0x5a, 0}, {0x2a, 0}, MAX, 0x3D},
+   /* NEG : 1000 1010 1001 1010 */
+   {"NEG", 0, {0, 0}, 1, {0x0a, 0}, {0x9a, 0}, MAX, 0x29},
+   /* SLA : 1000 1010 0010 1010 */
+   {"SLA", 0, {0, 0}, 1, {0x0a, 0}, {0x2a, 0}, MAX, 0x22},
+   /* SLA2: 1000 1010 0011 1010 */
+   {"SLA2", 0, {0, 0}, 1, {0x0a, 0}, {0x3a, 0}, MAX, 0x23},
+   /* SLA4: 1000 1010 0110 1010 */
+   {"SLA4", 0, {0, 0}, 1, {0x0a, 0}, {0x6a, 0}, MAX, 0x26},
+   /* RL : 1000 1010 0100 1010 */
+   {"RL", 0, {0, 0}, 1, {0x0a, 0}, {0x4a, 0}, MAX, 0x24},
+   /* RLC : 1000 1010 0101 1010 */
+   {"RLC", 0, {0, 0}, 1, {0x0a, 0}, {0x5a, 0}, MAX, 0x25},
+   /* SRA : 1000 1010 1111 1010 */
+   {"SRA", 0, {0, 0}, 1, {0x0a, 0}, {0xfa, 0}, MAX, 0x2F},
+   /* SRA2: 1000 1010 1110 1010 */
+   {"SRA2", 0, {0, 0}, 1, {0x0a, 0}, {0xea, 0}, MAX, 0x2E},
+   /* SRA4: 1000 1010 1011 1010 */
+   {"SRA4", 0, {0, 0}, 1, {0x0a, 0}, {0xba, 0}, MAX, 0x2B},
+   /* SR : 1000 1010 1010 1010 */
+   {"SR", 0, {0, 0}, 1, {0x0a, 0}, {0xaa, 0}, MAX, 0x2A},
+   /* RR : 1000 1010 1100 1010 */
+   {"RR", 0, {0, 0}, 1, {0x0a, 0}, {0xca, 0}, MAX, 0x2C},
+   /* RRC : 1000 1010 1101 1010 */
+   {"RRC", 0, {0, 0}, 1, {0x0a, 0}, {0xda, 0}, MAX, 0x2D},
+   /* MATH OPERATIONS */
+   /* ADD src : f100 1010 ssss ssss */
+   {"ADD", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x4a, 0},
+    {IMM | REG | MEM | DISP, 0}, MAX, 0x14},
+   /* ADDC src : f110 1010 ssss ssss */
+   {"ADDC", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x6a, 0},
+    {IMM | REG | MEM | DISP, 0}, MAX, 0x16},
+   /* SUB src : f101 1010 ssss ssss */
+   {"SUB", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x5a, 0},
+    {IMM | REG | MEM | DISP, 0}, MAX, 0x15},
+   /* SUBB src : f111 1010 ssss ssss */
+   {"SUBB", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x7a, 0},
+    {IMM | REG | MEM | DISP, 0}, MAX, 0x17},
+   /* BRANCHING OPERATIONS */
+ 
+   /* DJNZ LC[0] src: f100 1101 ssss ssss */
+   {"DJNZ", 2, {A_REG, A_IMM | A_REG | A_MEM | A_DISP}, FMT, {0x4d, 0},
+    {IMM | REG | MEM | DISP, 0}, MAX, 0xA4},
+   /* DJNZ LC[1] src: f101 1101 ssss ssss */
+   {"DJNZ", 2, {A_REG, A_IMM | A_REG | A_MEM | A_DISP}, FMT, {0x5d, 0},
+    {IMM | REG | MEM | DISP, 0}, MAX, 0xA5},
+   /* CALL src : f011 1101 ssss ssss */
+   {"CALL", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x3d, 0},
+    {IMM | REG | MEM | DISP, 0}, MAX, 0xA3},
+   /* JUMP src : f000 1100 ssss ssss */
+   {"JUMP", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x0c, 0},
+    {IMM | REG | MEM | DISP, 0}, MAX, 0x50},
+   /* JUMP C,src : f010 1100 ssss ssss */
+   {"JUMP", 2, {FLAG_C, A_IMM | A_REG | A_MEM | A_DISP}, FMT, {0x2c, 0},
+    {IMM | REG | MEM | DISP, 0}, MAX, 0x52},
+   /* JUMP NC,src: f110 1100 ssss ssss */
+   {"JUMP", 2, {FLAG_NC, A_IMM | A_REG | A_MEM | A_DISP}, FMT, {0x6c, 0},
+    {IMM | REG | MEM | DISP, 0}, MAX, 0x56},
+   /* JUMP Z,src : f001 1100 ssss ssss */
+   {"JUMP", 2, {FLAG_Z, A_IMM | A_REG | A_MEM | A_DISP}, FMT, {0x1c, 0},
+    {IMM | REG | MEM | DISP, 0}, MAX, 0x51},
+   /* JUMP NZ,src: f101 1100 ssss ssss */
+   {"JUMP", 2, {FLAG_NZ, A_IMM | A_REG | A_MEM | A_DISP}, FMT, {0x5c, 0},
+    {IMM | REG | MEM | DISP, 0}, MAX, 0x55},
+   /* JUMP E,src : 0011 1100 ssss ssss */
+   {"JUMP", 2, {FLAG_E, A_IMM | A_DISP}, 0, {0x3c, 0}, {IMM, 0}, MAX, 0x53},
+   /* JUMP NE,src: 0111 1100 ssss ssss */
+   {"JUMP", 2, {FLAG_NE, A_IMM | A_DISP}, 0, {0x7c, 0}, {IMM, 0}, MAX, 0x57},
+   /* JUMP S,src : f100 1100 ssss ssss */
+   {"JUMP", 2, {FLAG_S, A_IMM | A_REG | A_MEM | A_DISP}, FMT, {0x4c, 0},
+    {IMM | REG | MEM | DISP, 0}, MAX, 0x54},
+   /* RET : 1000 1100 0000 1101 */
+   {"RET", 0, {0, 0}, 1, {0x0c, 0}, {0x0d, 0}, MAX, 0x68},
+   /* RET C : 1010 1100 0000 1101 */
+   {"RET", 1, {FLAG_C, 0}, 1, {0x2c, 0}, {0x0d, 0}, MAX, 0x6A},
+   /* RET NC : 1110 1100 0000 1101 */
+   {"RET", 1, {FLAG_NC, 0}, 1, {0x6c, 0}, {0x0d, 0}, MAX, 0x6E},
+   /* RET Z : 1001 1100 0000 1101 */
+   {"RET", 1, {FLAG_Z, 0}, 1, {0x1c, 0}, {0x0d, 0}, MAX, 0x69},
+   /* RET NZ : 1101 1100 0000 1101 */
+   {"RET", 1, {FLAG_NZ, 0}, 1, {0x5c, 0}, {0x0d, 0}, MAX, 0x6D},
+   /* RET S : 1100 1100 0000 1101 */
+   {"RET", 1, {FLAG_S, 0}, 1, {0x4c, 0}, {0x0d, 0}, MAX, 0x6C},
+   /* RETI : 1000 1100 1000 1101 */
+   {"RETI", 0, {0, 0}, 1, {0x0c, 0}, {0x8d, 0}, MAX, 0x78},
+   /* ADDED ACCORDING TO NEW SPECIFICATION */
+ 
+   /* RETI C : 1010 1100 1000 1101 */
+   {"RETI", 1, {FLAG_C, 0}, 1, {0x2c, 0}, {0x8d, 0}, MAX, 0x7A},
+   /* RETI NC : 1110 1100 1000 1101 */
+   {"RETI", 1, {FLAG_NC, 0}, 1, {0x6c, 0}, {0x8d, 0}, MAX, 0x7E},
+   /* RETI Z : 1001 1100 1000 1101 */
+   {"RETI", 1, {FLAG_Z, 0}, 1, {0x1c, 0}, {0x8d, 0}, MAX, 0x79},
+   /* RETI NZ : 1101 1100 1000 1101 */
+   {"RETI", 1, {FLAG_NZ, 0}, 1, {0x5c, 0}, {0x8d, 0}, MAX, 0x7D},
+   /* RETI S : 1100 1100 1000 1101 */
+   {"RETI", 1, {FLAG_S, 0}, 1, {0x4c, 0}, {0x8d, 0}, MAX, 0x7C},
+   /* MISCELLANEOUS INSTRUCTIONS */
+   /* CMP src : f111 1000 ssss ssss */
+   {"CMP", 1, {A_REG | A_IMM | A_MEM | A_DISP, 0}, FMT, {0x78, 0},
+    {REG | MEM | IMM | DISP, 0}, MAX, 0xD7},
+   /* DATA TRANSFER OPERATIONS */
+   /* XCH : 1000 1010 1000 1010 */
+   {"XCH", 0, {0, 0}, 1, {0x0a, 0}, {0x8a, 0}, MAXQ20, 0x28},
+   /* XCHN : 1000 1010 0111 1010 */
+   {"XCHN", 0, {0, 0}, 1, {0x0a, 0}, {0x7a, 0}, MAX, 0x27},
+   /* PUSH src : f000 1101 ssss ssss */
+   {"PUSH", 1, {A_REG | A_IMM | A_MEM | A_DISP, 0}, FMT, {0x0d, 0},
+    {IMM | REG | MEM | DISP, 0}, MAX, 0xA0},
+   /* POP dst : 1ddd dddd 0000 1101 */
+   {"POP", 1, {A_REG, 0}, 1, {REG, 0}, {0x0d, 0}, MAX, 0xB0},
+   /* Added according to new spec */
+   /* POPI dst : 1ddd dddd 1000 1101 */
+   {"POPI", 1, {A_REG, 0}, 1, {REG, 0}, {0x8d, 0}, MAX, 0xC0},
+   /* MOVE dst,src: fddd dddd ssss ssss */
+   {"MOVE", 2, {A_REG | A_MEM, A_REG | A_IMM | A_MEM | A_DATA | A_DISP}, FMT,
+    {REG | MEM, 0}, {REG | IMM | MEM | DATA | A_DISP, 0}, MAX, 0x80},
+   /* BIT OPERATIONS */
+   /* MOVE C,Acc.<b> : 1110 1010 bbbb 1010 */
+   {"MOVE", 2, {FLAG_C, ACC_BIT}, 1, {0x6a, 0}, {BIT, 0xa}, MAX, 0x3E},
+   /* MOVE C,#0 : 1101 1010 0000 1010 */
+   {"MOVE", 2, {FLAG_C, A_BIT_0}, 1, {0x5a, 0}, {0x0a, 0}, MAX, 0x3D},
+   /* MOVE C,#1 : 1101 1010 0001 1010 */
+   {"MOVE", 2, {FLAG_C, A_BIT_1}, 1, {0x5a, 0}, {0x1a, 0}, MAX, 0x3D},
+   /* MOVE Acc.<b>,C : 1111 1010 bbbb 1010 */
+   {"MOVE", 2, {ACC_BIT, FLAG_C}, 1, {0x7a, 0}, {BIT, 0xa}, MAX, 0x3F},
+   /* MOVE dst.<b>,#0 : 1ddd dddd 0bbb 0111 */
+   {"MOVE", 2, {DST_BIT, A_BIT_0}, 1, {REG, 0}, {ZEROBIT, 0x7}, MAX, 0x40},
+   /* MOVE dst.<b>,#1 : 1ddd dddd 1bbb 0111 */
+   {"MOVE", 2, {DST_BIT, A_BIT_1}, 1, {REG, 0}, {ONEBIT, 0x7}, MAX, 0x41},
+   /* MOVE C,src.<b> : fbbb 0111 ssss ssss */
+   {"MOVE", 2, {FLAG_C, SRC_BIT}, FMT, {BIT, 0x7}, {REG, 0}, MAX, 0x97},
+   /* NOP : 1101 1010 0011 1010 */
+   {"NOP", 0, {0, 0}, NOP_FMT, {NOP_DST, 0}, {NOP_SRC, 0}, MAX, 0x3D},
+   {NULL, 0, {0, 0}, 0, {0, 0}, {0, 0}, 0, 0x00}
+ };
+ 
+ /* All the modules */
+ 
+ #define	MOD0 0x0
+ #define MOD1 0x1
+ #define MOD2 0x2
+ #define MOD3 0x3
+ #define MOD4 0x4
+ #define MOD5 0x5
+ #define MOD6 0x6
+ #define MOD7 0x7
+ #define MOD8 0x8
+ #define MOD9 0x9
+ #define MODA 0xa
+ #define MODB 0xb
+ #define MODC 0xc
+ #define MODD 0xd
+ #define MODE 0xe
+ #define MODF 0xf
+ 
+ /* ADDED ACCORDING TO NEW SPECIFICATION */
+ #define MOD10 0x10
+ #define MOD11 0x11
+ #define MOD12 0x12
+ #define MOD13 0x13
+ #define MOD14 0x14
+ #define MOD15 0x15
+ #define MOD16 0x16
+ #define MOD17 0x17
+ #define MOD18 0x18
+ #define MOD19 0x19
+ #define MOD1A 0x1a
+ #define MOD1B 0x1b
+ #define MOD1C 0x1c
+ #define MOD1D 0x1d
+ #define MOD1E 0x1e
+ #define MOD1F 0x1f
+ 
+ /* - Peripheral Register Modules - */
+ /* Serial Register Modules */
+ #define CTRL		MOD8	/* For the module containing the control
+ 				   registers */
+ #define ACC	 	MOD9	/* For the module containing the 16
+ 				   accumulators */
+ #define Act_ACC 	MODA	/* For the module containing the active
+ 				   accumulator */
+ #define PFX  		MODB	/* For the module containing the prefix
+ 				   registers */
+ #define IP	 	MODC	/* For the module containing the instruction
+ 				   pointer register. */
+ #define SPIV 		MODD	/* For the module containing the stack
+ 				   pointer and the interrupt vector */
+ #define	LC 		MODD	/* For the module containing the loop
+ 				   counters and HILO registers */
+ #define DP 		MODF	/* For the module containig the data pointer
+ 				   registers */
+ 
+ /* Register Types */
+ typedef enum _Reg_type
+ { Reg_8R,			/* 8 bit register. read only */
+   Reg_16R,			/* 16 bit register, read only */
+   Reg_8W,			/* 8 bit register, both read and write */
+   Reg_16W			/* 16 bit register, both read and write */
+ }
+ Reg_type;
+ 
+ /* Register Structure */
+ typedef struct reg
+ {
+   char *reg_name;		/* Register name */
+   short int Mod_name;		/* The module name */
+   short int Mod_index;		/* The module index */
+   int opcode;			/* The opcode of the register */
+   Reg_type rtype;		/* 8 bit/16 bit and read only/read write */
+   int arch;			/* The Machine architecture */
+ }
+ reg_entry;
+ reg_entry *new_reg_table = NULL;
+ int num_of_reg = 0;
+ typedef struct
+ {
+   char *rname;
+   int rindex;
+ }
+ reg_index;
+ 
+ /* Register Table description */
+ reg_entry system_reg_table[] = {
+ 
+   /* Serial Registers */
+   /* MODULE 8 Registers : I call them the control registers */
+   /* Accumulator Pointer CTRL[0h] */
+   {
+    "AP", CTRL, 0x0, 0x00 | CTRL, Reg_8W, MAX},
+   /* Accumulator Pointer Control Register : CTRL[1h] */
+ 
+   {
+    "APC", CTRL, 0x1, 0x10 | CTRL, Reg_8W, MAX},
+   /* Processor Status Flag Register CTRL[4h] Note: Bits 6 and 7 read only */
+   {
+    "PSF", CTRL, 0x4, 0x40 | CTRL, Reg_8W, MAX},
+   /* Interrupt and Control Register : CTRL[5h] */
+   {
+    "IC", CTRL, 0x5, 0x50 | CTRL, Reg_8W, MAX},
+   /* Interrupt Mask Register : CTRL[6h] */
+   {
+    "IMR", CTRL, 0x6, 0x60 | CTRL, Reg_8W, MAX},
+   /* Interrupt System Control : CTRL[8h] */
+   {
+    "SC", CTRL, 0x8, 0x80 | CTRL, Reg_8W, MAX},
+   /* Interrupt Identification Register : CTRL[Bh] */
+   {
+    "IIR", CTRL, 0xb, 0xb0 | CTRL, Reg_8R, MAX},
+   /* System Clock Control Register : CTRL[Eh] Note: Bit 5 is read only */
+   {
+    "CKCN", CTRL, 0xe, 0xe0 | CTRL, Reg_8W, MAX},
+   /* Watchdog Control Register : CTRL[Fh] */
+   {
+    "WDCN", CTRL, 0xf, 0xf0 | CTRL, Reg_8W, MAX},
+   /* The 16 accumulator registers : ACC[0h-Fh] */
+   {
+    "A[0]", ACC, 0x0, 0x00 | ACC, Reg_16W, MAXQ20},
+   {
+    "A[1]", ACC, 0x1, 0x10 | ACC, Reg_16W, MAXQ20},
+   {
+    "A[2]", ACC, 0x2, 0x20 | ACC, Reg_16W, MAXQ20},
+   {
+    "A[3]", ACC, 0x3, 0x30 | ACC, Reg_16W, MAXQ20},
+   {
+    "A[4]", ACC, 0x4, 0x40 | ACC, Reg_16W, MAXQ20},
+   {
+    "A[5]", ACC, 0x5, 0x50 | ACC, Reg_16W, MAXQ20},
+   {
+    "A[6]", ACC, 0x6, 0x60 | ACC, Reg_16W, MAXQ20},
+   {
+    "A[7]", ACC, 0x7, 0x70 | ACC, Reg_16W, MAXQ20},
+   {
+    "A[8]", ACC, 0x8, 0x80 | ACC, Reg_16W, MAXQ20},
+   {
+    "A[9]", ACC, 0x9, 0x90 | ACC, Reg_16W, MAXQ20},
+   {
+    "A[10]", ACC, 0xa, 0xa0 | ACC, Reg_16W, MAXQ20},
+   {
+    "A[11]", ACC, 0xb, 0xb0 | ACC, Reg_16W, MAXQ20},
+   {
+    "A[12]", ACC, 0xc, 0xc0 | ACC, Reg_16W, MAXQ20},
+   {
+    "A[13]", ACC, 0xd, 0xd0 | ACC, Reg_16W, MAXQ20},
+   {
+    "A[14]", ACC, 0xe, 0xe0 | ACC, Reg_16W, MAXQ20},
+   {
+    "A[15]", ACC, 0xf, 0xf0 | ACC, Reg_16W, MAXQ20},
+   /* The Active Accumulators : Act_Acc[0h-1h] */
+   {
+    "ACC", Act_ACC, 0x0, 0x00 | Act_ACC, Reg_16W, MAXQ20},
+   {
+    "A[AP]", Act_ACC, 0x1, 0x10 | Act_ACC, Reg_16W, MAXQ20},
+   /* The 16 accumulator registers : ACC[0h-Fh] */
+   {
+    "A[0]", ACC, 0x0, 0x00 | ACC, Reg_8W, MAXQ10},
+   {
+    "A[1]", ACC, 0x1, 0x10 | ACC, Reg_8W, MAXQ10},
+   {
+    "A[2]", ACC, 0x2, 0x20 | ACC, Reg_8W, MAXQ10},
+   {
+    "A[3]", ACC, 0x3, 0x30 | ACC, Reg_8W, MAXQ10},
+   {
+    "A[4]", ACC, 0x4, 0x40 | ACC, Reg_8W, MAXQ10},
+   {
+    "A[5]", ACC, 0x5, 0x50 | ACC, Reg_8W, MAXQ10},
+   {
+    "A[6]", ACC, 0x6, 0x60 | ACC, Reg_8W, MAXQ10},
+   {
+    "A[7]", ACC, 0x7, 0x70 | ACC, Reg_8W, MAXQ10},
+   {
+    "A[8]", ACC, 0x8, 0x80 | ACC, Reg_8W, MAXQ10},
+   {
+    "A[9]", ACC, 0x9, 0x90 | ACC, Reg_8W, MAXQ10},
+   {
+    "A[10]", ACC, 0xa, 0xa0 | ACC, Reg_8W, MAXQ10},
+   {
+    "A[11]", ACC, 0xb, 0xb0 | ACC, Reg_8W, MAXQ10},
+   {
+    "A[12]", ACC, 0xc, 0xc0 | ACC, Reg_8W, MAXQ10},
+   {
+    "A[13]", ACC, 0xd, 0xd0 | ACC, Reg_8W, MAXQ10},
+   {
+    "A[14]", ACC, 0xe, 0xe0 | ACC, Reg_8W, MAXQ10},
+   {
+    "A[15]", ACC, 0xf, 0xf0 | ACC, Reg_8W, MAXQ10},
+   /* The Active Accumulators : Act_Acc[0h-1h] */
+   {
+    "A[AP]", Act_ACC, 0x1, 0x10 | Act_ACC, Reg_8W, MAXQ10},
+   /* The Active Accumulators : Act_Acc[0h-1h] */
+   {
+    "ACC", Act_ACC, 0x0, 0x00 | Act_ACC, Reg_8W, MAXQ10},
+   /* The Prefix Registers : PFX[0h,2h] */
+   {
+    "PFX[0]", PFX, 0x0, 0x00 | PFX, Reg_16W, MAX},
+   {
+    "PFX[1]", PFX, 0x1, 0x10 | PFX, Reg_16W, MAX},
+   {
+    "PFX[2]", PFX, 0x2, 0x20 | PFX, Reg_16W, MAX},
+   {
+    "PFX[3]", PFX, 0x3, 0x30 | PFX, Reg_16W, MAX},
+   {
+    "PFX[4]", PFX, 0x4, 0x40 | PFX, Reg_16W, MAX},
+   {
+    "PFX[5]", PFX, 0x5, 0x50 | PFX, Reg_16W, MAX},
+   {
+    "PFX[6]", PFX, 0x6, 0x60 | PFX, Reg_16W, MAX},
+   {
+    "PFX[7]", PFX, 0x7, 0x70 | PFX, Reg_16W, MAX},
+   /* The Instruction Pointer Registers : IP[0h,8h] */
+   {
+    "IP", IP, 0x0, 0x00 | IP, Reg_16W, MAX},
+   /* The Stack Pointer Registers : SPIV[1h,9h] */
+   {
+    "SP", SPIV, 0x1, 0x10 | SPIV, Reg_16W, MAX},
+   /* The Interrupt Vector Registers : SPIV[2h,Ah] */
+   {
+    "IV", SPIV, 0x2, 0x20 | SPIV, Reg_16W, MAX},
+   /* ADDED for New Specification */
+ 
+   /* The Loop Counter Registers : LCHILO[0h-4h,8h-Bh] */
+   {
+    "LC[0]", LC, 0x6, 0x60 | LC, Reg_16W, MAX},
+   {
+    "LC[1]", LC, 0x7, 0x70 | LC, Reg_16W, MAX},
+   /* MODULE Eh Whole Column has changed */
+ 
+   {
+    "OFFS", MODE, 0x3, 0x30 | MODE, Reg_8W, MAX},
+   {
+    "DPC", MODE, 0x4, 0x40 | MODE, Reg_16W, MAX},
+   {
+    "GR", MODE, 0x5, 0x50 | MODE, Reg_16W, MAX},
+   {
+    "GRL", MODE, 0x6, 0x60 | MODE, Reg_8W, MAX},
+   {
+    "BP", MODE, 0x7, 0x70 | MODE, Reg_16W, MAX},
+   {
+    "GRS", MODE, 0x8, 0x80 | MODE, Reg_16W, MAX},
+   {
+    "GRH", MODE, 0x9, 0x90 | MODE, Reg_8W, MAX},
+   {
+    "GRXL", MODE, 0xA, 0xA0 | MODE, Reg_8R, MAX},
+   {
+    "FP", MODE, 0xB, 0xB0 | MODE, Reg_16R, MAX},
+   /* The Data Pointer registers : DP[3h,7h,Bh,Fh] */
+   {
+    "DP[0]", DP, 0x3, 0x30 | DP, Reg_16W, MAX},
+   {
+    "DP[1]", DP, 0x7, 0x70 | DP, Reg_16W, MAX},
+ };
+ typedef struct
+ {
+   char *name;
+   int type;
+ }
+ match_table;
+ 
+ #define GPIO0   	0x00	/* Gerneral Purpose I/O Module 0 */
+ #define GPIO1   	0x01	/* Gerneral Purpose I/O Module 1 */
+ #define RTC	  	0x00	/* Real Time Clock Module */
+ #define MAC	  	0x02	/* Hardware Multiplier Module */
+ #define SER0	  	0x02	/* Contains the UART Registers */
+ #define SPI	  	0x03	/* Serial Pheripheral Interface Module */
+ #define OWBM  		0x03	/* One Wire Bus Module */
+ #define SER1	  	0x03	/* Contains the UART Registers */
+ #define TIMER20		0x03	/* Timer Counter Module 2 */
+ #define TIMER21		0x04	/* Timer Counter Module 2 */
+ #define JTAGD 		0x03	/* In-Circuit Debugging Support */
+ #define LCD		0x03	/* LCD register Modules */
+ 
+ /* 
+  *      Plugable modules register table f
+  */
+ reg_entry peripheral_reg_table[] = {
+ 
+   /* -------- The GPIO Module Registers -------- */
+   /* Port n Output Registers : GPIO[0h-4h] */
+   {
+    "PO0", GPIO0, 0x0, 0x00 | MOD0, Reg_8W, MAX},
+   {
+    "PO1", GPIO0, 0x1, 0x10 | MOD0, Reg_8W, MAX},
+   {
+    "PO2", GPIO0, 0x2, 0x20 | MOD0, Reg_8W, MAX},
+   {
+    "PO3", GPIO0, 0x3, 0x30 | MOD0, Reg_8W, MAX},
+   /* External Interrupt Flag Register : GPIO[6h] */
+   {
+    "EIF0", GPIO0, 0x6, 0x60 | MOD0, Reg_8W, MAX},
+   /* External Interrupt Enable Register : GPIO[7h] */
+   {
+    "EIE0", GPIO0, 0x7, 0x70 | MOD0, Reg_8W, MAX},
+   /* Port n Input Registers : GPIO[8h-Bh] */
+   {
+    "PI0", GPIO0, 0x8, 0x80 | MOD0, Reg_8W, MAX},
+   {
+    "PI1", GPIO0, 0x9, 0x90 | MOD0, Reg_8W, MAX},
+   {
+    "PI2", GPIO0, 0xa, 0xa0 | MOD0, Reg_8W, MAX},
+   {
+    "PI3", GPIO0, 0xb, 0xb0 | MOD0, Reg_8W, MAX},
+   {
+    "EIES0", GPIO0, 0xc, 0xc0 | MOD0, Reg_8W, MAX},
+   /* Port n Direction Registers : GPIO[Ch-Fh] */
+   {
+    "PD0", GPIO0, 0x10, 0x10 | MOD0, Reg_8W, MAX},
+   {
+    "PD1", GPIO0, 0x11, 0x11 | MOD0, Reg_8W, MAX},
+   {
+    "PD2", GPIO0, 0x12, 0x12 | MOD0, Reg_8W, MAX},
+   {
+    "PD3", GPIO0, 0x13, 0x13 | MOD0, Reg_8W, MAX},
+   /* -------- Real Time Counter Module RTC -------- */
+   /* RTC Control Register : [01h] */
+   {
+    "RCNT", RTC, 0x19, 0x19 | MOD0, Reg_16W, MAX},
+   /* RTC Seconds High [02h] */
+   {
+    "RTSS", RTC, 0x1A, 0x1A | MOD0, Reg_8W, MAX},
+   /* RTC Seconds Low [03h] */
+   {
+    "RTSH", RTC, 0x1b, 0x1b | MOD0, Reg_16W, MAX},
+   /* RTC Subsecond Register [04h] */
+   {
+    "RTSL", RTC, 0x1C, 0x1C | MOD0, Reg_16W, MAX},
+   /* RTC Alarm seconds high [05h] */
+   {
+    "RSSA", RTC, 0x1D, 0x1D | MOD0, Reg_8W, MAX},
+   /* RTC Alarm seconds high [06h] */
+   {
+    "RASH", RTC, 0x1E, 0x1E | MOD0, Reg_8W, MAX},
+   /* RTC Subsecond Alarm Register [07h] */
+   {
+    "RASL", RTC, 0x1F, 0x1F | MOD0, Reg_16W, MAX},
+   /* -------- The GPIO Module Registers -------- */
+   /* Port n Output Registers : GPIO[0h-4h] */
+   {
+    "PO4", GPIO1, 0x0, 0x00 | MOD1, Reg_8W, MAX},
+   {
+    "PO5", GPIO1, 0x1, 0x10 | MOD1, Reg_8W, MAX},
+   {
+    "PO6", GPIO1, 0x2, 0x20 | MOD1, Reg_8W, MAX},
+   {
+    "PO7", GPIO1, 0x3, 0x30 | MOD1, Reg_8W, MAX},
+   /* External Interrupt Flag Register : GPIO[6h] */
+   {
+    "EIF1", GPIO0, 0x6, 0x60 | MOD1, Reg_8W, MAX},
+   /* External Interrupt Enable Register : GPIO[7h] */
+   {
+    "EIE1", GPIO0, 0x7, 0x70 | MOD1, Reg_8W, MAX},
+   /* Port n Input Registers : GPIO[8h-Bh] */
+   {
+    "PI4", GPIO1, 0x8, 0x80 | MOD1, Reg_8W, MAX},
+   {
+    "PI5", GPIO1, 0x9, 0x90 | MOD1, Reg_8W, MAX},
+   {
+    "PI6", GPIO1, 0xa, 0xa0 | MOD1, Reg_8W, MAX},
+   {
+    "PI7", GPIO1, 0xb, 0xb0 | MOD1, Reg_8W, MAX},
+   {
+    "EIES1", GPIO1, 0xc, 0xc0 | MOD1, Reg_8W, MAX},
+   /* Port n Direction Registers : GPIO[Ch-Fh] */
+   {
+    "PD4", GPIO1, 0x10, 0x10 | MOD1, Reg_8W, MAX},
+   {
+    "PD5", GPIO1, 0x11, 0x11 | MOD1, Reg_8W, MAX},
+   {
+    "PD6", GPIO1, 0x12, 0x12 | MOD1, Reg_8W, MAX},
+   {
+    "PD7", GPIO1, 0x13, 0x13 | MOD1, Reg_8W, MAX},
+ #if 0
+   /* Supply Boltage Check Register */
+   {
+    "SVS", GPIO1, 0x1e, 0x1e | GPIO1, Reg_8W, MAX},
+   /* Wake up output register */
+   {
+    "WK0", GPIO1, 0x1f, 0x1f | GPIO1, Reg_8W, MAX},
+ #endif /* */
+ 
+   /* -------- MAC Hardware multiplier module -------- */
+   /* MAC Hardware Multiplier control register: [01h] */
+   {
+    "MCNT", MAC, 0x1, 0x10 | MOD2, Reg_8W, MAX},
+   /* MAC Multiplier Operand A Register [02h] */
+   {
+    "MA", MAC, 0x2, 0x20 | MOD2, Reg_16W, MAX},
+   /* MAC Multiplier Operand B Register [03h] */
+   {
+    "MB", MAC, 0x3, 0x30 | MOD2, Reg_16W, MAX},
+   /* MAC Multiplier Accumulator 2 Register [04h] */
+   {
+    "MC2", MAC, 0x4, 0x40 | MOD2, Reg_16W, MAX},
+   /* MAC Multiplier Accumulator 1 Register [05h] */
+   {
+    "MC1", MAC, 0x5, 0x50 | MOD2, Reg_16W, MAX},
+   /* MAC Multiplier Accumulator 0 Register [06h] */
+   {
+    "MC0", MAC, 0x6, 0x60 | MOD2, Reg_16W, MAX},
+   /* -------- The Serial I/O module SER -------- */
+   /* UART registers */
+   /* Serial Port Control Register : SER[6h] */
+   {
+    "SCON0", SER0, 0x6, 0x60 | MOD2, Reg_8W, MAX},
+   /* Serial Data Buffer Register : SER[7h] */
+   {
+    "SBUF0", SER0, 0x7, 0x70 | MOD2, Reg_8W, MAX},
+   /* Serial Port Mode Register : SER[4h] */
+   {
+    "SMD0", SER0, 0x8, 0x80 | MOD2, Reg_8W, MAX},
+   /* Serial Port Phase Register : SER[4h] */
+   {
+    "PR0", SER1, 0x9, 0x90 | MOD2, Reg_16W, MAX},
+   /* ------ LCD Display Module ---------- */
+   {
+    "LCRA", LCD, 0xd, 0xd0 | MOD2, Reg_16W, MAX},
+   {
+    "LCFG", LCD, 0xe, 0xe0 | MOD2, Reg_8W, MAX},
+   {
+    "LCD16", LCD, 0xf, 0xf0 | MOD2, Reg_8W, MAX},
+   {
+    "LCD0", LCD, 0x10, 0x10 | MOD2, Reg_8W, MAX},
+   {
+    "LCD1", LCD, 0x11, 0x11 | MOD2, Reg_8W, MAX},
+   {
+    "LCD2", LCD, 0x12, 0x12 | MOD2, Reg_8W, MAX},
+   {
+    "LCD3", LCD, 0x13, 0x13 | MOD2, Reg_8W, MAX},
+   {
+    "LCD4", LCD, 0x14, 0x14 | MOD2, Reg_8W, MAX},
+   {
+    "LCD5", LCD, 0x15, 0x15 | MOD2, Reg_8W, MAX},
+   {
+    "LCD6", LCD, 0x16, 0x16 | MOD2, Reg_8W, MAX},
+   {
+    "LCD7", LCD, 0x17, 0x17 | MOD2, Reg_8W, MAX},
+   {
+    "LCD8", LCD, 0x18, 0x18 | MOD2, Reg_8W, MAX},
+   {
+    "LCD9", LCD, 0x19, 0x19 | MOD2, Reg_8W, MAX},
+   {
+    "LCD10", LCD, 0x1a, 0x1a | MOD2, Reg_8W, MAX},
+   {
+    "LCD11", LCD, 0x1b, 0x1b | MOD2, Reg_8W, MAX},
+   {
+    "LCD12", LCD, 0x1c, 0x1c | MOD2, Reg_8W, MAX},
+   {
+    "LCD13", LCD, 0x1d, 0x1d | MOD2, Reg_8W, MAX},
+   {
+    "LCD14", LCD, 0x1e, 0x1e | MOD2, Reg_8W, MAX},
+   {
+    "LCD15", LCD, 0x1f, 0x1f | MOD2, Reg_8W, MAX},
+   /* -------- SPI registers -------- */
+   /* SPI data buffer Register : SER[7h] */
+   {
+    "SPIB", SPI, 0x5, 0x50 | MOD3, Reg_16W, MAX},
+   /* SPI Control Register : SER[8h] Note : Bit 7 is a read only bit */
+   {
+    "SPICN", SPI, 0x15, 0x15 | MOD3, Reg_8W, MAX},
+   /* SPI Configuration Register : SER[9h] Note : Bits 4,3 and 2 are read
+      only.  */
+   {
+    "SPICF", SPI, 0x16, 0x16 | MOD3, Reg_8W, MAX},
+   /* SPI Clock Register : SER[Ah] */
+   {
+    "SPICK", SPI, 0x17, 0x17 | MOD3, Reg_8W, MAX},
+   /* -------- One Wire Bus Master OWBM -------- */
+   /* OWBM One Wire address Register register: [01h] */
+   {
+    "OWA", OWBM, 0x13, 0x13 | MOD3, Reg_8W, MAX},
+   /* OWBM One Wire Data register: [02h] */
+   {
+    "OWD", OWBM, 0x14, 0x14 | MOD3, Reg_8W, MAX},
+   /* -------- The Serial I/O module SER -------- */
+   /* UART registers */
+   /* Serial Port Control Register : SER[6h] */
+   {
+    "SCON1", SER1, 0x6, 0x60 | MOD3, Reg_8W, MAX},
+   /* Serial Data Buffer Register : SER[7h] */
+   {
+    "SBUF1", SER1, 0x7, 0x70 | MOD3, Reg_8W, MAX},
+   /* Serial Port Mode Register : SER[4h] */
+   {
+    "SMD1", SER1, 0x8, 0x80 | MOD3, Reg_8W, MAX},
+   /* Serial Port Phase Register : SER[4h] */
+   {
+    "PR1", SER1, 0x9, 0x90 | MOD3, Reg_16W, MAX},
+   /* -------- Timer/Counter 2 Module -------- */
+   /* Timer 2 configuration Register : TC[3h] */
+   {
+    "T2CNA0", TIMER20, 0x0, 0x00 | MOD3, Reg_8W, MAX},
+   {
+    "T2H0", TIMER20, 0x1, 0x10 | MOD3, Reg_8W, MAX},
+   {
+    "T2RH0", TIMER20, 0x2, 0x20 | MOD3, Reg_8W, MAX},
+   {
+    "T2CH0", TIMER20, 0x3, 0x30 | MOD3, Reg_8W, MAX},
+   {
+    "T2CNB0", TIMER20, 0xc, 0xc0 | MOD3, Reg_8W, MAX},
+   {
+    "T2V0", TIMER20, 0xd, 0xd0 | MOD3, Reg_16W, MAX},
+   {
+    "T2R0", TIMER20, 0xe, 0xe0 | MOD3, Reg_16W, MAX},
+   {
+    "T2C0", TIMER20, 0xf, 0xf0 | MOD3, Reg_16W, MAX},
+   {
+    "T2CFG0", TIMER20, 0x10, 0x10 | MOD3, Reg_8W, MAX},
+   /* Timer 2-1 configuration Register : TC[4h] */
+ 
+   {
+    "T2CNA1", TIMER21, 0x0, 0x00 | MOD4, Reg_8W, MAX},
+   {
+    "T2H1", TIMER21, 0x1, 0x10 | MOD4, Reg_8W, MAX},
+   {
+    "T2RH1", TIMER21, 0x2, 0x20 | MOD4, Reg_8W, MAX},
+   {
+    "T2CH1", TIMER21, 0x3, 0x30 | MOD4, Reg_8W, MAX},
+   {
+    "T2CNA2", TIMER21, 0x4, 0x40 | MOD4, Reg_8W, MAX},
+   {
+    "T2H2", TIMER21, 0x5, 0x50 | MOD4, Reg_8W, MAX},
+   {
+    "T2RH2", TIMER21, 0x6, 0x60 | MOD4, Reg_8W, MAX},
+   {
+    "T2CH2", TIMER21, 0x7, 0x70 | MOD4, Reg_8W, MAX},
+   {
+    "T2CNB1", TIMER21, 0x8, 0x80 | MOD4, Reg_8W, MAX},
+   {
+    "T2V1", TIMER21, 0x9, 0x90 | MOD4, Reg_16W, MAX},
+   {
+    "T2R1", TIMER21, 0xa, 0xa0 | MOD4, Reg_16W, MAX},
+   {
+    "T2C1", TIMER21, 0xb, 0xb0 | MOD4, Reg_16W, MAX},
+   {
+    "T2CNB2", TIMER21, 0xc, 0xc0 | MOD4, Reg_8W, MAX},
+   {
+    "T2V2", TIMER21, 0xd, 0xd0 | MOD4, Reg_16W, MAX},
+   {
+    "T2R2", TIMER21, 0xe, 0xe0 | MOD4, Reg_16W, MAX},
+   {
+    "T2C2", TIMER21, 0xf, 0xf0 | MOD4, Reg_16W, MAX},
+   {
+    "T2CFG1", TIMER21, 0x10, 0x10 | MOD4, Reg_8W, MAX},
+   {
+    "T2CFG2", TIMER21, 0x11, 0x11 | MOD4, Reg_8W, MAX},
+   {
+    NULL, 0, 0, 0, 0, 0}
+ };
+ 
+ /* Memory access argument */
+ struct mem_access
+ {
+   char *name;			/* Name of the Memory access operand */
+   int opcode;			/* Its corresponding opcode */
+ };
+ typedef struct mem_access mem_access;
+ 
+ /* The Memory table for accessing the data memory through particular
+    registers */
+ struct mem_access mem_table[] = {
+   /* The Pop Operation on the stack */
+   {"@SP--", 0x0d},
+   /* Data Pointer 0 */
+   {"@DP[0]", 0x0f},
+   /* Data Ponter 1 */
+   {"@DP[1]", 0x4f},
+   /* Data Pointer 0 post increment */
+   {"@DP[0]++", 0x1f},
+   /* Data Pointer 1 post increment */
+   {"@DP[1]++", 0x5f},
+   /* Data Pointer 0 post decrement */
+   {"@DP[0]--", 0x2f},
+   /* Data Pointer 1 post decrement */
+   {"@DP[1]--", 0x6f},
+   /* ADDED According to New Specification */
+ 
+   {"@BP[OFFS]", 0x0E},
+   {"@BP[OFFS++]", 0x1E},
+   {"@BP[OFFS--]", 0x2E},
+   {"NUL", 0x76},
+   {"@++SP", 0x0D},
+   {"@BP[++OFFS]", 0x1E},
+   {"@BP[--OFFS]", 0x2E},
+   {"@++DP[0]", 0x1F},
+   {"@++DP[1]", 0x5F}, {"@--DP[0]", 0x2F}, {"@--DP[1]", 0x6F}
+ };
+ 
+ /* Register bit argument */
+ struct reg_bit
+ {
+   reg_entry *reg;
+   int bit;
+ };
+ typedef struct reg_bit reg_bit;
+ 
+ /* There are certain names given to particular bits of some registers. These 
+    will be taken care of here */
+ struct bit_name
+ {
+   char *name;
+   char *reg_bit;
+ };
+ typedef struct bit_name bit_name;
+ bit_name bit_table[] = {
+ 
+   {
+    "RI", "SCON.0"},
+   /* FOr APC */
+   {
+    "MOD0", "APC.0"},
+   {
+    "MOD1", "APC.1"},
+   {
+    "MOD2", "APC.2"},
+   {
+    "IDS", "APC.6"},
+   {
+    "CLR", "APC.6"},
+   /* For PSF */
+   {
+    "E", "PSF.0"},
+   {
+    "C", "PSF.1"},
+   {
+    "OV", "PSF.2"},
+   {
+    "S", "PSF.6"},
+   {
+    "Z", "PSF.7"},
+   /* For IC */
+ 
+   {
+    "IGE", "IC.0"},
+   {
+    "INS", "IC.1"},
+   {
+    "CGDS", "IC.5"},
+   /* For IMR */
+ 
+   {
+    "IM0", "IMR.0"},
+   {
+    "IM1", "IMR.1"},
+   {
+    "IM2", "IMR.2"},
+   {
+    "IM3", "IMR.3"},
+   {
+    "IM4", "IMR.4"},
+   {
+    "IM5", "IMR.5"},
+   {
+    "IMS", "IMR.7"},
+   /* For SC */
+   {
+    "PWL", "SC.1"},
+   {
+    "ROD", "SC.2"},
+   {
+    "UPA", "SC.3"},
+   {
+    "CDA0", "SC.4"},
+   {
+    "CDA1", "SC.5"},
+   /* For IIR */
+ 
+   {
+    "II0", "IIR.0"},
+   {
+    "II1", "IIR.1"},
+   {
+    "II2", "IIR.2"},
+   {
+    "II3", "IIR.3"},
+   {
+    "II4", "IIR.4"},
+   {
+    "II5", "IIR.5"},
+   {
+    "IIS", "IIR.7"},
+   /* For CKCN */
+ 
+   {
+    "CD0", "CKCN.0"},
+   {
+    "CD1", "CKCN.1"},
+   {
+    "PMME", "CKCN.2"},
+   {
+    "SWB", "CKCN.3"},
+   {
+    "STOP", "CKCN.4"},
+   {
+    "RGMD", "CKCN.5"},
+   {
+    "RGSL", "CKCN.6"},
+   /* For WDCN */
+ 
+   {
+    "RWT", "WDCN.0"},
+   {
+    "EWT", "WDCN.1"},
+   {
+    "WTRF", "WDCN.2"},
+   {
+    "WDIF", "WDCN.3"},
+   {
+    "WD0", "WDCN.4"},
+   {
+    "WD1", "WDCN.5"},
+   {
+    "EWDI", "WDCN.6"},
+   {
+    "POR", "WDCN.7"},
+   /* For DPC */
+ 
+   {
+    "DPS0", "DPC.0"},
+   {
+    "DPS1", "DPC.1"},
+   {
+    "WBS0", "DPC.2"},
+   {
+    "WBS1", "DPC.3"},
+   {
+    "WBS2", "DPC.4"},
+ 
+    /* For SCON */  
+   {
+    "TI", "SCON.1"},
+   {
+    "RB8", "SCON.2"},
+   {
+    "TB8", "SCON.3"},
+   {
+    "REN", "SCON.4"},
+   {
+    "SM2", "SCON.5"},
+   {
+    "SM1", "SCON.6"},
+   {
+    "SM0", "SCON.7"},
+   {
+    "FE", "SCON.7"}
+ };
+ const char *LSInstr[] =
+   { "LJUMP", "SJUMP", "LDJNZ", "SDJNZ", "LCALL", "SCALL", "JUMP",
+   "DJNZ", "CALL", NULL
+ };
+ typedef enum
+ { DST, SRC, BOTH,
+ }
+ type1;
+ struct mem_access_syntax
+ {
+   char name[12];		/* Name of the Memory access operand */
+   type1 type;
+   char *invalid_op[5];
+ };
+ typedef struct mem_access_syntax mem_access_syntax;
+ 
+ /* The Memory Access table for accessing the data memory through particular
+    registers */
+ mem_access_syntax mem_access_syntax_table[] = {
+ 
+   {
+    "@SP--", SRC,
+    {
+     NULL, NULL, NULL, NULL, NULL}},
+   /* Data Pointer 0 */
+   {
+    "@DP[0]", BOTH,
+    {
+     "@DP[0]--", "@DP[0]++", NULL, NULL, NULL}},
+   /* Data Ponter 1 */
+   {
+    "@DP[1]", BOTH,
+    {
+     "@DP[1]--", "@DP[1]++", NULL, NULL, NULL}},
+   /* Data Pointer 0 post increment */
+   {
+    "@DP[0]++", SRC,
+    {
+     NULL, NULL, NULL, NULL, NULL}},
+   /* Data Pointer 1 post increment */
+   {
+    "@DP[1]++", SRC,
+    {
+     NULL, NULL, NULL, NULL, NULL}},
+   /* Data Pointer 0 post decrement */
+   {
+    "@DP[0]--", SRC,
+    {
+     NULL, NULL, NULL, NULL, NULL}},
+   /* Data Pointer 1 post decrement */
+   {
+    "@DP[1]--", SRC,
+    {
+     NULL, NULL, NULL, NULL, NULL}},
+   /* ADDED According to New Specification */
+ 
+   {
+    "@BP[OFFS]", BOTH,
+    {
+     "@BP[OFFS++]", "@BP[OFFS--]", NULL, NULL, NULL}},
+   {
+    "@BP[OFFS++]", SRC,
+    {
+     NULL, NULL, NULL, NULL, NULL}},
+   {
+    "@BP[OFFS--]", SRC,
+    {
+     NULL, NULL, NULL, NULL, NULL}},
+   {
+    "NUL", DST,
+    {
+     NULL, NULL, NULL, NULL, NULL}},
+   {
+    "@++SP", DST,
+    {
+     NULL, NULL, NULL, NULL, NULL}},
+   {
+    "@BP[++OFFS]", DST,
+    {
+     "@BP[OFFS--]", "@BP[OFFS++]", NULL, NULL, NULL}},
+   {
+    "@BP[--OFFS]", DST,
+    {
+     "@BP[OFFS--]", "@BP[OFFS++]", NULL, NULL, NULL}},
+   {
+    "@++DP[0]", DST,
+    {
+     "@DP[0]--", "@DP[0]++", NULL, NULL, NULL}},
+   {
+    "@++DP[1]", DST,
+    {
+     "@DP[1]--", "@DP[1]++", NULL, NULL, NULL}},
+   {
+    "@--DP[0]", DST,
+    {
+     "@DP[0]++", "@DP[0]--", NULL, NULL, NULL}},
+   {
+    "@--DP[1]", DST,
+    {
+     "@DP[1]++", "@DP[1]--", NULL, NULL, NULL}}
+ };
+ 
+ #endif /* */
Index: ld/Makefile.in
===================================================================
RCS file: /cvs/src/src/ld/Makefile.in,v
retrieving revision 1.161.6.1
diff -c -3 -p -r1.161.6.1 Makefile.in
*** ld/Makefile.in	8 Apr 2004 15:02:12 -0000	1.161.6.1
--- ld/Makefile.in	2 Nov 2004 13:51:44 -0000
*************** ALL_EMULATIONS = \
*** 362,367 ****
--- 362,368 ----
  	em68knbsd.o \
  	em68kpsos.o \
  	em88kbcs.o \
+ 	emaxqcoff.o \
  	emcorepe.o \
  	emipsbig.o \
  	emipsbsd.o \
*************** em68kpsos.c:	$(srcdir)/emulparams/m68kps
*** 1748,1753 ****
--- 1749,1757 ----
  em88kbcs.c: $(srcdir)/emulparams/m88kbcs.sh \
    $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/m88kbcs.sc ${GEN_DEPENDS}
  	${GENSCRIPTS} m88kbcs "$(tdir_m88kbcs)"
+ emaxqcoff.c: $(srcdir)/emulparams/maxqcoff.sh \
+   $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/maxqcoff.sc ${GEN_DEPENDS}
+ 	${GENSCRIPTS} maxqcoff "$(tdir_maxqcoff)"
  emcorepe.c: $(srcdir)/emulparams/mcorepe.sh \
    $(srcdir)/emultempl/pe.em $(srcdir)/scripttempl/pe.sc ${GEN_DEPENDS}
  	${GENSCRIPTS} mcorepe "$(tdir_mcorepe)"
Index: ld/configure.tgt
===================================================================
RCS file: /cvs/src/src/ld/configure.tgt,v
retrieving revision 1.144.6.3
diff -c -3 -p -r1.144.6.3 configure.tgt
*** ld/configure.tgt	17 May 2004 16:16:41 -0000	1.144.6.3
--- ld/configure.tgt	2 Nov 2004 13:51:44 -0000
*************** m68*-sun-sunos[34]*)	targ_emul=sun3 ;;
*** 127,132 ****
--- 127,135 ----
  m68*-wrs-vxworks*)	targ_emul=sun3 ;;
  m68*-ericsson-ose)	targ_emul=sun3 ;;
  m68*-apple-aux*)	targ_emul=m68kaux ;;
+ maxq-*-coff)            targ_emul=maxqcoff;;
+ maxq-*-ihex)            targ_emul=maxqihex;;
+ 
  *-tandem-none)		targ_emul=st2000 ;;
  i370-*-elf* | i370-*-linux-gnu*) targ_emul=elf32i370 ;;
  i[3-7]86-*-nto-qnx*)	targ_emul=i386nto ;;
Index: ld/emulparams/maxqcoff.sh
===================================================================
RCS file: ld/emulparams/maxqcoff.sh
diff -N ld/emulparams/maxqcoff.sh
*** /dev/null	1 Jan 1970 00:00:00 -0000
--- ld/emulparams/maxqcoff.sh	2 Nov 2004 13:51:44 -0000
***************
*** 0 ****
--- 1,8 ----
+ 
+ OUTPUT_FORMAT="coff-maxq"
+ 
+ SCRIPT_NAME=maxqcoff
+ 
+ ARCH=MAXQ
+ 
+ TEXT_START_ADDR=0x8000
Index: ld/scripttempl/maxqcoff.sc
===================================================================
RCS file: ld/scripttempl/maxqcoff.sc
diff -N ld/scripttempl/maxqcoff.sc
*** /dev/null	1 Jan 1970 00:00:00 -0000
--- ld/scripttempl/maxqcoff.sc	2 Nov 2004 13:51:44 -0000
***************
*** 0 ****
--- 1,43 ----
+ test -z "$ENTRY" && ENTRY=_main
+ cat <<EOF
+ OUTPUT_FORMAT("${OUTPUT_FORMAT}")
+ ${LIB_SEARCH_DIRS}
+ ENTRY(${ENTRY})
+ MEMORY 
+   {
+   rom (rx)  : ORIGIN = 0, LENGTH = 0x7FFE
+   ram (!rx) : org = 0x0A000, l = 0x5FFF
+   }
+ 
+ SECTIONS
+ {
+ 	.text  ${RELOCATING+ 0x0000}: 
+ 	{
+ 		*(.text) 
+ 	} >rom
+ 
+ 	.data ${RELOCATING}: 
+ 	{ 
+ 		*(.data)  
+ 		*(.rodata)
+ 		*(.bss)
+ 		*(COMMON)
+ 		${RELOCATING+ edata  =  .};
+ 	}>ram
+ 
+ /*	.bss ${RELOCATING+ SIZEOF(.data) + 0x0000}  :
+ 	{ 
+ 		*(.bss)  
+ 		*(COMMON)
+ 	}
+ */
+ 	.stab  0 ${RELOCATING+(NOLOAD)} :
+ 	{
+ 		[ .stab ]
+ 	}
+ 	.stabstr  0 ${RELOCATING+(NOLOAD)} :
+ 	{
+ 		[ .stabstr ]
+ 	}
+ }
+ EOF
Index: opcodes/configure
===================================================================
RCS file: /cvs/src/src/opcodes/configure,v
retrieving revision 1.59
diff -c -3 -p -r1.59 configure
*** opcodes/configure	5 Aug 2003 09:39:31 -0000	1.59
--- opcodes/configure	2 Nov 2004 13:51:46 -0000
*************** if test x${all_targets} = xfalse ; then
*** 4655,4660 ****
--- 4655,4661 ----
  	bfd_m68hc12_arch)	ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;;
  	bfd_m68k_arch)		ta="$ta m68k-dis.lo m68k-opc.lo" ;;
  	bfd_m88k_arch)		ta="$ta m88k-dis.lo" ;;
+         bfd_maxq_arch)         ta="$ta maxq-dis.lo" ;;
  	bfd_mcore_arch)		ta="$ta mcore-dis.lo" ;;
  	bfd_mips_arch)		ta="$ta mips-dis.lo mips-opc.lo mips16-opc.lo" ;;
  	bfd_mmix_arch)		ta="$ta mmix-dis.lo mmix-opc.lo" ;;
Index: opcodes/configure.in
===================================================================
RCS file: /cvs/src/src/opcodes/configure.in,v
retrieving revision 1.47
diff -c -3 -p -r1.47 configure.in
*** opcodes/configure.in	5 Aug 2003 09:39:31 -0000	1.47
--- opcodes/configure.in	2 Nov 2004 13:51:46 -0000
*************** if test x${all_targets} = xfalse ; then
*** 196,201 ****
--- 196,202 ----
  	bfd_m68hc12_arch)	ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;;
  	bfd_m68k_arch)		ta="$ta m68k-dis.lo m68k-opc.lo" ;;
  	bfd_m88k_arch)		ta="$ta m88k-dis.lo" ;;
+ 	 bfd_maxq_arch)         ta="$ta maxq-dis.lo" ;;
  	bfd_mcore_arch)		ta="$ta mcore-dis.lo" ;;
  	bfd_mips_arch)		ta="$ta mips-dis.lo mips-opc.lo mips16-opc.lo" ;;
  	bfd_mmix_arch)		ta="$ta mmix-dis.lo mmix-opc.lo" ;;
Index: opcodes/disassemble.c
===================================================================
RCS file: /cvs/src/src/opcodes/disassemble.c,v
retrieving revision 1.45
diff -c -3 -p -r1.45 disassemble.c
*** opcodes/disassemble.c	14 Nov 2003 15:12:44 -0000	1.45
--- opcodes/disassemble.c	2 Nov 2004 13:51:46 -0000
*************** Foundation, Inc., 59 Temple Place - Suit
*** 45,50 ****
--- 45,51 ----
  #define ARCH_m68hc12
  #define ARCH_m88k
  #define ARCH_mcore
+ #define ARCH_maxq
  #define ARCH_mips
  #define ARCH_mmix
  #define ARCH_mn10200
*************** disassembler (abfd)
*** 230,235 ****
--- 231,241 ----
        disassemble = print_insn_ns32k;
        break;
  #endif
+ #ifdef ARCH_maxq
+     case bfd_arch_maxq:
+       disassemble = print_insn_maxq_little;
+       break;
+ #endif
  #ifdef ARCH_mcore
      case bfd_arch_mcore:
        disassemble = print_insn_mcore;
Index: opcodes/maxq-dis.c
===================================================================
RCS file: opcodes/maxq-dis.c
diff -N opcodes/maxq-dis.c
*** /dev/null	1 Jan 1970 00:00:00 -0000
--- opcodes/maxq-dis.c	2 Nov 2004 13:51:46 -0000
***************
*** 0 ****
--- 1,889 ----
+ /* Instruction printing code for the MAXQ Copyright 2003, 2004, 2005 Free
+    Software Foundation, Inc.
+ 
+    Written by Vineet Sharma(vineets@noida.hcltech.com) Inderpreet
+    S.(inderpreetb@noida.hcltech.com)
+ 
+    This file is part of GDB.
+ 
+    This program is free software; you can redistribute it and/or modify it
+    under the terms of the GNU General Public License as published by the Free 
+    Software Foundation; either version 2 of the License, or (at your option)
+    any later version.
+ 
+    This program is distributed in the hope that it will be useful, but
+    WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 
+    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+    for more details.
+ 
+    You should have received a copy of the GNU General Public License along
+    with this program; if not, write to the Free Software Foundation, Inc., 59 
+    Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+ 
+ #include "sysdep.h"
+ #include "dis-asm.h"
+ #include "opcode/maxq.h"
+ 
+ #ifndef boolean
+ #define boolean int
+ #endif
+ 
+ #ifndef true
+ #define true (1==1)
+ #endif
+ 
+ #ifndef false
+ #define false (0==1)
+ #endif
+ 
+ struct _group_info
+ {
+   unsigned char group_no;
+   unsigned char sub_opcode;
+   unsigned char src;
+   unsigned char dst;
+   unsigned char fbit;
+   unsigned char bit_no;
+   unsigned char flag;
+ 
+ };
+ 
+ typedef struct _group_info group_info;
+ 
+ #define SRC	0x01
+ #define DST	0x02
+ #define FORMAT	0x04
+ #define BIT_NO	0x08
+ #define SUB_OP	0x10
+ 
+ #define MASK_LOW_BYTE 0x0f
+ #define MASK_HIGH_BYTE 0xf0
+ 
+ /* Flags for retrieving the bits from the op-code */
+ #define _DECODE_LOWNIB_LOWBYTE  0x000f
+ #define _DECODE_HIGHNIB_LOWBYTE 0x00f0
+ #define _DECODE_LOWNIB_HIGHBYTE 0x0f00
+ #define _DECODE_HIGHNIB_HIGHBYTE 0xf000
+ #define _DECODE_HIGHBYTE 0xff00
+ #define _DECODE_LOWBYTE  0x00ff
+ #define _DECODE_4TO6_HIGHBYTE 0x7000
+ #define _DECODE_4TO6_LOWBYTE 0x0070
+ #define _DECODE_0TO6_HIGHBYTE 0x7f00
+ #define _DECODE_0TO2_HIGHBYTE 0x0700
+ #define _DECODE_GET_F_HIGHBYTE 0x8000
+ #define _DECODE_BIT7_HIGHBYTE 0x8000
+ #define _DECODE_BIT7_LOWBYTE 0x0080
+ #define _DECODE_GET_CARRY 0x10000
+ #define _DECODE_BIT0_LOWBYTE 0x1
+ #define _DECODE_BIT6AND7_HIGHBYTE 0xc000
+ 
+ /* Module and Register Indexed of System Registers */
+ #define _CURR_ACC_MODINDEX 0xa
+ #define _CURR_ACC_REGINDEX 0x0
+ #define _PSF_REG_MODINDEX  0x8
+ #define _PSF_REG_REGINDEX  0x4
+ #define _PFX_REG_MODINDEX  0xb
+ #define _PFX0_REG_REGINDEX 0x0
+ #define _PFX2_REG_REGINDEX 0x2
+ #define _DP_REG_MODINDEX   0xf
+ #define _DP0_REG_REGINDEX  0x3
+ #define _DP1_REG_REGINDEX  0x7
+ #define _IP_REG_MODINDEX   0xc
+ #define _IP_REG_REGINDEX   0x0
+ #define _IIR_REG_MODINDEX  0x8
+ #define _IIR_REG_REGINDEX  0xb
+ #define _SP_REG_MODINDEX   0xd
+ #define _SP_REG_REGINDEX   0x1
+ #define _IC_REG_MODINDEX   0x8
+ #define _IC_REG_REGINDEX   0x5
+ #define _LC_REG_MODINDEX   0xe
+ #define _LC0_REG_REGINDEX  0x0
+ #define _LC1_REG_REGINDEX  0x1
+ #define _LC2_REG_REGINDEX  0x2
+ #define _LC3_REG_REGINDEX  0x3
+ 
+ /* Flags for finding the bits in PSF Register */
+ #define SIM_ALU_DECODE_CARRY_BIT_POS  0x2
+ #define SIM_ALU_DECODE_SIGN_BIT_POS   0x40
+ #define SIM_ALU_DECODE_ZERO_BIT_POS   0x80
+ #define SIM_ALU_DECODE_EQUAL_BIT_POS  0x1
+ #define SIM_ALU_DECODE_IGE_BIT_POS    0x1
+ 
+ /* Number Of Op-code Groups */
+ unsigned char const SIM_ALU_DECODE_OPCODE_GROUPS = 11;
+ 
+ /* Op-code Groups */
+ unsigned char const SIM_ALU_DECODE_LOGICAL_XCHG_OP_GROUP = 1;
+ 
+ /* Group1: AND/OR/XOR/ADD/SUB Operations: fxxx 1010 ssss ssss */
+ unsigned char const SIM_ALU_DECODE_AND_OR_ADD_SUB_OP_GROUP = 2;
+ 
+ /* Group2: Logical Operations: 1000 1010 xxxx 1010 */
+ unsigned char const SIM_ALU_DECODE_BIT_OP_GROUP = 3;
+ 
+ /* XCHG/Bit Operations: 1xxx 1010 xxxx 1010 */
+ unsigned char const SIM_ALU_DECODE_SET_DEST_BIT_GROUP = 4;
+ 
+ /* Move value in bit of destination register: 1ddd dddd xbbb 0111 */
+ unsigned char const SIM_ALU_DECODE_JUMP_OP_GROUP = 5;
+ 
+ #define JUMP_CHECK(insn)   (((insn &  _DECODE_4TO6_HIGHBYTE)==0x0000) || \
+ 			   ((insn &  _DECODE_4TO6_HIGHBYTE)==0x2000) ||  \
+ 			   ((insn &  _DECODE_4TO6_HIGHBYTE)==0x6000) ||  \
+ 			   ((insn &  _DECODE_4TO6_HIGHBYTE)==0x1000) ||  \
+                            ((insn &  _DECODE_4TO6_HIGHBYTE)==0x5000) ||  \
+ 			   ((insn &  _DECODE_4TO6_HIGHBYTE)==0x3000) ||  \
+ 			   ((insn &  _DECODE_4TO6_HIGHBYTE)==0x7000) ||  \
+ 			   ((insn &  _DECODE_4TO6_HIGHBYTE)==0x4000))
+ 
+ /* JUMP operations: fxxx 1100 ssss ssss */
+ unsigned char const SIM_ALU_DECODE_RET_OP_GROUP = 6;
+ 
+ /* RET Operations: 1xxx 1100 0000 1101 */
+ unsigned char const SIM_ALU_DECODE_MOVE_SRC_DST_GROUP = 7;
+ 
+ /* Move src into dest register: fddd dddd ssss ssss */
+ unsigned char const SIM_ALU_DECODE_SET_SRC_BIT_GROUP = 8;
+ 
+ /* Move value in bit of source register: fbbb 0111 ssss ssss */
+ unsigned char const SIM_ALU_DECODE_DJNZ_CALL_PUSH_OP_GROUP = 9;
+ 
+ /* PUSH, DJNZ and CALL operations: fxxx 1101 ssss ssss */
+ unsigned char const SIM_ALU_DECODE_POP_OP_GROUP = 10;
+ 
+ /* POP operation: 1ddd dddd 0000 1101 */
+ unsigned char const SIM_ALU_DECODE_CMP_SRC_OP_GROUP = 11;
+ 
+ /* GLOBAL */
+ unsigned char unres_reg_name[20];
+ 
+ static int print_insn
+ PARAMS ((bfd_vma, struct disassemble_info *, enum bfd_endian));
+ int print_insn_maxq_little PARAMS ((bfd_vma, struct disassemble_info *));
+ 
+ static boolean check_move PARAMS ((unsigned char, unsigned char));
+ static unsigned char *get_reg_name PARAMS ((unsigned char reg_code, type1));
+ static void get_insn_opcode PARAMS ((const unsigned int, group_info *));
+ static unsigned char get_group PARAMS ((const unsigned int));
+ 
+ static unsigned char *
+ get_reg_name (reg_code, arg_pos)
+      unsigned char reg_code;
+      type1 arg_pos;
+ {
+   unsigned char module;
+   unsigned char index;
+   int ix = 0;
+   reg_entry const *reg_x;
+   mem_access_syntax const *syntax;
+   mem_access *mem_acc;
+ 
+   module = 0;
+   index = 0;
+   module = (reg_code & MASK_LOW_BYTE);
+   index = (reg_code & MASK_HIGH_BYTE);
+   index = index >> 4;
+ 
+   /* search the system register table */
+   for (reg_x = &system_reg_table[0]; reg_x->reg_name != NULL; ++reg_x)
+     {
+       if ((reg_x->Mod_name == module) && (reg_x->Mod_index == index))
+ 	{
+ 	  return reg_x->reg_name;
+ 	}
+     }
+ 
+   /* serch pheripheral table */
+   for (ix = 0; ix < num_of_reg; ix++)
+     {
+       reg_x = &new_reg_table[ix];
+       if ((reg_x->Mod_name == module) && (reg_x->Mod_index == index))
+ 	{
+ 	  return reg_x->reg_name;
+ 	}
+     }
+ 
+   for (mem_acc = &mem_table[0]; mem_acc->name != NULL || !mem_acc; ++mem_acc)
+     {
+       if (reg_code == mem_acc->opcode)
+ 	{
+ 	  for (syntax = &mem_access_syntax_table;
+ 	       mem_access_syntax_table != NULL
+ 	       || mem_access_syntax_table->name; ++syntax)
+ 	    if (!strcmp (mem_acc->name, syntax->name))
+ 	      {
+ 		if ((arg_pos == syntax->type) || (syntax->type == BOTH))
+ 		  {
+ 		    return mem_acc->name;
+ 		  }
+ 		else
+ 		  break;
+ 	      }
+ 	}
+     }
+ 
+   memset (unres_reg_name, 0, 20);
+   sprintf (unres_reg_name, "%01x%01xh", index, module);
+ 
+   return unres_reg_name;
+ }
+ 
+ static boolean
+ check_move (insn0, insn8)
+      unsigned char insn0;
+      unsigned char insn8;
+ {
+ 
+   boolean first = false, second = false;
+   char *first_reg, *second_reg;
+ 
+   reg_entry const *reg_x;
+ 
+   const unsigned char module1 = insn0 & MASK_LOW_BYTE;
+   const unsigned char index1 = ((insn0 & 0x70) >> 4);
+   const unsigned char module2 = insn8 & MASK_LOW_BYTE;
+   const unsigned char index2 = ((insn8 & MASK_HIGH_BYTE) >> 4);
+ 
+   /* DST */
+   if (((insn0 & MASK_LOW_BYTE) == MASK_LOW_BYTE)
+       && ((index1 == 0) || (index1 == 1) || (index1 == 2) || (index1 == 4)
+ 	  || (index1 == 5) || (index1 == 6)))
+     {
+       first = true;
+     }
+   else if (((insn0 & MASK_LOW_BYTE) == 0x0D) && (index1 == 0))
+     {
+       first = true;
+     }
+   else if ((module1 == 0x0E)
+ 	   && ((index1 == 0) || (index1 == 1) || (index1 == 2)))
+     {
+       first = true;
+     }
+   else
+     {
+       for (reg_x = &system_reg_table[0]; reg_x->reg_name != NULL && reg_x;
+ 	   ++reg_x)
+ 	{
+ 	  if ((reg_x->Mod_name == module1) && (reg_x->Mod_index == index1)
+ 	      && ((reg_x->rtype == Reg_16W) || (reg_x->rtype == Reg_8W)))
+ 	    {
+ 	      /* IP not allowed */
+ 	      if ((reg_x->Mod_name == 0x0C) && (reg_x->Mod_index == 0x00))
+ 		continue;
+ 
+ 	      /* A[AP] not allowed */
+ 	      if ((reg_x->Mod_name == 0x0A) && (reg_x->Mod_index == 0x01))
+ 		continue;
+ 	      first_reg = reg_x->reg_name;
+ 	      first = true;
+ 	      break;
+ 	    }
+ 	}
+     }
+ 
+   if (!first)
+     return false;		/* No need to check further */
+ 
+   if (insn0 & 0x80)
+     {
+       /* SRC */
+       if (((insn8 & MASK_LOW_BYTE) == MASK_LOW_BYTE)
+ 	  && ((index2 == 0) || (index2 == 1) || (index2 == 2) || (index2 == 4)
+ 	      || (index2 == 5) || (index2 == 6)))
+ 	{
+ 	  second = true;
+ 	}
+       else if (((insn8 & MASK_LOW_BYTE) == 0x0D) && (index2 == 0))
+ 	{
+ 	  second = true;
+ 	}
+       else if ((module2 == 0x0E)
+ 	       && ((index2 == 0) || (index2 == 1) || (index2 == 2)))
+ 	{
+ 	  second = true;
+ 	}
+ 
+       else
+ 	{
+ 	  for (reg_x = &system_reg_table[0]; reg_x->reg_name != NULL && reg_x;
+ 	       ++reg_x)
+ 	    {
+ 	      if ((reg_x->Mod_name == (insn8 & MASK_LOW_BYTE))
+ 		  && (reg_x->Mod_index == (((insn8 & 0xf0) >> 4))))
+ 		{
+ 		  second = true;
+ 		  second_reg = reg_x->reg_name;
+ 		  break;
+ 		}
+ 	    }
+ 	}	
+ 
+       if (second)
+ 	{
+ 	  if ((module1 == 0x0A && index1 == 0x0)
+ 	      && (module2 == 0x0A && index2 == 0x01))
+ 	    return false;
+ 
+ 	  return true;
+ 	}
+       else
+ 	return false;
+ 
+     }
+   if (first == true)
+     return true;		/* First is true and Second is false */
+   else
+     return false;
+ }
+ 
+ int
+ print_insn_maxq_little (memaddr, info)
+      bfd_vma memaddr;
+      struct disassemble_info *info;
+ {
+   return print_insn (memaddr, info, BFD_ENDIAN_LITTLE);
+ }
+ 
+ /* Print one instruction from MEMADDR on INFO->STREAM. Return the size of the 
+    instruction (always 2 on MAXQ20).  */
+ 
+ static int
+ print_insn (memaddr, info, endianess)
+      bfd_vma memaddr;
+      struct disassemble_info *info;
+      enum bfd_endian endianess;
+ {
+   /* The raw instruction.  */
+   unsigned char insn[2], insn0, insn8, derived_code;
+   unsigned int format;
+   unsigned int actual_operands;
+   unsigned int i;
+   /* The group_info collected/decoded */
+   group_info grp;
+ 
+   MAXQ20_OPCODE_INFO const *opcode;
+ 
+   format = 0;
+ 
+   {
+     /* READ THE OPCODE AND DECIDE THE NO OF OPERANDS */
+     int status =
+       (*info->read_memory_func) (memaddr, (bfd_byte *) & insn[0], 2, info);
+ 
+     if (status != 0)
+       {
+ 	(*info->memory_error_func) (status, memaddr, info);
+ 	return -1;
+       }
+   }
+ 
+   insn8 = insn[1];
+   insn0 = insn[0];
+ 
+   /* FIXME: Endianness always little */
+   if (endianess == BFD_ENDIAN_BIG)
+     get_insn_opcode (((insn[0] << 8) | (insn[1])), &grp);
+ 
+   else
+     get_insn_opcode (((insn[1] << 8) | (insn[0])), &grp);
+ 
+   derived_code = ((grp.group_no << 4) | grp.sub_opcode);
+ 
+   if (insn[0] == 0 && insn[1] == 0)
+     {
+       (*info->fprintf_func) (info->stream, "00 00");
+       return 2;
+     }
+ 
+   /* The opcode is always in insn0 */
+   for (opcode = &op_table[0]; opcode->name != NULL; ++opcode)
+     {
+       if (opcode->instr_id == derived_code)
+ 	{
+ 
+ 	  if (opcode->instr_id == 0x3D)
+ 	    {
+ 
+ 	      if ((grp.bit_no == 0) && (opcode->arg[1] != A_BIT_0))
+ 		continue;
+ 	      if ((grp.bit_no == 1) && (opcode->arg[1] != A_BIT_1))
+ 		continue;
+ 	      if ((grp.bit_no == 3) && (opcode->arg[0] != 0))
+ 		continue;
+ 	    }
+ 
+ 	  (*info->fprintf_func) (info->stream, "%s ", opcode->name);
+ 
+ 	  actual_operands = 0;
+ 
+ 	  if ((grp.flag & SRC) == SRC)
+ 	    actual_operands++;
+ 
+ 	  if ((grp.flag & DST) == DST)
+ 	    actual_operands++;
+ 
+ 	  /* If Implict FLAG in the Instruction */
+ 	  if ((opcode->op_number > actual_operands)
+ 	      && !((grp.flag & SRC) == SRC) && !((grp.flag & DST) == DST))
+ 	    {
+ 	      for (i = 0; i < opcode->op_number; i++)
+ 		{
+ 		  if (i == 1 && (opcode->arg[1] != NULL))
+ 		    (*info->fprintf_func) (info->stream, ",");
+ 		  switch (opcode->arg[i])
+ 		    {
+ 		    case FLAG_C:
+ 		      (*info->fprintf_func) (info->stream, "C");
+ 		      break;
+ 		    case FLAG_NC:
+ 		      (*info->fprintf_func) (info->stream, "NC");
+ 		      break;
+ 
+ 		    case FLAG_Z:
+ 		      (*info->fprintf_func) (info->stream, "Z");
+ 		      break;
+ 
+ 		    case FLAG_NZ:
+ 		      (*info->fprintf_func) (info->stream, "NZ");
+ 		      break;
+ 
+ 		    case FLAG_S:
+ 		      (*info->fprintf_func) (info->stream, "S");
+ 		      break;
+ 
+ 		    case FLAG_E:
+ 		      (*info->fprintf_func) (info->stream, "E");
+ 		      break;
+ 
+ 		    case FLAG_NE:
+ 		      (*info->fprintf_func) (info->stream, "NE");
+ 		      break;
+ 
+ 		    case ACC_BIT:
+ 		      (*info->fprintf_func) (info->stream, "Acc");
+ 		      if ((grp.flag & BIT_NO) == BIT_NO)
+ 			(*info->fprintf_func) (info->stream, ".%d",
+ 					       grp.bit_no);
+ 		      break;
+ 
+ 		    case A_BIT_0:
+ 		      (*info->fprintf_func) (info->stream, "#0");
+ 		      break;
+ 
+ 		    case A_BIT_1:
+ 		      (*info->fprintf_func) (info->stream, "#1");
+ 		      break;
+ 
+ 		    default:
+ 		      break;
+ 		    }
+ 		}		// No of arguments
+ 	    }
+ 
+ 	  /* DST is ABSENT in the grp */
+ 	  if ((opcode->op_number > actual_operands)
+ 	      && ((grp.flag & SRC) == SRC))
+ 	    {
+ 	      switch (opcode->arg[0])
+ 		{
+ 		case FLAG_C:
+ 		  (*info->fprintf_func) (info->stream, "C ");
+ 		  break;
+ 		case FLAG_NC:
+ 		  (*info->fprintf_func) (info->stream, "NC ");
+ 		  break;
+ 
+ 		case FLAG_Z:
+ 		  (*info->fprintf_func) (info->stream, "Z ");
+ 		  break;
+ 
+ 		case FLAG_NZ:
+ 		  (*info->fprintf_func) (info->stream, "NZ ");
+ 		  break;
+ 
+ 		case FLAG_S:
+ 		  (*info->fprintf_func) (info->stream, "S ");
+ 		  break;
+ 
+ 		case FLAG_E:
+ 		  (*info->fprintf_func) (info->stream, "E ");
+ 		  break;
+ 
+ 		case FLAG_NE:
+ 		  (*info->fprintf_func) (info->stream, "NE ");
+ 		  break;
+ 
+ 		case ACC_BIT:
+ 		  (*info->fprintf_func) (info->stream, "Acc ");
+ 		  if ((grp.flag & BIT_NO) == BIT_NO)
+ 		    (*info->fprintf_func) (info->stream, ".%d", grp.bit_no);
+ 		  break;
+ 
+ 		case A_BIT_0:
+ 		  (*info->fprintf_func) (info->stream, "#0 ");
+ 		  break;
+ 
+ 		case A_BIT_1:
+ 		  (*info->fprintf_func) (info->stream, "#1 ");
+ 
+ 		  break;
+ 		default:
+ 		  break;
+ 		}
+ 
+ 	      if (opcode->instr_id == 0xA4)
+ 		{
+ 		  (*info->fprintf_func) (info->stream, "LC[0]");
+ 		}
+ 
+ 	      if (opcode->instr_id == 0xA5)
+ 		{
+ 		  (*info->fprintf_func) (info->stream, "LC[1]");
+ 		}
+ 
+ 	      if ((grp.flag & SRC) == SRC)
+ 		(*info->fprintf_func) (info->stream, ",");
+ 	    }
+ 	  if ((grp.flag & DST) == DST)
+ 	    {
+ 	      if ((grp.flag & BIT_NO) == BIT_NO)
+ 		{
+ 		  (*info->fprintf_func) (info->stream, " %s.%d",
+ 					 get_reg_name (grp.dst,
+ 						       (type1) 0 /*DST*/),
+ 					 grp.bit_no);
+ 		}
+ 
+ 	      else
+ 		{
+ 		  (*info->fprintf_func) (info->stream, " %s", get_reg_name (grp.dst, (type1) 0	/* DST 
+ 												 */
+ 									    ));
+ 		}
+ 	    }
+ 
+ 	  /* SRC is ABSENT in the grp */
+ 	  if ((opcode->op_number > actual_operands)
+ 	      && ((grp.flag & DST) == DST))
+ 	    {
+ 
+ 	      switch (opcode->arg[1])
+ 		{
+ 
+ 		case FLAG_C:
+ 		  (*info->fprintf_func) (info->stream, ",C ");
+ 		  break;
+ 		case FLAG_NC:
+ 		  (*info->fprintf_func) (info->stream, ",NC ");
+ 		  break;
+ 
+ 		case FLAG_Z:
+ 		  (*info->fprintf_func) (info->stream, ",Z ");
+ 		  break;
+ 
+ 		case FLAG_NZ:
+ 		  (*info->fprintf_func) (info->stream, ",NZ ");
+ 		  break;
+ 
+ 		case FLAG_S:
+ 		  (*info->fprintf_func) (info->stream, ",S ");
+ 		  break;
+ 
+ 		case FLAG_E:
+ 		  (*info->fprintf_func) (info->stream, ",E ");
+ 		  break;
+ 
+ 		case FLAG_NE:
+ 		  (*info->fprintf_func) (info->stream, ",NE ");
+ 		  break;
+ 
+ 		case ACC_BIT:
+ 		  (*info->fprintf_func) (info->stream, ",Acc ");
+ 		  if ((grp.flag & BIT_NO) == BIT_NO)
+ 		    (*info->fprintf_func) (info->stream, ".%d", grp.bit_no);
+ 		  break;
+ 
+ 		case A_BIT_0:
+ 		  (*info->fprintf_func) (info->stream, ",#0 ");
+ 		  break;
+ 
+ 		case A_BIT_1:
+ 		  (*info->fprintf_func) (info->stream, ",#1 ");
+ 
+ 		  break;
+ 
+ 		default:
+ 		  break;
+ 		}
+ 	    }
+ 
+ 	  if ((grp.flag & SRC) == SRC)
+ 	    {
+ 
+ 	      if ((grp.flag & DST) == DST)
+ 		(*info->fprintf_func) (info->stream, ",");
+ 
+ 	      if ((grp.flag & BIT_NO) == BIT_NO)
+ 		{
+ 		  format = opcode->format;
+ 
+ 		  if ((grp.flag & FORMAT) == FORMAT)
+ 		    format = grp.fbit;
+ 		  if (format == 1)
+ 		    (*info->fprintf_func) (info->stream, " %s.%d",
+ 					   get_reg_name (grp.src,
+ 							 (type1) 1 /*SRC*/),
+ 					   grp.bit_no);
+ 		  if (format == 0)
+ 		    (*info->fprintf_func) (info->stream, " #%02xh.%d",
+ 					   (grp.src, SRC), grp.bit_no);
+ 
+ 		}
+ 	      else
+ 		{
+ 
+ 		  format = opcode->format;
+ 
+ 		  if ((grp.flag & FORMAT) == FORMAT)
+ 		    format = grp.fbit;
+ 		  if (format == 1)
+ 		    (*info->fprintf_func) (info->stream, " %s",
+ 					   get_reg_name (grp.src,
+ 							 (type1) 1 /*SRC*/));
+ 		  if (format == 0)
+ 		    (*info->fprintf_func) (info->stream, " #%02xh",
+ 					   (grp.src));
+ 		}
+ 	    }
+ 
+ 	  return 2;
+ 	}
+     }
+   (*info->fprintf_func) (info->stream, "Unable to Decode :  %02x %02x",
+ 			 insn[0], insn[1]);
+ 
+   return 2;			
+ }
+ 
+ #if 0
+ /* Disassemble an MAXQ instruction.  */
+ int
+ print_insn_maxq (memaddr, info)
+      bfd_vma memaddr;
+      struct disassemble_info *info;
+ {
+   return print_insn (memaddr, info);
+ }
+ #endif
+ 
+ unsigned char
+ get_group (insn)
+      const unsigned int insn;
+ {
+   if (check_move ((insn >> 8), (insn & _DECODE_LOWBYTE)))
+     return 8;
+ 
+   if ((insn & _DECODE_LOWNIB_HIGHBYTE) == 0x0A00)
+     {
+ 
+       /* && condition with sec part added on 26 May for resoveing 2 & 3 grp
+          conflict */
+       if (((insn & _DECODE_LOWNIB_LOWBYTE) == 0x000A)
+ 	  && ((insn & _DECODE_GET_F_HIGHBYTE) == 0x8000))
+ 	{
+ 	  if ((insn & _DECODE_HIGHNIB_HIGHBYTE) == 0x8000)
+ 	    return 2;
+ 	  else
+ 	    return 3;
+ 	}
+       else
+ 	{
+ 	  return 1;
+ 	}
+     }
+ 
+   else if ((insn & _DECODE_LOWNIB_HIGHBYTE) == 0x0C00)
+     {
+       if (((insn & _DECODE_LOWBYTE) == 0x000D) && JUMP_CHECK (insn)
+ 	  && ((insn & _DECODE_GET_F_HIGHBYTE) == 0x8000))
+ 	return 6;
+       else if ((insn & _DECODE_LOWBYTE) == 0x008D)
+ 	return 7;
+       else
+ 	return 5;
+     }
+   else if (((insn & _DECODE_LOWNIB_HIGHBYTE) == 0x0D00) &&
+ 	   (((insn & _DECODE_4TO6_HIGHBYTE) == 0x3000) ||
+ 	    ((insn & _DECODE_4TO6_HIGHBYTE) == 0x4000) ||
+ 	    ((insn & _DECODE_4TO6_HIGHBYTE) == 0x5000) ||
+ 	    ((insn & _DECODE_4TO6_HIGHBYTE) == 0x0000)))
+     {
+       return 10;
+ 
+     }
+   else if ((insn & _DECODE_LOWBYTE) == 0x000D)
+     {
+       return 11;
+     }
+   else if ((insn & _DECODE_LOWBYTE) == 0x008D)
+     {
+       return 12;
+     }
+   else if ((insn & _DECODE_0TO6_HIGHBYTE) == 0x7800)
+     {
+       return 13;
+     }
+   else if ((insn & _DECODE_LOWNIB_HIGHBYTE) == 0x0700)
+     {
+       return 9;
+     }
+   else if (((insn & _DECODE_LOWNIB_LOWBYTE) == 0x0007)
+ 	   && ((insn & _DECODE_GET_F_HIGHBYTE) == 0x8000))
+     {
+       return 4;
+     }
+   else
+     {
+       return 8;
+     }
+ }
+ 
+ void
+ get_insn_opcode (insn, i)
+      const unsigned int insn;
+      group_info *i;
+ {
+ 
+   static unsigned char pfx_flag = 0;
+   static unsigned char count_for_pfx = 0;
+ 
+   i->flag ^= i->flag;
+   i->bit_no ^= i->bit_no;
+   i->dst ^= i->dst;
+   i->fbit ^= i->fbit;
+   i->group_no ^= i->group_no;
+   i->src ^= i->src;
+   i->sub_opcode ^= i->sub_opcode;
+ 
+   if (count_for_pfx > 0)
+     count_for_pfx++;
+ 
+   if (((insn >> 8) == 0x0b) || ((insn >> 8) == 0x2b))
+     {
+       pfx_flag = 1;
+       count_for_pfx = 1;
+     }
+ 
+   i->group_no = get_group (insn);
+ 
+   if (pfx_flag && (i->group_no == 0x0D) && (count_for_pfx == 2)
+       && ((insn & _DECODE_0TO6_HIGHBYTE) == 0x7800))
+     {
+       i->group_no = 0x08;
+       count_for_pfx = 0;
+       pfx_flag ^= pfx_flag;
+     }
+ 
+   switch (i->group_no)
+     {
+     case 1:
+       i->sub_opcode = ((insn & _DECODE_4TO6_HIGHBYTE) >> 12);
+       i->flag |= SUB_OP;
+       i->src = ((insn & _DECODE_LOWBYTE));
+       i->flag |= SRC;
+       i->fbit = ((insn & _DECODE_GET_F_HIGHBYTE) >> 15);
+       i->flag |= FORMAT;
+       break;
+ 
+     case 2:
+       i->sub_opcode = ((insn & _DECODE_HIGHNIB_LOWBYTE) >> 4);
+       i->flag |= SUB_OP;
+       break;
+ 
+     case 3:
+       i->sub_opcode = ((insn & _DECODE_HIGHNIB_HIGHBYTE) >> 12);
+       i->flag |= SUB_OP;
+       i->bit_no = ((insn & _DECODE_HIGHNIB_LOWBYTE) >> 4);
+       i->flag |= BIT_NO;
+       break;
+ 
+     case 4:
+       i->sub_opcode = ((insn & _DECODE_BIT7_LOWBYTE) >> 7);
+       i->flag |= SUB_OP;
+       i->dst = ((insn & _DECODE_0TO6_HIGHBYTE) >> 8);
+       i->flag |= DST;
+       i->bit_no = ((insn & _DECODE_4TO6_LOWBYTE) >> 4);
+       i->flag |= BIT_NO;
+       break;
+ 
+     case 5:
+       i->sub_opcode = ((insn & _DECODE_4TO6_HIGHBYTE) >> 12);
+       i->flag |= SUB_OP;
+       i->src = ((insn & _DECODE_LOWBYTE));
+       i->flag |= SRC;
+       i->fbit = ((insn & _DECODE_GET_F_HIGHBYTE) >> 15);
+       i->flag |= FORMAT;
+       break;
+ 
+     case 6:
+       i->sub_opcode = ((insn & _DECODE_HIGHNIB_HIGHBYTE) >> 12);
+       i->flag |= SUB_OP;
+       break;
+ 
+     case 7:
+       i->sub_opcode = ((insn & _DECODE_HIGHNIB_HIGHBYTE) >> 12);
+       i->flag |= SUB_OP;
+       break;
+ 
+     case 8:
+       i->dst = ((insn & _DECODE_0TO6_HIGHBYTE) >> 8);
+       i->flag |= DST;
+       i->src = ((insn & _DECODE_LOWBYTE));
+       i->flag |= SRC;
+       i->fbit = ((insn & _DECODE_GET_F_HIGHBYTE) >> 15);
+       i->flag |= FORMAT;
+       break;
+ 
+     case 9:
+       i->sub_opcode = ((insn & _DECODE_0TO2_HIGHBYTE) >> 8);
+       i->flag |= SUB_OP;
+       i->bit_no = ((insn & _DECODE_4TO6_HIGHBYTE) >> 12);
+       i->flag |= BIT_NO;
+       i->fbit = ((insn & _DECODE_GET_F_HIGHBYTE) >> 15);
+       i->flag |= FORMAT;
+       i->src = ((insn & _DECODE_LOWBYTE));
+       i->flag |= SRC;
+       break;
+ 
+     case 10:
+       i->sub_opcode = ((insn & _DECODE_4TO6_HIGHBYTE) >> 12);
+       i->flag |= SUB_OP;
+       i->src = ((insn & _DECODE_LOWBYTE));
+       i->flag |= SRC;
+       i->fbit = ((insn & _DECODE_GET_F_HIGHBYTE) >> 15);
+       i->flag |= FORMAT;
+       break;
+ 
+     case 11:
+       i->dst = ((insn & _DECODE_0TO6_HIGHBYTE) >> 8);
+       i->flag |= DST;
+       break;
+ 
+     case 12:
+       i->dst = ((insn & _DECODE_0TO6_HIGHBYTE) >> 8);
+       i->flag |= DST;
+       break;
+ 
+     case 13:
+       i->sub_opcode = ((insn & _DECODE_4TO6_HIGHBYTE) >> 12);
+       i->flag |= SUB_OP;
+       i->src = ((insn & _DECODE_LOWBYTE));
+       i->flag |= SRC;
+       i->fbit = ((insn & _DECODE_GET_F_HIGHBYTE) >> 15);
+       i->flag |= FORMAT;
+       break;
+ 
+     }
+   return;
+ }
