(Resubmission of the previously sent patch with the adjustment to cs/ds acceptance removed.) The previously sent patch for x86-64 corrections to the opcode table wasn't completely applied for some reason. Additionally, I found an inconsistency with the other x86-64 patch that I had sent, and there are also two additions that should be done. This patch tries to address all of this. Built and tested on x86_64-unknown-linux-gnu. Jan gas: 2004-08-02 Jan Beulich * config/tc-i386.c (optimize_imm): Adjust immediates to only those permissible for the selected instruction suffix. (process_suffix): For DefaultSize instructions, suppressing the guessing of a 'q' suffix if the instruction doesn't support it is pointless, because only an 'l' suffix can be guessed in this place. include/opcode: 2004-08-02 Jan Beulich * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves to/from test registers are illegal in 64-bit mode. Add missing NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix (previously one had to explicitly encode a rex64 prefix). Add cmpxchg16b as per Intel's 64-bit documentation. diff -N'aprux*.gmo' -xsid /home/jbeulich/src/binutils/mainline/2004-08-02.10.53/gas/config/tc-i386.c 2004-08-02.10.53-x86_64/gas/config/tc-i386.c --- /home/jbeulich/src/binutils/mainline/2004-08-02.10.53/gas/config/tc-i386.c 2004-07-22 11:48:34.000000000 +0200 +++ 2004-08-02.10.53-x86_64/gas/config/tc-i386.c 2004-07-23 09:35:22.000000000 +0200 @@ -2258,9 +2258,6 @@ process_suffix (void) else if ((i.tm.opcode_modifier & DefaultSize) && !i.suffix) { i.suffix = stackop_size; - if (i.suffix == QWORD_MNEM_SUFFIX - && (i.tm.opcode_modifier & No_qSuf)) - i.suffix = LONG_MNEM_SUFFIX; } /* Change the opcode based on the operand size given by i.suffix; @@ -2547,7 +2544,7 @@ finalize_imm () i.types[0] = overlap0; overlap1 = i.types[1] & i.tm.operand_types[1]; - if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32)) + if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64)) && overlap1 != Imm8 && overlap1 != Imm8S && overlap1 != Imm16 && overlap1 != Imm32S && overlap1 != Imm32 && overlap1 != Imm64) diff -N'aprux*.gmo' -xsid /home/jbeulich/src/binutils/mainline/2004-08-02.10.53/include/opcode/i386.h 2004-08-02.10.53-x86_64/include/opcode/i386.h --- /home/jbeulich/src/binutils/mainline/2004-08-02.10.53/include/opcode/i386.h 2004-08-02 10:52:23.000000000 +0200 +++ 2004-08-02.10.53-x86_64/include/opcode/i386.h 2004-08-02 11:10:14.969127800 +0200 @@ -85,7 +85,7 @@ static const template i386_optab[] = #define MOV_AX_DISP32 0xa0 /* In the 64bit mode the short form mov immediate is redefined to have 64bit displacement value. */ -{ "mov", 2, 0xa0, X, CpuNo64,bwlq_Suf|D|W, { Disp16|Disp32, Acc, 0 } }, +{ "mov", 2, 0xa0, X, CpuNo64,bwl_Suf|D|W, { Disp16|Disp32, Acc, 0 } }, { "mov", 2, 0x88, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, /* In the 64bit mode the short form mov immediate is redefined to have 64bit displacement value. */ @@ -107,7 +107,7 @@ static const template i386_optab[] = { "mov", 2, 0x0f20, X, Cpu64, q_Suf|D|Modrm|IgnoreSize|NoRex64,{ Control, Reg64|InvMem, 0} }, { "mov", 2, 0x0f21, X, Cpu386|CpuNo64, l_Suf|D|Modrm|IgnoreSize,{ Debug, Reg32|InvMem, 0} }, { "mov", 2, 0x0f21, X, Cpu64, q_Suf|D|Modrm|IgnoreSize|NoRex64,{ Debug, Reg64|InvMem, 0} }, -{ "mov", 2, 0x0f24, X, Cpu386, l_Suf|D|Modrm|IgnoreSize, { Test, Reg32|InvMem, 0} }, +{ "mov", 2, 0x0f24, X, Cpu386|CpuNo64, l_Suf|D|Modrm|IgnoreSize, { Test, Reg32|InvMem, 0} }, { "movabs",2, 0xa0, X, Cpu64, bwlq_Suf|D|W, { Disp64, Acc, 0 } }, { "movabs",2, 0xb0, X, Cpu64, q_Suf|W|ShortForm, { Imm64, Reg64, 0 } }, @@ -576,7 +576,7 @@ static const template i386_optab[] = {"sgdt", 1, 0x0f01, 0, Cpu286|CpuNo64, wl_Suf|Modrm, { WordMem, 0, 0} }, {"sgdt", 1, 0x0f01, 0, Cpu64, q_Suf|Modrm|NoRex64, { LLongMem, 0, 0} }, {"sidt", 1, 0x0f01, 1, Cpu286|CpuNo64, wl_Suf|Modrm, { WordMem, 0, 0} }, -{"sidt", 1, 0x0f01, 1, Cpu64, q_Suf|Modrm, { LLongMem, 0, 0} }, +{"sidt", 1, 0x0f01, 1, Cpu64, q_Suf|Modrm|NoRex64, { LLongMem, 0, 0} }, {"sldt", 1, 0x0f00, 0, Cpu286, wlq_Suf|Modrm, { WordReg|InvMem, 0, 0} }, {"sldt", 1, 0x0f00, 0, Cpu286, w_Suf|Modrm|IgnoreSize,{ ShortMem, 0, 0} }, {"smsw", 1, 0x0f01, 4, Cpu286, wlq_Suf|Modrm, { WordReg|InvMem, 0, 0} }, @@ -910,8 +910,8 @@ static const template i386_optab[] = /* Pentium II/Pentium Pro extensions. */ {"sysenter",0, 0x0f34, X, Cpu686, NoSuf, { 0, 0, 0} }, {"sysexit", 0, 0x0f35, X, Cpu686, NoSuf, { 0, 0, 0} }, -{"fxsave", 1, 0x0fae, 0, Cpu686, FP|Modrm, { LLongMem, 0, 0} }, -{"fxrstor", 1, 0x0fae, 1, Cpu686, FP|Modrm, { LLongMem, 0, 0} }, +{"fxsave", 1, 0x0fae, 0, Cpu686, q_Suf|Modrm, { LLongMem, 0, 0} }, +{"fxrstor", 1, 0x0fae, 1, Cpu686, q_Suf|Modrm, { LLongMem, 0, 0} }, {"rdpmc", 0, 0x0f33, X, Cpu686, NoSuf, { 0, 0, 0} }, /* official undefined instr. */ {"ud2", 0, 0x0f0b, X, Cpu686, NoSuf, { 0, 0, 0} }, @@ -1318,6 +1318,7 @@ static const template i386_optab[] = {"addsubpd", 2, 0x660fd0, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, {"addsubps", 2, 0xf20fd0, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpxchg16b",1, 0x0fc7, 1, CpuPNI|Cpu64, NoSuf|Modrm|Rex64, { LLongMem, 0, 0} }, {"fisttp", 1, 0xdf, 1, CpuPNI, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, /* Intel Syntax */ {"fisttpq", 1, 0xdd, 1, CpuPNI, FP|Modrm, { LLongMem, 0, 0} },